gef_sbc310.dts 4.9 KB

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  1. /*
  2. * GE SBC310 Device Tree Source
  3. *
  4. * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. * Based on: SBS CM6 Device Tree Source
  12. * Copyright 2007 SBS Technologies GmbH & Co. KG
  13. * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14. * Copyright 2006 Freescale Semiconductor Inc.
  15. */
  16. /*
  17. * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
  18. */
  19. /include/ "mpc8641si-pre.dtsi"
  20. / {
  21. model = "GEF_SBC310";
  22. compatible = "gef,sbc310";
  23. memory {
  24. device_type = "memory";
  25. reg = <0x0 0x40000000>; // set by uboot
  26. };
  27. lbc: localbus@fef05000 {
  28. reg = <0xfef05000 0x1000>;
  29. ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
  30. 1 0 0xe0000000 0x08000000 // Paged Flash 0
  31. 2 0 0xe8000000 0x08000000 // Paged Flash 1
  32. 3 0 0xfc100000 0x00020000 // NVRAM
  33. 4 0 0xfc000000 0x00010000>; // FPGA
  34. /* flash@0,0 is a mirror of part of the memory in flash@1,0
  35. flash@0,0 {
  36. compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
  37. reg = <0x0 0x0 0x01000000>;
  38. bank-width = <2>;
  39. device-width = <2>;
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. partition@0 {
  43. label = "firmware";
  44. reg = <0x0 0x01000000>;
  45. read-only;
  46. };
  47. };
  48. */
  49. flash@1,0 {
  50. compatible = "gef,sbc310-paged-flash", "cfi-flash";
  51. reg = <0x1 0x0 0x8000000>;
  52. bank-width = <2>;
  53. device-width = <2>;
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. partition@0 {
  57. label = "user";
  58. reg = <0x0 0x7800000>;
  59. };
  60. partition@7800000 {
  61. label = "firmware";
  62. reg = <0x7800000 0x800000>;
  63. read-only;
  64. };
  65. };
  66. nvram@3,0 {
  67. device_type = "nvram";
  68. compatible = "simtek,stk14ca8";
  69. reg = <0x3 0x0 0x20000>;
  70. };
  71. fpga@4,0 {
  72. compatible = "gef,fpga-regs";
  73. reg = <0x4 0x0 0x40>;
  74. };
  75. wdt@4,2000 {
  76. compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
  77. "gef,fpga-wdt";
  78. reg = <0x4 0x2000 0x8>;
  79. interrupts = <0x1a 0x4>;
  80. interrupt-parent = <&gef_pic>;
  81. };
  82. /*
  83. wdt@4,2010 {
  84. compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
  85. "gef,fpga-wdt";
  86. reg = <0x4 0x2010 0x8>;
  87. interrupts = <0x1b 0x4>;
  88. interrupt-parent = <&gef_pic>;
  89. };
  90. */
  91. gef_pic: pic@4,4000 {
  92. #interrupt-cells = <1>;
  93. interrupt-controller;
  94. compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
  95. reg = <0x4 0x4000 0x20>;
  96. interrupts = <0x8 0x9 0 0>;
  97. };
  98. gef_gpio: gpio@4,8000 {
  99. #gpio-cells = <2>;
  100. compatible = "gef,sbc310-gpio";
  101. reg = <0x4 0x8000 0x24>;
  102. gpio-controller;
  103. };
  104. };
  105. soc: soc@fef00000 {
  106. ranges = <0x0 0xfef00000 0x00100000>;
  107. i2c@3000 {
  108. rtc@51 {
  109. compatible = "epson,rx8581";
  110. reg = <0x00000051>;
  111. };
  112. };
  113. i2c@3100 {
  114. hwmon@48 {
  115. compatible = "national,lm92";
  116. reg = <0x48>;
  117. };
  118. hwmon@4c {
  119. compatible = "adi,adt7461";
  120. reg = <0x4c>;
  121. };
  122. eti@6b {
  123. compatible = "dallas,ds1682";
  124. reg = <0x6b>;
  125. };
  126. };
  127. enet0: ethernet@24000 {
  128. tbi-handle = <&tbi0>;
  129. phy-handle = <&phy0>;
  130. phy-connection-type = "gmii";
  131. };
  132. mdio@24520 {
  133. phy0: ethernet-phy@0 {
  134. interrupt-parent = <&gef_pic>;
  135. interrupts = <0x9 0x4>;
  136. reg = <1>;
  137. };
  138. phy2: ethernet-phy@2 {
  139. interrupt-parent = <&gef_pic>;
  140. interrupts = <0x8 0x4>;
  141. reg = <3>;
  142. };
  143. tbi0: tbi-phy@11 {
  144. reg = <0x11>;
  145. device_type = "tbi-phy";
  146. };
  147. };
  148. enet1: ethernet@26000 {
  149. tbi-handle = <&tbi2>;
  150. phy-handle = <&phy2>;
  151. phy-connection-type = "gmii";
  152. };
  153. mdio@26520 {
  154. tbi2: tbi-phy@11 {
  155. reg = <0x11>;
  156. device_type = "tbi-phy";
  157. };
  158. };
  159. enet2: ethernet@25000 {
  160. status = "disabled";
  161. };
  162. mdio@25520 {
  163. status = "disabled";
  164. };
  165. enet3: ethernet@27000 {
  166. status = "disabled";
  167. };
  168. mdio@27520 {
  169. status = "disabled";
  170. };
  171. };
  172. pci0: pcie@fef08000 {
  173. reg = <0xfef08000 0x1000>;
  174. ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
  175. 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
  176. interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
  177. interrupt-map = <
  178. 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
  179. 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
  180. 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
  181. 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
  182. >;
  183. pcie@0 {
  184. ranges = <0x02000000 0x0 0x80000000
  185. 0x02000000 0x0 0x80000000
  186. 0x0 0x40000000
  187. 0x01000000 0x0 0x00000000
  188. 0x01000000 0x0 0x00000000
  189. 0x0 0x00400000>;
  190. };
  191. };
  192. pci1: pcie@fef09000 {
  193. reg = <0xfef09000 0x1000>;
  194. ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
  195. 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
  196. pcie@0 {
  197. ranges = <0x02000000 0x0 0xc0000000
  198. 0x02000000 0x0 0xc0000000
  199. 0x0 0x20000000
  200. 0x01000000 0x0 0x00000000
  201. 0x01000000 0x0 0x00000000
  202. 0x0 0x00400000>;
  203. };
  204. };
  205. };
  206. /include/ "mpc8641si-post.dtsi"