bsc9132si-post.dtsi 5.0 KB

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  1. /*
  2. * BSC9132 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2014 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &ifc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,ifc", "simple-bus";
  38. /* FIXME: Test whether interrupts are split */
  39. interrupts = <16 2 0 0 20 2 0 0>;
  40. };
  41. /* controller at 0xa000 */
  42. &pci0 {
  43. compatible = "fsl,bsc9132-pcie", "fsl,qoriq-pcie-v2.2";
  44. device_type = "pci";
  45. #size-cells = <2>;
  46. #address-cells = <3>;
  47. bus-range = <0 255>;
  48. interrupts = <16 2 0 0>;
  49. pcie@0 {
  50. reg = <0 0 0 0 0>;
  51. #interrupt-cells = <1>;
  52. #size-cells = <2>;
  53. #address-cells = <3>;
  54. device_type = "pci";
  55. interrupts = <16 2 0 0>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0 0x0
  60. 0000 0x0 0x0 0x2 &mpic 0x1 0x2 0x0 0x0
  61. 0000 0x0 0x0 0x3 &mpic 0x2 0x2 0x0 0x0
  62. 0000 0x0 0x0 0x4 &mpic 0x3 0x2 0x0 0x0
  63. >;
  64. };
  65. };
  66. &soc {
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. device_type = "soc";
  70. compatible = "fsl,bsc9132-immr", "simple-bus";
  71. bus-frequency = <0>; // Filled out by uboot.
  72. ecm-law@0 {
  73. compatible = "fsl,ecm-law";
  74. reg = <0x0 0x1000>;
  75. fsl,num-laws = <12>;
  76. };
  77. ecm@1000 {
  78. compatible = "fsl,bsc9132-ecm", "fsl,ecm";
  79. reg = <0x1000 0x1000>;
  80. interrupts = <16 2 0 0>;
  81. };
  82. memory-controller@2000 {
  83. compatible = "fsl,bsc9132-memory-controller";
  84. reg = <0x2000 0x1000>;
  85. interrupts = <16 2 1 8>;
  86. };
  87. /include/ "pq3-i2c-0.dtsi"
  88. i2c@3000 {
  89. interrupts = <17 2 0 0>;
  90. };
  91. /include/ "pq3-i2c-1.dtsi"
  92. i2c@3100 {
  93. interrupts = <17 2 0 0>;
  94. };
  95. /include/ "pq3-duart-0.dtsi"
  96. serial0: serial@4500 {
  97. interrupts = <18 2 0 0>;
  98. };
  99. serial1: serial@4600 {
  100. interrupts = <18 2 0 0 >;
  101. };
  102. /include/ "pq3-espi-0.dtsi"
  103. spi0: spi@7000 {
  104. fsl,espi-num-chipselects = <1>;
  105. interrupts = <22 0x2 0 0>;
  106. };
  107. /include/ "pq3-gpio-0.dtsi"
  108. gpio-controller@f000 {
  109. interrupts = <19 0x2 0 0>;
  110. };
  111. L2: l2-cache-controller@20000 {
  112. compatible = "fsl,bsc9132-l2-cache-controller";
  113. reg = <0x20000 0x1000>;
  114. cache-line-size = <32>; // 32 bytes
  115. cache-size = <0x40000>; // L2,256K
  116. interrupts = <16 2 1 0>;
  117. };
  118. /include/ "pq3-dma-0.dtsi"
  119. dma@21300 {
  120. dma-channel@0 {
  121. interrupts = <62 2 0 0>;
  122. };
  123. dma-channel@80 {
  124. interrupts = <63 2 0 0>;
  125. };
  126. dma-channel@100 {
  127. interrupts = <64 2 0 0>;
  128. };
  129. dma-channel@180 {
  130. interrupts = <65 2 0 0>;
  131. };
  132. };
  133. /include/ "pq3-usb2-dr-0.dtsi"
  134. usb@22000 {
  135. compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
  136. interrupts = <40 0x2 0 0>;
  137. };
  138. /include/ "pq3-esdhc-0.dtsi"
  139. sdhc@2e000 {
  140. fsl,sdhci-auto-cmd12;
  141. interrupts = <41 0x2 0 0>;
  142. };
  143. /include/ "pq3-sec4.4-0.dtsi"
  144. crypto@30000 {
  145. interrupts = <57 2 0 0>;
  146. sec_jr0: jr@1000 {
  147. interrupts = <58 2 0 0>;
  148. };
  149. sec_jr1: jr@2000 {
  150. interrupts = <59 2 0 0>;
  151. };
  152. sec_jr2: jr@3000 {
  153. interrupts = <60 2 0 0>;
  154. };
  155. sec_jr3: jr@4000 {
  156. interrupts = <61 2 0 0>;
  157. };
  158. };
  159. /include/ "pq3-mpic.dtsi"
  160. /include/ "pq3-mpic-timer-B.dtsi"
  161. /include/ "pq3-etsec2-0.dtsi"
  162. enet0: ethernet@b0000 {
  163. queue-group@b0000 {
  164. fsl,rx-bit-map = <0xff>;
  165. fsl,tx-bit-map = <0xff>;
  166. interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
  167. };
  168. };
  169. /include/ "pq3-etsec2-1.dtsi"
  170. enet1: ethernet@b1000 {
  171. queue-group@b1000 {
  172. fsl,rx-bit-map = <0xff>;
  173. fsl,tx-bit-map = <0xff>;
  174. interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
  175. };
  176. };
  177. global-utilities@e0000 {
  178. compatible = "fsl,bsc9132-guts";
  179. reg = <0xe0000 0x1000>;
  180. fsl,has-rstcr;
  181. };
  182. };