digsy_mtc.dts 3.0 KB

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  1. /*
  2. * Digsy MTC board Device Tree Source
  3. *
  4. * Copyright (C) 2009 Semihalf
  5. *
  6. * Based on the CM5200 by M. Balakowicz
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. /include/ "mpc5200b.dtsi"
  14. &gpt0 { gpio-controller; fsl,has-wdt; };
  15. &gpt1 { gpio-controller; };
  16. / {
  17. model = "intercontrol,digsy-mtc";
  18. compatible = "intercontrol,digsy-mtc";
  19. memory {
  20. reg = <0x00000000 0x02000000>; // 32MB
  21. };
  22. soc5200@f0000000 {
  23. rtc@800 {
  24. status = "disabled";
  25. };
  26. spi@f00 {
  27. msp430@0 {
  28. compatible = "spidev";
  29. spi-max-frequency = <32000>;
  30. reg = <0>;
  31. };
  32. };
  33. psc@2000 { // PSC1
  34. status = "disabled";
  35. };
  36. psc@2200 { // PSC2
  37. status = "disabled";
  38. };
  39. psc@2400 { // PSC3
  40. status = "disabled";
  41. };
  42. psc@2600 { // PSC4
  43. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  44. };
  45. psc@2800 { // PSC5
  46. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  47. };
  48. psc@2c00 { // PSC6
  49. status = "disabled";
  50. };
  51. ethernet@3000 {
  52. phy-handle = <&phy0>;
  53. };
  54. mdio@3000 {
  55. phy0: ethernet-phy@0 {
  56. reg = <0>;
  57. };
  58. };
  59. i2c@3d00 {
  60. eeprom@50 {
  61. compatible = "at,24c08";
  62. reg = <0x50>;
  63. };
  64. rtc@56 {
  65. compatible = "mc,rv3029c2";
  66. reg = <0x56>;
  67. };
  68. rtc@68 {
  69. compatible = "dallas,ds1339";
  70. reg = <0x68>;
  71. };
  72. };
  73. i2c@3d40 {
  74. status = "disabled";
  75. };
  76. };
  77. pci@f0000d00 {
  78. interrupt-map-mask = <0xf800 0 0 7>;
  79. interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
  80. 0xc000 0 0 2 &mpc5200_pic 0 0 3
  81. 0xc000 0 0 3 &mpc5200_pic 0 0 3
  82. 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
  83. clock-frequency = <0>; // From boot loader
  84. interrupts = <2 8 0 2 9 0 2 10 0>;
  85. bus-range = <0 0>;
  86. ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
  87. 0x02000000 0 0x90000000 0x90000000 0 0x10000000
  88. 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
  89. };
  90. localbus {
  91. ranges = <0 0 0xff000000 0x1000000
  92. 4 0 0x60000000 0x0001000>;
  93. // 16-bit flash device at LocalPlus Bus CS0
  94. flash@0,0 {
  95. compatible = "cfi-flash";
  96. reg = <0 0 0x1000000>;
  97. bank-width = <2>;
  98. device-width = <2>;
  99. #size-cells = <1>;
  100. #address-cells = <1>;
  101. partition@0 {
  102. label = "kernel";
  103. reg = <0x0 0x00200000>;
  104. };
  105. partition@200000 {
  106. label = "root";
  107. reg = <0x00200000 0x00300000>;
  108. };
  109. partition@500000 {
  110. label = "user";
  111. reg = <0x00500000 0x00a00000>;
  112. };
  113. partition@f00000 {
  114. label = "u-boot";
  115. reg = <0x00f00000 0x100000>;
  116. };
  117. };
  118. can@4,0 {
  119. compatible = "nxp,sja1000";
  120. reg = <4 0x000 0x80>;
  121. nxp,external-clock-frequency = <24000000>;
  122. interrupts = <1 2 3>; // Level-low
  123. };
  124. can@4,100 {
  125. compatible = "nxp,sja1000";
  126. reg = <4 0x100 0x80>;
  127. nxp,external-clock-frequency = <24000000>;
  128. interrupts = <1 2 3>; // Level-low
  129. };
  130. serial@4,200 {
  131. compatible = "nxp,sc28l92";
  132. reg = <4 0x200 0x10>;
  133. interrupts = <1 3 3>;
  134. };
  135. };
  136. };