asp834x-redboot.dts 6.7 KB

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  1. /*
  2. * Analogue & Micro ASP8347 Device Tree Source
  3. *
  4. * Copyright 2008 Codehermit
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "Analogue & Micro ASP8347E";
  14. compatible = "analogue-and-micro,asp8347e";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8347@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>; // from bootloader
  34. bus-frequency = <0>; // from bootloader
  35. clock-frequency = <0>; // from bootloader
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x8000000>; // 128MB at 0
  41. };
  42. localbus@ff005000 {
  43. #address-cells = <2>;
  44. #size-cells = <1>;
  45. compatible = "fsl,mpc8347e-localbus",
  46. "fsl,pq2pro-localbus",
  47. "simple-bus";
  48. reg = <0xff005000 0x1000>;
  49. interrupts = <77 0x8>;
  50. interrupt-parent = <&ipic>;
  51. ranges = <
  52. 0 0 0xf0000000 0x02000000
  53. >;
  54. flash@0,0 {
  55. compatible = "cfi-flash";
  56. reg = <0 0 0x02000000>;
  57. bank-width = <2>;
  58. device-width = <2>;
  59. };
  60. };
  61. soc8349@ff000000 {
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. device_type = "soc";
  65. ranges = <0x0 0xff000000 0x00100000>;
  66. reg = <0xff000000 0x00000200>;
  67. bus-frequency = <0>;
  68. wdt@200 {
  69. device_type = "watchdog";
  70. compatible = "mpc83xx_wdt";
  71. reg = <0x200 0x100>;
  72. };
  73. i2c@3000 {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. cell-index = <0>;
  77. compatible = "fsl-i2c";
  78. reg = <0x3000 0x100>;
  79. interrupts = <14 0x8>;
  80. interrupt-parent = <&ipic>;
  81. dfsrr;
  82. rtc@68 {
  83. compatible = "dallas,ds1374";
  84. reg = <0x68>;
  85. };
  86. };
  87. i2c@3100 {
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. cell-index = <1>;
  91. compatible = "fsl-i2c";
  92. reg = <0x3100 0x100>;
  93. interrupts = <15 0x8>;
  94. interrupt-parent = <&ipic>;
  95. dfsrr;
  96. };
  97. spi@7000 {
  98. cell-index = <0>;
  99. compatible = "fsl,spi";
  100. reg = <0x7000 0x1000>;
  101. interrupts = <16 0x8>;
  102. interrupt-parent = <&ipic>;
  103. mode = "cpu";
  104. };
  105. dma@82a8 {
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
  109. reg = <0x82a8 4>;
  110. ranges = <0 0x8100 0x1a8>;
  111. interrupt-parent = <&ipic>;
  112. interrupts = <71 8>;
  113. cell-index = <0>;
  114. dma-channel@0 {
  115. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  116. reg = <0 0x80>;
  117. cell-index = <0>;
  118. interrupt-parent = <&ipic>;
  119. interrupts = <71 8>;
  120. };
  121. dma-channel@80 {
  122. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  123. reg = <0x80 0x80>;
  124. cell-index = <1>;
  125. interrupt-parent = <&ipic>;
  126. interrupts = <71 8>;
  127. };
  128. dma-channel@100 {
  129. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  130. reg = <0x100 0x80>;
  131. cell-index = <2>;
  132. interrupt-parent = <&ipic>;
  133. interrupts = <71 8>;
  134. };
  135. dma-channel@180 {
  136. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  137. reg = <0x180 0x28>;
  138. cell-index = <3>;
  139. interrupt-parent = <&ipic>;
  140. interrupts = <71 8>;
  141. };
  142. };
  143. /* phy type (ULPI or SERIAL) are only types supported for MPH */
  144. /* port = 0 or 1 */
  145. usb@22000 {
  146. compatible = "fsl-usb2-mph";
  147. reg = <0x22000 0x1000>;
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. interrupt-parent = <&ipic>;
  151. interrupts = <39 0x8>;
  152. phy_type = "ulpi";
  153. port0;
  154. };
  155. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  156. usb@23000 {
  157. compatible = "fsl-usb2-dr";
  158. reg = <0x23000 0x1000>;
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. interrupt-parent = <&ipic>;
  162. interrupts = <38 0x8>;
  163. dr_mode = "otg";
  164. phy_type = "ulpi";
  165. };
  166. enet0: ethernet@24000 {
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. cell-index = <0>;
  170. device_type = "network";
  171. model = "TSEC";
  172. compatible = "gianfar";
  173. reg = <0x24000 0x1000>;
  174. ranges = <0x0 0x24000 0x1000>;
  175. local-mac-address = [ 00 08 e5 11 32 33 ];
  176. interrupts = <32 0x8 33 0x8 34 0x8>;
  177. interrupt-parent = <&ipic>;
  178. tbi-handle = <&tbi0>;
  179. phy-handle = <&phy0>;
  180. linux,network-index = <0>;
  181. mdio@520 {
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. compatible = "fsl,gianfar-mdio";
  185. reg = <0x520 0x20>;
  186. phy0: ethernet-phy@0 {
  187. interrupt-parent = <&ipic>;
  188. interrupts = <17 0x8>;
  189. reg = <0x1>;
  190. };
  191. phy1: ethernet-phy@1 {
  192. interrupt-parent = <&ipic>;
  193. interrupts = <18 0x8>;
  194. reg = <0x2>;
  195. };
  196. tbi0: tbi-phy@11 {
  197. reg = <0x11>;
  198. device_type = "tbi-phy";
  199. };
  200. };
  201. };
  202. enet1: ethernet@25000 {
  203. #address-cells = <1>;
  204. #size-cells = <1>;
  205. cell-index = <1>;
  206. device_type = "network";
  207. model = "TSEC";
  208. compatible = "gianfar";
  209. reg = <0x25000 0x1000>;
  210. ranges = <0x0 0x25000 0x1000>;
  211. local-mac-address = [ 00 08 e5 11 32 34 ];
  212. interrupts = <35 0x8 36 0x8 37 0x8>;
  213. interrupt-parent = <&ipic>;
  214. tbi-handle = <&tbi1>;
  215. phy-handle = <&phy1>;
  216. linux,network-index = <1>;
  217. mdio@520 {
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. compatible = "fsl,gianfar-tbi";
  221. reg = <0x520 0x20>;
  222. tbi1: tbi-phy@11 {
  223. reg = <0x11>;
  224. device_type = "tbi-phy";
  225. };
  226. };
  227. };
  228. serial0: serial@4500 {
  229. cell-index = <0>;
  230. device_type = "serial";
  231. compatible = "fsl,ns16550", "ns16550";
  232. reg = <0x4500 0x100>;
  233. clock-frequency = <400000000>;
  234. interrupts = <9 0x8>;
  235. interrupt-parent = <&ipic>;
  236. };
  237. serial1: serial@4600 {
  238. cell-index = <1>;
  239. device_type = "serial";
  240. compatible = "fsl,ns16550", "ns16550";
  241. reg = <0x4600 0x100>;
  242. clock-frequency = <400000000>;
  243. interrupts = <10 0x8>;
  244. interrupt-parent = <&ipic>;
  245. };
  246. /* May need to remove if on a part without crypto engine */
  247. crypto@30000 {
  248. device_type = "crypto";
  249. model = "SEC2";
  250. compatible = "talitos";
  251. reg = <0x30000 0x10000>;
  252. interrupts = <11 0x8>;
  253. interrupt-parent = <&ipic>;
  254. num-channels = <4>;
  255. channel-fifo-len = <24>;
  256. exec-units-mask = <0x0000007e>;
  257. /* desc mask is for rev2.0,
  258. * we need runtime fixup for >2.0 */
  259. descriptor-types-mask = <0x01010ebf>;
  260. };
  261. /* IPIC
  262. * interrupts cell = <intr #, sense>
  263. * sense values match linux IORESOURCE_IRQ_* defines:
  264. * sense == 8: Level, low assertion
  265. * sense == 2: Edge, high-to-low change
  266. */
  267. ipic: pic@700 {
  268. interrupt-controller;
  269. #address-cells = <0>;
  270. #interrupt-cells = <2>;
  271. reg = <0x700 0x100>;
  272. device_type = "ipic";
  273. };
  274. };
  275. chosen {
  276. bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
  277. linux,stdout-path = &serial0;
  278. };
  279. };