dma.c 6.3 KB

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  1. /*
  2. * OpenRISC Linux
  3. *
  4. * Linux architectural port borrowing liberally from similar works of
  5. * others. All original copyrights apply as per the original source
  6. * declaration.
  7. *
  8. * Modifications for the OpenRISC architecture:
  9. * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  10. * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version
  15. * 2 of the License, or (at your option) any later version.
  16. *
  17. * DMA mapping callbacks...
  18. * As alloc_coherent is the only DMA callback being used currently, that's
  19. * the only thing implemented properly. The rest need looking into...
  20. */
  21. #include <linux/dma-mapping.h>
  22. #include <linux/dma-debug.h>
  23. #include <linux/export.h>
  24. #include <asm/cpuinfo.h>
  25. #include <asm/spr_defs.h>
  26. #include <asm/tlbflush.h>
  27. static int
  28. page_set_nocache(pte_t *pte, unsigned long addr,
  29. unsigned long next, struct mm_walk *walk)
  30. {
  31. unsigned long cl;
  32. pte_val(*pte) |= _PAGE_CI;
  33. /*
  34. * Flush the page out of the TLB so that the new page flags get
  35. * picked up next time there's an access
  36. */
  37. flush_tlb_page(NULL, addr);
  38. /* Flush page out of dcache */
  39. for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo.dcache_block_size)
  40. mtspr(SPR_DCBFR, cl);
  41. return 0;
  42. }
  43. static int
  44. page_clear_nocache(pte_t *pte, unsigned long addr,
  45. unsigned long next, struct mm_walk *walk)
  46. {
  47. pte_val(*pte) &= ~_PAGE_CI;
  48. /*
  49. * Flush the page out of the TLB so that the new page flags get
  50. * picked up next time there's an access
  51. */
  52. flush_tlb_page(NULL, addr);
  53. return 0;
  54. }
  55. /*
  56. * Alloc "coherent" memory, which for OpenRISC means simply uncached.
  57. *
  58. * This function effectively just calls __get_free_pages, sets the
  59. * cache-inhibit bit on those pages, and makes sure that the pages are
  60. * flushed out of the cache before they are used.
  61. *
  62. * If the NON_CONSISTENT attribute is set, then this function just
  63. * returns "normal", cachable memory.
  64. *
  65. * There are additional flags WEAK_ORDERING and WRITE_COMBINE to take
  66. * into consideration here, too. All current known implementations of
  67. * the OR1K support only strongly ordered memory accesses, so that flag
  68. * is being ignored for now; uncached but write-combined memory is a
  69. * missing feature of the OR1K.
  70. */
  71. static void *
  72. or1k_dma_alloc(struct device *dev, size_t size,
  73. dma_addr_t *dma_handle, gfp_t gfp,
  74. unsigned long attrs)
  75. {
  76. unsigned long va;
  77. void *page;
  78. struct mm_walk walk = {
  79. .pte_entry = page_set_nocache,
  80. .mm = &init_mm
  81. };
  82. page = alloc_pages_exact(size, gfp);
  83. if (!page)
  84. return NULL;
  85. /* This gives us the real physical address of the first page. */
  86. *dma_handle = __pa(page);
  87. va = (unsigned long)page;
  88. if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
  89. /*
  90. * We need to iterate through the pages, clearing the dcache for
  91. * them and setting the cache-inhibit bit.
  92. */
  93. if (walk_page_range(va, va + size, &walk)) {
  94. free_pages_exact(page, size);
  95. return NULL;
  96. }
  97. }
  98. return (void *)va;
  99. }
  100. static void
  101. or1k_dma_free(struct device *dev, size_t size, void *vaddr,
  102. dma_addr_t dma_handle, unsigned long attrs)
  103. {
  104. unsigned long va = (unsigned long)vaddr;
  105. struct mm_walk walk = {
  106. .pte_entry = page_clear_nocache,
  107. .mm = &init_mm
  108. };
  109. if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
  110. /* walk_page_range shouldn't be able to fail here */
  111. WARN_ON(walk_page_range(va, va + size, &walk));
  112. }
  113. free_pages_exact(vaddr, size);
  114. }
  115. static dma_addr_t
  116. or1k_map_page(struct device *dev, struct page *page,
  117. unsigned long offset, size_t size,
  118. enum dma_data_direction dir,
  119. unsigned long attrs)
  120. {
  121. unsigned long cl;
  122. dma_addr_t addr = page_to_phys(page) + offset;
  123. switch (dir) {
  124. case DMA_TO_DEVICE:
  125. /* Flush the dcache for the requested range */
  126. for (cl = addr; cl < addr + size;
  127. cl += cpuinfo.dcache_block_size)
  128. mtspr(SPR_DCBFR, cl);
  129. break;
  130. case DMA_FROM_DEVICE:
  131. /* Invalidate the dcache for the requested range */
  132. for (cl = addr; cl < addr + size;
  133. cl += cpuinfo.dcache_block_size)
  134. mtspr(SPR_DCBIR, cl);
  135. break;
  136. default:
  137. /*
  138. * NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
  139. * flush nor invalidate the cache here as the area will need
  140. * to be manually synced anyway.
  141. */
  142. break;
  143. }
  144. return addr;
  145. }
  146. static void
  147. or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
  148. size_t size, enum dma_data_direction dir,
  149. unsigned long attrs)
  150. {
  151. /* Nothing special to do here... */
  152. }
  153. static int
  154. or1k_map_sg(struct device *dev, struct scatterlist *sg,
  155. int nents, enum dma_data_direction dir,
  156. unsigned long attrs)
  157. {
  158. struct scatterlist *s;
  159. int i;
  160. for_each_sg(sg, s, nents, i) {
  161. s->dma_address = or1k_map_page(dev, sg_page(s), s->offset,
  162. s->length, dir, 0);
  163. }
  164. return nents;
  165. }
  166. static void
  167. or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
  168. int nents, enum dma_data_direction dir,
  169. unsigned long attrs)
  170. {
  171. struct scatterlist *s;
  172. int i;
  173. for_each_sg(sg, s, nents, i) {
  174. or1k_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, 0);
  175. }
  176. }
  177. static void
  178. or1k_sync_single_for_cpu(struct device *dev,
  179. dma_addr_t dma_handle, size_t size,
  180. enum dma_data_direction dir)
  181. {
  182. unsigned long cl;
  183. dma_addr_t addr = dma_handle;
  184. /* Invalidate the dcache for the requested range */
  185. for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
  186. mtspr(SPR_DCBIR, cl);
  187. }
  188. static void
  189. or1k_sync_single_for_device(struct device *dev,
  190. dma_addr_t dma_handle, size_t size,
  191. enum dma_data_direction dir)
  192. {
  193. unsigned long cl;
  194. dma_addr_t addr = dma_handle;
  195. /* Flush the dcache for the requested range */
  196. for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
  197. mtspr(SPR_DCBFR, cl);
  198. }
  199. struct dma_map_ops or1k_dma_map_ops = {
  200. .alloc = or1k_dma_alloc,
  201. .free = or1k_dma_free,
  202. .map_page = or1k_map_page,
  203. .unmap_page = or1k_unmap_page,
  204. .map_sg = or1k_map_sg,
  205. .unmap_sg = or1k_unmap_sg,
  206. .sync_single_for_cpu = or1k_sync_single_for_cpu,
  207. .sync_single_for_device = or1k_sync_single_for_device,
  208. };
  209. EXPORT_SYMBOL(or1k_dma_map_ops);
  210. /* Number of entries preallocated for DMA-API debugging */
  211. #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
  212. static int __init dma_init(void)
  213. {
  214. dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
  215. return 0;
  216. }
  217. fs_initcall(dma_init);