interrupts.c 9.5 KB

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  1. /*
  2. * interrupts.c: Interrupt mappings for PNX833X.
  3. *
  4. * Copyright 2008 NXP Semiconductors
  5. * Chris Steel <chris.steel@nxp.com>
  6. * Daniel Laird <daniel.j.laird@nxp.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/irq.h>
  24. #include <linux/hardirq.h>
  25. #include <linux/interrupt.h>
  26. #include <asm/mipsregs.h>
  27. #include <asm/irq_cpu.h>
  28. #include <asm/setup.h>
  29. #include <irq.h>
  30. #include <irq-mapping.h>
  31. #include <gpio.h>
  32. static int mips_cpu_timer_irq;
  33. static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
  34. {
  35. 0, /* unused */
  36. 4, /* PNX833X_PIC_I2C0_INT 1 */
  37. 4, /* PNX833X_PIC_I2C1_INT 2 */
  38. 1, /* PNX833X_PIC_UART0_INT 3 */
  39. 1, /* PNX833X_PIC_UART1_INT 4 */
  40. 6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */
  41. 6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */
  42. 7, /* PNX833X_PIC_GPIO_INT 7 */
  43. 4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */
  44. 5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */
  45. 4, /* PNX833X_PIC_CONFIG_INT 10 */
  46. 4, /* PNX833X_PIC_AOI_INT 11 */
  47. 9, /* PNX833X_PIC_SYNC_INT 12 */
  48. 9, /* PNX8335_PIC_SATA_INT 13 */
  49. 4, /* PNX833X_PIC_OSD_INT 14 */
  50. 9, /* PNX833X_PIC_DISP1_INT 15 */
  51. 4, /* PNX833X_PIC_DEINTERLACER_INT 16 */
  52. 9, /* PNX833X_PIC_DISPLAY2_INT 17 */
  53. 4, /* PNX833X_PIC_VC_INT 18 */
  54. 4, /* PNX833X_PIC_SC_INT 19 */
  55. 9, /* PNX833X_PIC_IDE_INT 20 */
  56. 9, /* PNX833X_PIC_IDE_DMA_INT 21 */
  57. 6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */
  58. 6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */
  59. 4, /* PNX833X_PIC_SGDX_DMA_INT 24 */
  60. 4, /* PNX833X_PIC_TS_OUT_INT 25 */
  61. 4, /* PNX833X_PIC_IR_INT 26 */
  62. 3, /* PNX833X_PIC_VMSP1_INT 27 */
  63. 3, /* PNX833X_PIC_VMSP2_INT 28 */
  64. 4, /* PNX833X_PIC_PIBC_INT 29 */
  65. 4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */
  66. 4, /* PNX833X_PIC_SGDX_TPD_INT 31 */
  67. 5, /* PNX833X_PIC_USB_INT 32 */
  68. 4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */
  69. 4, /* PNX833X_PIC_CLOCK_INT 34 */
  70. 4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */
  71. 4, /* PNX833X_PIC_VMSP_DMA_INT 36 */
  72. #if defined(CONFIG_SOC_PNX8335)
  73. 4, /* PNX8335_PIC_MIU_INT 37 */
  74. 4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */
  75. 9, /* PNX8335_PIC_SYNC_HD_INT 39 */
  76. 9, /* PNX8335_PIC_DISP_HD_INT 40 */
  77. 9, /* PNX8335_PIC_DISP_SCALER_INT 41 */
  78. 4, /* PNX8335_PIC_OSD_HD1_INT 42 */
  79. 4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */
  80. 4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */
  81. 4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */
  82. 4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */
  83. 4, /* PNX8335_PIC_DENC_TTX_INT 47 */
  84. 4, /* PNX8335_PIC_MMI_SIF0_INT 48 */
  85. 4, /* PNX8335_PIC_MMI_SIF1_INT 49 */
  86. 4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */
  87. 4, /* PNX8335_PIC_PIBCS_INT 51 */
  88. 12, /* PNX8335_PIC_ETHERNET_INT 52 */
  89. 3, /* PNX8335_PIC_VMSP1_0_INT 53 */
  90. 3, /* PNX8335_PIC_VMSP1_1_INT 54 */
  91. 4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */
  92. 4, /* PNX8335_PIC_TDGR_DE_INT 56 */
  93. 4, /* PNX8335_PIC_IR1_IRQ_INT 57 */
  94. #endif
  95. };
  96. static void pnx833x_timer_dispatch(void)
  97. {
  98. do_IRQ(mips_cpu_timer_irq);
  99. }
  100. static void pic_dispatch(void)
  101. {
  102. unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
  103. if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
  104. unsigned long priority = PNX833X_PIC_INT_PRIORITY;
  105. PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
  106. if (irq == PNX833X_PIC_GPIO_INT) {
  107. unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
  108. int pin;
  109. while ((pin = ffs(mask & 0xffff))) {
  110. pin -= 1;
  111. do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
  112. mask &= ~(1 << pin);
  113. }
  114. } else {
  115. do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
  116. }
  117. PNX833X_PIC_INT_PRIORITY = priority;
  118. } else {
  119. printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
  120. }
  121. }
  122. asmlinkage void plat_irq_dispatch(void)
  123. {
  124. unsigned int pending = read_c0_status() & read_c0_cause();
  125. if (pending & STATUSF_IP4)
  126. pic_dispatch();
  127. else if (pending & STATUSF_IP7)
  128. do_IRQ(PNX833X_TIMER_IRQ);
  129. else
  130. spurious_interrupt();
  131. }
  132. static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
  133. {
  134. /* Currently we do this by setting IRQ priority to 1.
  135. If priority support is being implemented, 1 should be repalced
  136. by a better value. */
  137. PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
  138. }
  139. static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
  140. {
  141. /* Disable IRQ by writing setting it's priority to 0 */
  142. PNX833X_PIC_INT_REG(irq) = 0;
  143. }
  144. static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock);
  145. static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
  146. {
  147. unsigned long flags;
  148. unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
  149. raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
  150. pnx833x_hard_enable_pic_irq(pic_irq);
  151. raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
  152. return 0;
  153. }
  154. static void pnx833x_enable_pic_irq(struct irq_data *d)
  155. {
  156. unsigned long flags;
  157. unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
  158. raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
  159. pnx833x_hard_enable_pic_irq(pic_irq);
  160. raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
  161. }
  162. static void pnx833x_disable_pic_irq(struct irq_data *d)
  163. {
  164. unsigned long flags;
  165. unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
  166. raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
  167. pnx833x_hard_disable_pic_irq(pic_irq);
  168. raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
  169. }
  170. static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
  171. static void pnx833x_enable_gpio_irq(struct irq_data *d)
  172. {
  173. int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
  174. unsigned long flags;
  175. raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
  176. pnx833x_gpio_enable_irq(pin);
  177. raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
  178. }
  179. static void pnx833x_disable_gpio_irq(struct irq_data *d)
  180. {
  181. int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
  182. unsigned long flags;
  183. raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
  184. pnx833x_gpio_disable_irq(pin);
  185. raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
  186. }
  187. static int pnx833x_set_type_gpio_irq(struct irq_data *d, unsigned int flow_type)
  188. {
  189. int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
  190. int gpio_mode;
  191. switch (flow_type) {
  192. case IRQ_TYPE_EDGE_RISING:
  193. gpio_mode = GPIO_INT_EDGE_RISING;
  194. break;
  195. case IRQ_TYPE_EDGE_FALLING:
  196. gpio_mode = GPIO_INT_EDGE_FALLING;
  197. break;
  198. case IRQ_TYPE_EDGE_BOTH:
  199. gpio_mode = GPIO_INT_EDGE_BOTH;
  200. break;
  201. case IRQ_TYPE_LEVEL_HIGH:
  202. gpio_mode = GPIO_INT_LEVEL_HIGH;
  203. break;
  204. case IRQ_TYPE_LEVEL_LOW:
  205. gpio_mode = GPIO_INT_LEVEL_LOW;
  206. break;
  207. default:
  208. gpio_mode = GPIO_INT_NONE;
  209. break;
  210. }
  211. pnx833x_gpio_setup_irq(gpio_mode, pin);
  212. return 0;
  213. }
  214. static struct irq_chip pnx833x_pic_irq_type = {
  215. .name = "PNX-PIC",
  216. .irq_enable = pnx833x_enable_pic_irq,
  217. .irq_disable = pnx833x_disable_pic_irq,
  218. };
  219. static struct irq_chip pnx833x_gpio_irq_type = {
  220. .name = "PNX-GPIO",
  221. .irq_enable = pnx833x_enable_gpio_irq,
  222. .irq_disable = pnx833x_disable_gpio_irq,
  223. .irq_set_type = pnx833x_set_type_gpio_irq,
  224. };
  225. void __init arch_init_irq(void)
  226. {
  227. unsigned int irq;
  228. /* setup standard internal cpu irqs */
  229. mips_cpu_irq_init();
  230. /* Set IRQ information in irq_desc */
  231. for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
  232. pnx833x_hard_disable_pic_irq(irq);
  233. irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
  234. handle_simple_irq);
  235. }
  236. for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
  237. irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
  238. handle_simple_irq);
  239. /* Set PIC priority limiter register to 0 */
  240. PNX833X_PIC_INT_PRIORITY = 0;
  241. /* Setup GPIO IRQ dispatching */
  242. pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
  243. /* Enable PIC IRQs (HWIRQ2) */
  244. if (cpu_has_vint)
  245. set_vi_handler(4, pic_dispatch);
  246. write_c0_status(read_c0_status() | IE_IRQ2);
  247. }
  248. unsigned int get_c0_compare_int(void)
  249. {
  250. if (cpu_has_vint)
  251. set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
  252. mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
  253. return mips_cpu_timer_irq;
  254. }
  255. void __init plat_time_init(void)
  256. {
  257. /* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
  258. extern unsigned long mips_hpt_frequency;
  259. unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
  260. if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
  261. /* Functional clock is disabled so use crystal frequency */
  262. mips_hpt_frequency = 25;
  263. } else {
  264. #if defined(CONFIG_SOC_PNX8335)
  265. /* Functional clock is enabled, so get clock multiplier */
  266. mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
  267. #else
  268. static const unsigned long int freq[4] = {240, 160, 120, 80};
  269. mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
  270. #endif
  271. }
  272. printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
  273. mips_hpt_frequency *= 500000;
  274. }