bcm63xx_dev_enet.h 2.5 KB

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  1. #ifndef BCM63XX_DEV_ENET_H_
  2. #define BCM63XX_DEV_ENET_H_
  3. #include <linux/if_ether.h>
  4. #include <linux/init.h>
  5. #include <bcm63xx_regs.h>
  6. /*
  7. * on board ethernet platform data
  8. */
  9. struct bcm63xx_enet_platform_data {
  10. char mac_addr[ETH_ALEN];
  11. int has_phy;
  12. /* if has_phy, then set use_internal_phy */
  13. int use_internal_phy;
  14. /* or fill phy info to use an external one */
  15. int phy_id;
  16. int has_phy_interrupt;
  17. int phy_interrupt;
  18. /* if has_phy, use autonegotiated pause parameters or force
  19. * them */
  20. int pause_auto;
  21. int pause_rx;
  22. int pause_tx;
  23. /* if !has_phy, set desired forced speed/duplex */
  24. int force_speed_100;
  25. int force_duplex_full;
  26. /* if !has_phy, set callback to perform mii device
  27. * init/remove */
  28. int (*mii_config)(struct net_device *dev, int probe,
  29. int (*mii_read)(struct net_device *dev,
  30. int phy_id, int reg),
  31. void (*mii_write)(struct net_device *dev,
  32. int phy_id, int reg, int val));
  33. /* DMA channel enable mask */
  34. u32 dma_chan_en_mask;
  35. /* DMA channel interrupt mask */
  36. u32 dma_chan_int_mask;
  37. /* DMA engine has internal SRAM */
  38. bool dma_has_sram;
  39. /* DMA channel register width */
  40. unsigned int dma_chan_width;
  41. /* DMA descriptor shift */
  42. unsigned int dma_desc_shift;
  43. };
  44. /*
  45. * on board ethernet switch platform data
  46. */
  47. #define ENETSW_MAX_PORT 8
  48. #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
  49. #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
  50. #define ENETSW_RGMII_PORT0 4
  51. struct bcm63xx_enetsw_port {
  52. int used;
  53. int phy_id;
  54. int bypass_link;
  55. int force_speed;
  56. int force_duplex_full;
  57. const char *name;
  58. };
  59. struct bcm63xx_enetsw_platform_data {
  60. char mac_addr[ETH_ALEN];
  61. int num_ports;
  62. struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
  63. /* DMA channel enable mask */
  64. u32 dma_chan_en_mask;
  65. /* DMA channel interrupt mask */
  66. u32 dma_chan_int_mask;
  67. /* DMA channel register width */
  68. unsigned int dma_chan_width;
  69. /* DMA engine has internal SRAM */
  70. bool dma_has_sram;
  71. };
  72. int __init bcm63xx_enet_register(int unit,
  73. const struct bcm63xx_enet_platform_data *pd);
  74. int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
  75. enum bcm63xx_regs_enetdmac {
  76. ENETDMAC_CHANCFG,
  77. ENETDMAC_IR,
  78. ENETDMAC_IRMASK,
  79. ENETDMAC_MAXBURST,
  80. ENETDMAC_BUFALLOC,
  81. ENETDMAC_RSTART,
  82. ENETDMAC_FC,
  83. ENETDMAC_LEN,
  84. };
  85. static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
  86. {
  87. extern const unsigned long *bcm63xx_regs_enetdmac;
  88. return bcm63xx_regs_enetdmac[reg];
  89. }
  90. #endif /* ! BCM63XX_DEV_ENET_H_ */