ar9132.dtsi 3.1 KB

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  1. #include <dt-bindings/clock/ath79-clk.h>
  2. / {
  3. compatible = "qca,ar9132";
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. device_type = "cpu";
  11. compatible = "mips,mips24Kc";
  12. clocks = <&pll ATH79_CLK_CPU>;
  13. reg = <0>;
  14. };
  15. };
  16. cpuintc: interrupt-controller {
  17. compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
  18. interrupt-controller;
  19. #interrupt-cells = <1>;
  20. qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
  21. qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
  22. <&ddr_ctrl 0>, <&ddr_ctrl 1>;
  23. };
  24. ahb {
  25. compatible = "simple-bus";
  26. ranges;
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. interrupt-parent = <&cpuintc>;
  30. apb {
  31. compatible = "simple-bus";
  32. ranges;
  33. #address-cells = <1>;
  34. #size-cells = <1>;
  35. interrupt-parent = <&miscintc>;
  36. ddr_ctrl: memory-controller@18000000 {
  37. compatible = "qca,ar9132-ddr-controller",
  38. "qca,ar7240-ddr-controller";
  39. reg = <0x18000000 0x100>;
  40. #qca,ddr-wb-channel-cells = <1>;
  41. };
  42. uart: uart@18020000 {
  43. compatible = "ns8250";
  44. reg = <0x18020000 0x20>;
  45. interrupts = <3>;
  46. clocks = <&pll ATH79_CLK_AHB>;
  47. clock-names = "uart";
  48. reg-io-width = <4>;
  49. reg-shift = <2>;
  50. no-loopback-test;
  51. status = "disabled";
  52. };
  53. gpio: gpio@18040000 {
  54. compatible = "qca,ar9132-gpio",
  55. "qca,ar7100-gpio";
  56. reg = <0x18040000 0x30>;
  57. interrupts = <2>;
  58. ngpios = <22>;
  59. gpio-controller;
  60. #gpio-cells = <2>;
  61. interrupt-controller;
  62. #interrupt-cells = <2>;
  63. };
  64. pll: pll-controller@18050000 {
  65. compatible = "qca,ar9132-pll",
  66. "qca,ar9130-pll";
  67. reg = <0x18050000 0x20>;
  68. clock-names = "ref";
  69. /* The board must provides the ref clock */
  70. #clock-cells = <1>;
  71. clock-output-names = "cpu", "ddr", "ahb";
  72. };
  73. wdt: wdt@18060008 {
  74. compatible = "qca,ar7130-wdt";
  75. reg = <0x18060008 0x8>;
  76. interrupts = <4>;
  77. clocks = <&pll ATH79_CLK_AHB>;
  78. clock-names = "wdt";
  79. };
  80. miscintc: interrupt-controller@18060010 {
  81. compatible = "qca,ar9132-misc-intc",
  82. "qca,ar7100-misc-intc";
  83. reg = <0x18060010 0x8>;
  84. interrupt-parent = <&cpuintc>;
  85. interrupts = <6>;
  86. interrupt-controller;
  87. #interrupt-cells = <1>;
  88. };
  89. rst: reset-controller@1806001c {
  90. compatible = "qca,ar9132-reset",
  91. "qca,ar7100-reset";
  92. reg = <0x1806001c 0x4>;
  93. #reset-cells = <1>;
  94. };
  95. };
  96. usb: usb@1b000100 {
  97. compatible = "qca,ar7100-ehci", "generic-ehci";
  98. reg = <0x1b000100 0x100>;
  99. interrupts = <3>;
  100. resets = <&rst 5>;
  101. has-transaction-translator;
  102. phy-names = "usb";
  103. phys = <&usb_phy>;
  104. status = "disabled";
  105. };
  106. spi: spi@1f000000 {
  107. compatible = "qca,ar9132-spi", "qca,ar7100-spi";
  108. reg = <0x1f000000 0x10>;
  109. clocks = <&pll ATH79_CLK_AHB>;
  110. clock-names = "ahb";
  111. status = "disabled";
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. };
  115. };
  116. usb_phy: usb-phy {
  117. compatible = "qca,ar7100-usb-phy";
  118. reset-names = "usb-phy", "usb-suspend-override";
  119. resets = <&rst 4>, <&rst 3>;
  120. #phy-cells = <0>;
  121. status = "disabled";
  122. };
  123. };