bcm7425.dtsi 10.0 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm7425";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. mips-hpt-frequency = <163125000>;
  9. cpu@0 {
  10. compatible = "brcm,bmips5000";
  11. device_type = "cpu";
  12. reg = <0>;
  13. };
  14. cpu@1 {
  15. compatible = "brcm,bmips5000";
  16. device_type = "cpu";
  17. reg = <1>;
  18. };
  19. };
  20. aliases {
  21. uart0 = &uart0;
  22. };
  23. cpu_intc: interrupt-controller {
  24. #address-cells = <0>;
  25. compatible = "mti,cpu-interrupt-controller";
  26. interrupt-controller;
  27. #interrupt-cells = <1>;
  28. };
  29. clocks {
  30. uart_clk: uart_clk {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <81000000>;
  34. };
  35. upg_clk: upg_clk {
  36. compatible = "fixed-clock";
  37. #clock-cells = <0>;
  38. clock-frequency = <27000000>;
  39. };
  40. };
  41. rdb {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. compatible = "simple-bus";
  45. ranges = <0 0x10000000 0x01000000>;
  46. periph_intc: interrupt-controller@41a400 {
  47. compatible = "brcm,bcm7038-l1-intc";
  48. reg = <0x41a400 0x30>, <0x41a600 0x30>;
  49. interrupt-controller;
  50. #interrupt-cells = <1>;
  51. interrupt-parent = <&cpu_intc>;
  52. interrupts = <2>, <3>;
  53. };
  54. sun_l2_intc: interrupt-controller@403000 {
  55. compatible = "brcm,l2-intc";
  56. reg = <0x403000 0x30>;
  57. interrupt-controller;
  58. #interrupt-cells = <1>;
  59. interrupt-parent = <&periph_intc>;
  60. interrupts = <47>;
  61. };
  62. gisb-arb@400000 {
  63. compatible = "brcm,bcm7400-gisb-arb";
  64. reg = <0x400000 0xdc>;
  65. native-endian;
  66. interrupt-parent = <&sun_l2_intc>;
  67. interrupts = <0>, <2>;
  68. brcm,gisb-arb-master-mask = <0x177b>;
  69. brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
  70. "bsp_0", "rdc_0",
  71. "raaga_0", "avd_1",
  72. "jtag_0", "svd_0",
  73. "vice_0";
  74. };
  75. upg_irq0_intc: interrupt-controller@406780 {
  76. compatible = "brcm,bcm7120-l2-intc";
  77. reg = <0x406780 0x8>;
  78. brcm,int-map-mask = <0x44>, <0x7000000>;
  79. brcm,int-fwd-mask = <0x70000>;
  80. interrupt-controller;
  81. #interrupt-cells = <1>;
  82. interrupt-parent = <&periph_intc>;
  83. interrupts = <55>, <53>;
  84. interrupt-names = "upg_main", "upg_bsc";
  85. };
  86. upg_aon_irq0_intc: interrupt-controller@409480 {
  87. compatible = "brcm,bcm7120-l2-intc";
  88. reg = <0x409480 0x8>;
  89. brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
  90. brcm,int-fwd-mask = <0>;
  91. brcm,irq-can-wake;
  92. interrupt-controller;
  93. #interrupt-cells = <1>;
  94. interrupt-parent = <&periph_intc>;
  95. interrupts = <56>, <54>, <59>;
  96. interrupt-names = "upg_main_aon", "upg_bsc_aon",
  97. "upg_spi";
  98. };
  99. sun_top_ctrl: syscon@404000 {
  100. compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
  101. reg = <0x404000 0x51c>;
  102. native-endian;
  103. };
  104. reboot {
  105. compatible = "brcm,brcmstb-reboot";
  106. syscon = <&sun_top_ctrl 0x304 0x308>;
  107. };
  108. uart0: serial@406b00 {
  109. compatible = "ns16550a";
  110. reg = <0x406b00 0x20>;
  111. reg-io-width = <0x4>;
  112. reg-shift = <0x2>;
  113. interrupt-parent = <&periph_intc>;
  114. interrupts = <61>;
  115. clocks = <&uart_clk>;
  116. status = "disabled";
  117. };
  118. uart1: serial@406b40 {
  119. compatible = "ns16550a";
  120. reg = <0x406b40 0x20>;
  121. reg-io-width = <0x4>;
  122. reg-shift = <0x2>;
  123. interrupt-parent = <&periph_intc>;
  124. interrupts = <62>;
  125. clocks = <&uart_clk>;
  126. status = "disabled";
  127. };
  128. uart2: serial@406b80 {
  129. compatible = "ns16550a";
  130. reg = <0x406b80 0x20>;
  131. reg-io-width = <0x4>;
  132. reg-shift = <0x2>;
  133. interrupt-parent = <&periph_intc>;
  134. interrupts = <63>;
  135. clocks = <&uart_clk>;
  136. status = "disabled";
  137. };
  138. bsca: i2c@409180 {
  139. clock-frequency = <390000>;
  140. compatible = "brcm,brcmstb-i2c";
  141. interrupt-parent = <&upg_aon_irq0_intc>;
  142. reg = <0x409180 0x58>;
  143. interrupts = <27>;
  144. interrupt-names = "upg_bsca";
  145. status = "disabled";
  146. };
  147. bscb: i2c@409400 {
  148. clock-frequency = <390000>;
  149. compatible = "brcm,brcmstb-i2c";
  150. interrupt-parent = <&upg_aon_irq0_intc>;
  151. reg = <0x409400 0x58>;
  152. interrupts = <28>;
  153. interrupt-names = "upg_bscb";
  154. status = "disabled";
  155. };
  156. bscc: i2c@406200 {
  157. clock-frequency = <390000>;
  158. compatible = "brcm,brcmstb-i2c";
  159. interrupt-parent = <&upg_irq0_intc>;
  160. reg = <0x406200 0x58>;
  161. interrupts = <24>;
  162. interrupt-names = "upg_bscc";
  163. status = "disabled";
  164. };
  165. bscd: i2c@406280 {
  166. clock-frequency = <390000>;
  167. compatible = "brcm,brcmstb-i2c";
  168. interrupt-parent = <&upg_irq0_intc>;
  169. reg = <0x406280 0x58>;
  170. interrupts = <25>;
  171. interrupt-names = "upg_bscd";
  172. status = "disabled";
  173. };
  174. bsce: i2c@406300 {
  175. clock-frequency = <390000>;
  176. compatible = "brcm,brcmstb-i2c";
  177. interrupt-parent = <&upg_irq0_intc>;
  178. reg = <0x406300 0x58>;
  179. interrupts = <26>;
  180. interrupt-names = "upg_bsce";
  181. status = "disabled";
  182. };
  183. pwma: pwm@406580 {
  184. compatible = "brcm,bcm7038-pwm";
  185. reg = <0x406580 0x28>;
  186. #pwm-cells = <2>;
  187. clocks = <&upg_clk>;
  188. status = "disabled";
  189. };
  190. pwmb: pwm@406800 {
  191. compatible = "brcm,bcm7038-pwm";
  192. reg = <0x406800 0x28>;
  193. #pwm-cells = <2>;
  194. clocks = <&upg_clk>;
  195. status = "disabled";
  196. };
  197. aon_pm_l2_intc: interrupt-controller@408440 {
  198. compatible = "brcm,l2-intc";
  199. reg = <0x408440 0x30>;
  200. interrupt-controller;
  201. #interrupt-cells = <1>;
  202. interrupt-parent = <&periph_intc>;
  203. interrupts = <49>;
  204. brcm,irq-can-wake;
  205. };
  206. upg_gio: gpio@406700 {
  207. compatible = "brcm,brcmstb-gpio";
  208. reg = <0x406700 0x80>;
  209. #gpio-cells = <2>;
  210. #interrupt-cells = <2>;
  211. gpio-controller;
  212. interrupt-controller;
  213. interrupt-parent = <&upg_irq0_intc>;
  214. interrupts = <6>;
  215. brcm,gpio-bank-widths = <32 32 32 21>;
  216. };
  217. upg_gio_aon: gpio@4094c0 {
  218. compatible = "brcm,brcmstb-gpio";
  219. reg = <0x4094c0 0x40>;
  220. #gpio-cells = <2>;
  221. #interrupt-cells = <2>;
  222. gpio-controller;
  223. interrupt-controller;
  224. interrupt-parent = <&upg_aon_irq0_intc>;
  225. interrupts = <6>;
  226. interrupts-extended = <&upg_aon_irq0_intc 6>,
  227. <&aon_pm_l2_intc 5>;
  228. wakeup-source;
  229. brcm,gpio-bank-widths = <18 4>;
  230. };
  231. enet0: ethernet@b80000 {
  232. phy-mode = "internal";
  233. phy-handle = <&phy1>;
  234. mac-address = [ 00 10 18 36 23 1a ];
  235. compatible = "brcm,genet-v3";
  236. #address-cells = <0x1>;
  237. #size-cells = <0x1>;
  238. reg = <0xb80000 0x11c88>;
  239. interrupts = <17>, <18>;
  240. interrupt-parent = <&periph_intc>;
  241. status = "disabled";
  242. mdio@e14 {
  243. compatible = "brcm,genet-mdio-v3";
  244. #address-cells = <0x1>;
  245. #size-cells = <0x0>;
  246. reg = <0xe14 0x8>;
  247. phy1: ethernet-phy@1 {
  248. max-speed = <100>;
  249. reg = <0x1>;
  250. compatible = "brcm,40nm-ephy",
  251. "ethernet-phy-ieee802.3-c22";
  252. };
  253. };
  254. };
  255. ehci0: usb@480300 {
  256. compatible = "brcm,bcm7425-ehci", "generic-ehci";
  257. reg = <0x480300 0x100>;
  258. native-endian;
  259. interrupt-parent = <&periph_intc>;
  260. interrupts = <65>;
  261. status = "disabled";
  262. };
  263. ohci0: usb@480400 {
  264. compatible = "brcm,bcm7425-ohci", "generic-ohci";
  265. reg = <0x480400 0x100>;
  266. native-endian;
  267. no-big-frame-no;
  268. interrupt-parent = <&periph_intc>;
  269. interrupts = <67>;
  270. status = "disabled";
  271. };
  272. ehci1: usb@480500 {
  273. compatible = "brcm,bcm7425-ehci", "generic-ehci";
  274. reg = <0x480500 0x100>;
  275. native-endian;
  276. interrupt-parent = <&periph_intc>;
  277. interrupts = <66>;
  278. status = "disabled";
  279. };
  280. ohci1: usb@480600 {
  281. compatible = "brcm,bcm7425-ohci", "generic-ohci";
  282. reg = <0x480600 0x100>;
  283. native-endian;
  284. no-big-frame-no;
  285. interrupt-parent = <&periph_intc>;
  286. interrupts = <68>;
  287. status = "disabled";
  288. };
  289. ehci2: usb@490300 {
  290. compatible = "brcm,bcm7425-ehci", "generic-ehci";
  291. reg = <0x490300 0x100>;
  292. native-endian;
  293. interrupt-parent = <&periph_intc>;
  294. interrupts = <70>;
  295. status = "disabled";
  296. };
  297. ohci2: usb@490400 {
  298. compatible = "brcm,bcm7425-ohci", "generic-ohci";
  299. reg = <0x490400 0x100>;
  300. native-endian;
  301. no-big-frame-no;
  302. interrupt-parent = <&periph_intc>;
  303. interrupts = <72>;
  304. status = "disabled";
  305. };
  306. ehci3: usb@490500 {
  307. compatible = "brcm,bcm7425-ehci", "generic-ehci";
  308. reg = <0x490500 0x100>;
  309. native-endian;
  310. interrupt-parent = <&periph_intc>;
  311. interrupts = <71>;
  312. status = "disabled";
  313. };
  314. ohci3: usb@490600 {
  315. compatible = "brcm,bcm7425-ohci", "generic-ohci";
  316. reg = <0x490600 0x100>;
  317. native-endian;
  318. no-big-frame-no;
  319. interrupt-parent = <&periph_intc>;
  320. interrupts = <73>;
  321. status = "disabled";
  322. };
  323. hif_l2_intc: interrupt-controller@41a000 {
  324. compatible = "brcm,l2-intc";
  325. reg = <0x41a000 0x30>;
  326. interrupt-controller;
  327. #interrupt-cells = <1>;
  328. interrupt-parent = <&periph_intc>;
  329. interrupts = <24>;
  330. };
  331. nand: nand@41b800 {
  332. compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
  333. #address-cells = <1>;
  334. #size-cells = <0>;
  335. reg-names = "nand";
  336. reg = <0x41b800 0x400>;
  337. interrupt-parent = <&hif_l2_intc>;
  338. interrupts = <24>;
  339. status = "disabled";
  340. };
  341. sata: sata@181000 {
  342. compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
  343. reg-names = "ahci", "top-ctrl";
  344. reg = <0x181000 0xa9c>, <0x180020 0x1c>;
  345. interrupt-parent = <&periph_intc>;
  346. interrupts = <41>;
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. status = "disabled";
  350. sata0: sata-port@0 {
  351. reg = <0>;
  352. phys = <&sata_phy0>;
  353. };
  354. sata1: sata-port@1 {
  355. reg = <1>;
  356. phys = <&sata_phy1>;
  357. };
  358. };
  359. sata_phy: sata-phy@180100 {
  360. compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
  361. reg = <0x180100 0x0eff>;
  362. reg-names = "phy";
  363. #address-cells = <1>;
  364. #size-cells = <0>;
  365. status = "disabled";
  366. sata_phy0: sata-phy@0 {
  367. reg = <0>;
  368. #phy-cells = <0>;
  369. };
  370. sata_phy1: sata-phy@1 {
  371. reg = <1>;
  372. #phy-cells = <0>;
  373. };
  374. };
  375. sdhci0: sdhci@419000 {
  376. compatible = "brcm,bcm7425-sdhci";
  377. reg = <0x419000 0x100>;
  378. interrupt-parent = <&periph_intc>;
  379. interrupts = <43>;
  380. sd-uhs-sdr50;
  381. mmc-hs200-1_8v;
  382. status = "disabled";
  383. };
  384. sdhci1: sdhci@419200 {
  385. compatible = "brcm,bcm7425-sdhci";
  386. reg = <0x419200 0x100>;
  387. interrupt-parent = <&periph_intc>;
  388. interrupts = <44>;
  389. sd-uhs-sdr50;
  390. mmc-hs200-1_8v;
  391. status = "disabled";
  392. };
  393. };
  394. };