bcm7420.dtsi 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292
  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm7420";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. mips-hpt-frequency = <93750000>;
  9. cpu@0 {
  10. compatible = "brcm,bmips5000";
  11. device_type = "cpu";
  12. reg = <0>;
  13. };
  14. cpu@1 {
  15. compatible = "brcm,bmips5000";
  16. device_type = "cpu";
  17. reg = <1>;
  18. };
  19. };
  20. aliases {
  21. uart0 = &uart0;
  22. };
  23. cpu_intc: interrupt-controller {
  24. #address-cells = <0>;
  25. compatible = "mti,cpu-interrupt-controller";
  26. interrupt-controller;
  27. #interrupt-cells = <1>;
  28. };
  29. clocks {
  30. uart_clk: uart_clk {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <81000000>;
  34. };
  35. upg_clk: upg_clk {
  36. compatible = "fixed-clock";
  37. #clock-cells = <0>;
  38. clock-frequency = <27000000>;
  39. };
  40. };
  41. rdb {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. compatible = "simple-bus";
  45. ranges = <0 0x10000000 0x01000000>;
  46. periph_intc: interrupt-controller@441400 {
  47. compatible = "brcm,bcm7038-l1-intc";
  48. reg = <0x441400 0x30>, <0x441600 0x30>;
  49. interrupt-controller;
  50. #interrupt-cells = <1>;
  51. interrupt-parent = <&cpu_intc>;
  52. interrupts = <2>, <3>;
  53. };
  54. sun_l2_intc: interrupt-controller@401800 {
  55. compatible = "brcm,l2-intc";
  56. reg = <0x401800 0x30>;
  57. interrupt-controller;
  58. #interrupt-cells = <1>;
  59. interrupt-parent = <&periph_intc>;
  60. interrupts = <23>;
  61. };
  62. gisb-arb@400000 {
  63. compatible = "brcm,bcm7400-gisb-arb";
  64. reg = <0x400000 0xdc>;
  65. native-endian;
  66. interrupt-parent = <&sun_l2_intc>;
  67. interrupts = <0>, <2>;
  68. brcm,gisb-arb-master-mask = <0x3ff>;
  69. brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
  70. "pcie_0", "bsp_0", "rdc_0",
  71. "rptd_0", "avd_0", "avd_1",
  72. "jtag_0";
  73. };
  74. upg_irq0_intc: interrupt-controller@406780 {
  75. compatible = "brcm,bcm7120-l2-intc";
  76. reg = <0x406780 0x8>;
  77. brcm,int-map-mask = <0x44>, <0x1f000000>;
  78. brcm,int-fwd-mask = <0x70000>;
  79. interrupt-controller;
  80. #interrupt-cells = <1>;
  81. interrupt-parent = <&periph_intc>;
  82. interrupts = <18>, <19>;
  83. interrupt-names = "upg_main", "upg_bsc";
  84. };
  85. sun_top_ctrl: syscon@404000 {
  86. compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
  87. reg = <0x404000 0x60c>;
  88. native-endian;
  89. };
  90. reboot {
  91. compatible = "brcm,bcm7038-reboot";
  92. syscon = <&sun_top_ctrl 0x8 0x14>;
  93. };
  94. uart0: serial@406b00 {
  95. compatible = "ns16550a";
  96. reg = <0x406b00 0x20>;
  97. reg-io-width = <0x4>;
  98. reg-shift = <0x2>;
  99. interrupt-parent = <&periph_intc>;
  100. interrupts = <21>;
  101. clocks = <&uart_clk>;
  102. status = "disabled";
  103. };
  104. uart1: serial@406b40 {
  105. compatible = "ns16550a";
  106. reg = <0x406b40 0x20>;
  107. reg-io-width = <0x4>;
  108. reg-shift = <0x2>;
  109. interrupt-parent = <&periph_intc>;
  110. interrupts = <64>;
  111. clocks = <&uart_clk>;
  112. status = "disabled";
  113. };
  114. uart2: serial@406b80 {
  115. compatible = "ns16550a";
  116. reg = <0x406b80 0x20>;
  117. reg-io-width = <0x4>;
  118. reg-shift = <0x2>;
  119. interrupt-parent = <&periph_intc>;
  120. interrupts = <65>;
  121. clocks = <&uart_clk>;
  122. status = "disabled";
  123. };
  124. bsca: i2c@406200 {
  125. clock-frequency = <390000>;
  126. compatible = "brcm,brcmstb-i2c";
  127. interrupt-parent = <&upg_irq0_intc>;
  128. reg = <0x406200 0x58>;
  129. interrupts = <24>;
  130. interrupt-names = "upg_bsca";
  131. status = "disabled";
  132. };
  133. bscb: i2c@406280 {
  134. clock-frequency = <390000>;
  135. compatible = "brcm,brcmstb-i2c";
  136. interrupt-parent = <&upg_irq0_intc>;
  137. reg = <0x406280 0x58>;
  138. interrupts = <25>;
  139. interrupt-names = "upg_bscb";
  140. status = "disabled";
  141. };
  142. bscc: i2c@406300 {
  143. clock-frequency = <390000>;
  144. compatible = "brcm,brcmstb-i2c";
  145. interrupt-parent = <&upg_irq0_intc>;
  146. reg = <0x406300 0x58>;
  147. interrupts = <26>;
  148. interrupt-names = "upg_bscc";
  149. status = "disabled";
  150. };
  151. bscd: i2c@406380 {
  152. clock-frequency = <390000>;
  153. compatible = "brcm,brcmstb-i2c";
  154. interrupt-parent = <&upg_irq0_intc>;
  155. reg = <0x406380 0x58>;
  156. interrupts = <27>;
  157. interrupt-names = "upg_bscd";
  158. status = "disabled";
  159. };
  160. bsce: i2c@406800 {
  161. clock-frequency = <390000>;
  162. compatible = "brcm,brcmstb-i2c";
  163. interrupt-parent = <&upg_irq0_intc>;
  164. reg = <0x406800 0x58>;
  165. interrupts = <28>;
  166. interrupt-names = "upg_bsce";
  167. status = "disabled";
  168. };
  169. pwma: pwm@406580 {
  170. compatible = "brcm,bcm7038-pwm";
  171. reg = <0x406580 0x28>;
  172. #pwm-cells = <2>;
  173. clocks = <&upg_clk>;
  174. status = "disabled";
  175. };
  176. pwmb: pwm@406880 {
  177. compatible = "brcm,bcm7038-pwm";
  178. reg = <0x406880 0x28>;
  179. #pwm-cells = <2>;
  180. clocks = <&upg_clk>;
  181. status = "disabled";
  182. };
  183. upg_gio: gpio@406700 {
  184. compatible = "brcm,brcmstb-gpio";
  185. reg = <0x406700 0x80>;
  186. #gpio-cells = <2>;
  187. #interrupt-cells = <2>;
  188. gpio-controller;
  189. interrupt-controller;
  190. interrupt-parent = <&upg_irq0_intc>;
  191. interrupts = <6>;
  192. brcm,gpio-bank-widths = <32 32 32 27>;
  193. };
  194. enet0: ethernet@468000 {
  195. phy-mode = "internal";
  196. phy-handle = <&phy1>;
  197. mac-address = [ 00 10 18 36 23 1a ];
  198. compatible = "brcm,genet-v1";
  199. #address-cells = <0x1>;
  200. #size-cells = <0x1>;
  201. reg = <0x468000 0x3c8c>;
  202. interrupts = <69>, <79>;
  203. interrupt-parent = <&periph_intc>;
  204. status = "disabled";
  205. mdio@e14 {
  206. compatible = "brcm,genet-mdio-v1";
  207. #address-cells = <0x1>;
  208. #size-cells = <0x0>;
  209. reg = <0xe14 0x8>;
  210. phy1: ethernet-phy@1 {
  211. max-speed = <100>;
  212. reg = <0x1>;
  213. compatible = "brcm,65nm-ephy",
  214. "ethernet-phy-ieee802.3-c22";
  215. };
  216. };
  217. };
  218. ehci0: usb@488300 {
  219. compatible = "brcm,bcm7420-ehci", "generic-ehci";
  220. reg = <0x488300 0x100>;
  221. interrupt-parent = <&periph_intc>;
  222. interrupts = <60>;
  223. status = "disabled";
  224. };
  225. ohci0: usb@488400 {
  226. compatible = "brcm,bcm7420-ohci", "generic-ohci";
  227. reg = <0x488400 0x100>;
  228. native-endian;
  229. no-big-frame-no;
  230. interrupt-parent = <&periph_intc>;
  231. interrupts = <61>;
  232. status = "disabled";
  233. };
  234. ehci1: usb@488500 {
  235. compatible = "brcm,bcm7420-ehci", "generic-ehci";
  236. reg = <0x488500 0x100>;
  237. interrupt-parent = <&periph_intc>;
  238. interrupts = <55>;
  239. status = "disabled";
  240. };
  241. ohci1: usb@488600 {
  242. compatible = "brcm,bcm7420-ohci", "generic-ohci";
  243. reg = <0x488600 0x100>;
  244. native-endian;
  245. no-big-frame-no;
  246. interrupt-parent = <&periph_intc>;
  247. interrupts = <62>;
  248. status = "disabled";
  249. };
  250. };
  251. };