bcm7125.dtsi 4.9 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm7125";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. mips-hpt-frequency = <202500000>;
  9. cpu@0 {
  10. compatible = "brcm,bmips4380";
  11. device_type = "cpu";
  12. reg = <0>;
  13. };
  14. cpu@1 {
  15. compatible = "brcm,bmips4380";
  16. device_type = "cpu";
  17. reg = <1>;
  18. };
  19. };
  20. aliases {
  21. uart0 = &uart0;
  22. };
  23. cpu_intc: interrupt-controller {
  24. #address-cells = <0>;
  25. compatible = "mti,cpu-interrupt-controller";
  26. interrupt-controller;
  27. #interrupt-cells = <1>;
  28. };
  29. clocks {
  30. uart_clk: uart_clk {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <81000000>;
  34. };
  35. upg_clk: upg_clk {
  36. compatible = "fixed-clock";
  37. #clock-cells = <0>;
  38. clock-frequency = <27000000>;
  39. };
  40. };
  41. rdb {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. compatible = "simple-bus";
  45. ranges = <0 0x10000000 0x01000000>;
  46. periph_intc: interrupt-controller@441400 {
  47. compatible = "brcm,bcm7038-l1-intc";
  48. reg = <0x441400 0x30>, <0x441600 0x30>;
  49. interrupt-controller;
  50. #interrupt-cells = <1>;
  51. interrupt-parent = <&cpu_intc>;
  52. interrupts = <2>, <3>;
  53. };
  54. sun_l2_intc: interrupt-controller@401800 {
  55. compatible = "brcm,l2-intc";
  56. reg = <0x401800 0x30>;
  57. interrupt-controller;
  58. #interrupt-cells = <1>;
  59. interrupt-parent = <&periph_intc>;
  60. interrupts = <23>;
  61. };
  62. gisb-arb@400000 {
  63. compatible = "brcm,bcm7400-gisb-arb";
  64. reg = <0x400000 0xdc>;
  65. native-endian;
  66. interrupt-parent = <&sun_l2_intc>;
  67. interrupts = <0>, <2>;
  68. brcm,gisb-arb-master-mask = <0x2f7>;
  69. brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
  70. "bsp_0", "rdc_0", "rptd_0",
  71. "avd_0", "jtag_0";
  72. };
  73. upg_irq0_intc: interrupt-controller@406780 {
  74. compatible = "brcm,bcm7120-l2-intc";
  75. reg = <0x406780 0x8>;
  76. brcm,int-map-mask = <0x44>, <0xf000000>;
  77. brcm,int-fwd-mask = <0x70000>;
  78. interrupt-controller;
  79. #interrupt-cells = <1>;
  80. interrupt-parent = <&periph_intc>;
  81. interrupts = <18>, <19>;
  82. interrupt-names = "upg_main", "upg_bsc";
  83. };
  84. sun_top_ctrl: syscon@404000 {
  85. compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
  86. reg = <0x404000 0x60c>;
  87. native-endian;
  88. };
  89. reboot {
  90. compatible = "brcm,bcm7038-reboot";
  91. syscon = <&sun_top_ctrl 0x8 0x14>;
  92. };
  93. uart0: serial@406b00 {
  94. compatible = "ns16550a";
  95. reg = <0x406b00 0x20>;
  96. reg-io-width = <0x4>;
  97. reg-shift = <0x2>;
  98. native-endian;
  99. interrupt-parent = <&periph_intc>;
  100. interrupts = <21>;
  101. clocks = <&uart_clk>;
  102. status = "disabled";
  103. };
  104. uart1: serial@406b40 {
  105. compatible = "ns16550a";
  106. reg = <0x406b40 0x20>;
  107. reg-io-width = <0x4>;
  108. reg-shift = <0x2>;
  109. native-endian;
  110. interrupt-parent = <&periph_intc>;
  111. interrupts = <64>;
  112. clocks = <&uart_clk>;
  113. status = "disabled";
  114. };
  115. uart2: serial@406b80 {
  116. compatible = "ns16550a";
  117. reg = <0x406b80 0x20>;
  118. reg-io-width = <0x4>;
  119. reg-shift = <0x2>;
  120. native-endian;
  121. interrupt-parent = <&periph_intc>;
  122. interrupts = <65>;
  123. clocks = <&uart_clk>;
  124. status = "disabled";
  125. };
  126. bsca: i2c@406200 {
  127. clock-frequency = <390000>;
  128. compatible = "brcm,brcmstb-i2c";
  129. interrupt-parent = <&upg_irq0_intc>;
  130. reg = <0x406200 0x58>;
  131. interrupts = <24>;
  132. interrupt-names = "upg_bsca";
  133. status = "disabled";
  134. };
  135. bscb: i2c@406280 {
  136. clock-frequency = <390000>;
  137. compatible = "brcm,brcmstb-i2c";
  138. interrupt-parent = <&upg_irq0_intc>;
  139. reg = <0x406280 0x58>;
  140. interrupts = <25>;
  141. interrupt-names = "upg_bscb";
  142. status = "disabled";
  143. };
  144. bscc: i2c@406300 {
  145. clock-frequency = <390000>;
  146. compatible = "brcm,brcmstb-i2c";
  147. interrupt-parent = <&upg_irq0_intc>;
  148. reg = <0x406300 0x58>;
  149. interrupts = <26>;
  150. interrupt-names = "upg_bscc";
  151. status = "disabled";
  152. };
  153. bscd: i2c@406380 {
  154. clock-frequency = <390000>;
  155. compatible = "brcm,brcmstb-i2c";
  156. interrupt-parent = <&upg_irq0_intc>;
  157. reg = <0x406380 0x58>;
  158. interrupts = <27>;
  159. interrupt-names = "upg_bscd";
  160. status = "disabled";
  161. };
  162. pwma: pwm@406580 {
  163. compatible = "brcm,bcm7038-pwm";
  164. reg = <0x406580 0x28>;
  165. #pwm-cells = <2>;
  166. clocks = <&upg_clk>;
  167. status = "disabled";
  168. };
  169. upg_gio: gpio@406700 {
  170. compatible = "brcm,brcmstb-gpio";
  171. reg = <0x406700 0x80>;
  172. #gpio-cells = <2>;
  173. #interrupt-cells = <2>;
  174. gpio-controller;
  175. interrupt-controller;
  176. interrupt-parent = <&upg_irq0_intc>;
  177. interrupts = <6>;
  178. brcm,gpio-bank-widths = <32 32 32 18>;
  179. };
  180. ehci0: usb@488300 {
  181. compatible = "brcm,bcm7125-ehci", "generic-ehci";
  182. reg = <0x488300 0x100>;
  183. native-endian;
  184. interrupt-parent = <&periph_intc>;
  185. interrupts = <60>;
  186. status = "disabled";
  187. };
  188. ohci0: usb@488400 {
  189. compatible = "brcm,bcm7125-ohci", "generic-ohci";
  190. reg = <0x488400 0x100>;
  191. native-endian;
  192. interrupt-parent = <&periph_intc>;
  193. interrupts = <61>;
  194. status = "disabled";
  195. };
  196. };
  197. };