bcm3384_zephyr.dtsi 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127
  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm3384", "brcm,bcm33843";
  5. memory@0 {
  6. device_type = "memory";
  7. /* Typical range. The bootloader should fill this in. */
  8. reg = <0x0 0x08000000>;
  9. };
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. /* On BMIPS5000 this is 1/8th of the CPU core clock */
  14. mips-hpt-frequency = <100000000>;
  15. cpu@0 {
  16. compatible = "brcm,bmips5000";
  17. device_type = "cpu";
  18. reg = <0>;
  19. };
  20. cpu@1 {
  21. compatible = "brcm,bmips5000";
  22. device_type = "cpu";
  23. reg = <1>;
  24. };
  25. };
  26. cpu_intc: cpu_intc {
  27. #address-cells = <0>;
  28. compatible = "mti,cpu-interrupt-controller";
  29. interrupt-controller;
  30. #interrupt-cells = <1>;
  31. };
  32. clocks {
  33. periph_clk: periph_clk {
  34. compatible = "fixed-clock";
  35. #clock-cells = <0>;
  36. clock-frequency = <54000000>;
  37. };
  38. };
  39. aliases {
  40. uart0 = &uart0;
  41. };
  42. ubus {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. compatible = "brcm,ubus", "simple-bus";
  46. ranges;
  47. dma-ranges = <0x00000000 0x08000000 0x08000000>,
  48. <0x08000000 0x00000000 0x08000000>;
  49. periph_intc: periph_intc@14e00038 {
  50. compatible = "brcm,bcm3380-l2-intc";
  51. reg = <0x14e00038 0x4 0x14e0003c 0x4>,
  52. <0x14e00340 0x4 0x14e00344 0x4>;
  53. interrupt-controller;
  54. #interrupt-cells = <1>;
  55. interrupt-parent = <&cpu_intc>;
  56. interrupts = <4>;
  57. };
  58. zmips_intc: zmips_intc@104b0060 {
  59. compatible = "brcm,bcm3380-l2-intc";
  60. reg = <0x104b0060 0x4 0x104b0064 0x4>;
  61. interrupt-controller;
  62. #interrupt-cells = <1>;
  63. interrupt-parent = <&periph_intc>;
  64. interrupts = <29>;
  65. brcm,int-map-mask = <0xffffffff>;
  66. };
  67. iop_intc: iop_intc@14e00058 {
  68. compatible = "brcm,bcm3380-l2-intc";
  69. reg = <0x14e00058 0x4 0x14e0005c 0x4>;
  70. interrupt-controller;
  71. #interrupt-cells = <1>;
  72. interrupt-parent = <&cpu_intc>;
  73. interrupts = <6>;
  74. brcm,int-map-mask = <0xffffffff>;
  75. };
  76. uart0: serial@14e00520 {
  77. compatible = "brcm,bcm6345-uart";
  78. reg = <0x14e00520 0x18>;
  79. interrupt-parent = <&periph_intc>;
  80. interrupts = <2>;
  81. clocks = <&periph_clk>;
  82. status = "disabled";
  83. };
  84. ehci0: usb@15400300 {
  85. compatible = "brcm,bcm3384-ehci", "generic-ehci";
  86. reg = <0x15400300 0x100>;
  87. big-endian;
  88. interrupt-parent = <&periph_intc>;
  89. interrupts = <41>;
  90. status = "disabled";
  91. };
  92. ohci0: usb@15400400 {
  93. compatible = "brcm,bcm3384-ohci", "generic-ohci";
  94. reg = <0x15400400 0x100>;
  95. big-endian;
  96. no-big-frame-no;
  97. interrupt-parent = <&periph_intc>;
  98. interrupts = <40>;
  99. status = "disabled";
  100. };
  101. };
  102. };