meson-gxbb.dtsi 15 KB

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  1. /*
  2. * Copyright (c) 2016 Andreas Färber
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This library is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This library is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. #include <dt-bindings/gpio/gpio.h>
  43. #include <dt-bindings/interrupt-controller/irq.h>
  44. #include <dt-bindings/interrupt-controller/arm-gic.h>
  45. #include <dt-bindings/gpio/meson-gxbb-gpio.h>
  46. #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  47. #include <dt-bindings/clock/gxbb-clkc.h>
  48. #include <dt-bindings/clock/gxbb-aoclkc.h>
  49. #include <dt-bindings/reset/gxbb-aoclkc.h>
  50. / {
  51. compatible = "amlogic,meson-gxbb";
  52. interrupt-parent = <&gic>;
  53. #address-cells = <2>;
  54. #size-cells = <2>;
  55. cpus {
  56. #address-cells = <0x2>;
  57. #size-cells = <0x0>;
  58. cpu0: cpu@0 {
  59. device_type = "cpu";
  60. compatible = "arm,cortex-a53", "arm,armv8";
  61. reg = <0x0 0x0>;
  62. enable-method = "psci";
  63. };
  64. cpu1: cpu@1 {
  65. device_type = "cpu";
  66. compatible = "arm,cortex-a53", "arm,armv8";
  67. reg = <0x0 0x1>;
  68. enable-method = "psci";
  69. };
  70. cpu2: cpu@2 {
  71. device_type = "cpu";
  72. compatible = "arm,cortex-a53", "arm,armv8";
  73. reg = <0x0 0x2>;
  74. enable-method = "psci";
  75. };
  76. cpu3: cpu@3 {
  77. device_type = "cpu";
  78. compatible = "arm,cortex-a53", "arm,armv8";
  79. reg = <0x0 0x3>;
  80. enable-method = "psci";
  81. };
  82. };
  83. arm-pmu {
  84. compatible = "arm,cortex-a53-pmu";
  85. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  86. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  87. <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  88. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  89. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  90. };
  91. psci {
  92. compatible = "arm,psci-0.2";
  93. method = "smc";
  94. };
  95. firmware {
  96. sm: secure-monitor {
  97. compatible = "amlogic,meson-gxbb-sm";
  98. };
  99. };
  100. efuse: efuse {
  101. compatible = "amlogic,meson-gxbb-efuse";
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. sn: sn@14 {
  105. reg = <0x14 0x10>;
  106. };
  107. eth_mac: eth_mac@34 {
  108. reg = <0x34 0x10>;
  109. };
  110. bid: bid@46 {
  111. reg = <0x46 0x30>;
  112. };
  113. };
  114. timer {
  115. compatible = "arm,armv8-timer";
  116. interrupts = <GIC_PPI 13
  117. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  118. <GIC_PPI 14
  119. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  120. <GIC_PPI 11
  121. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
  122. <GIC_PPI 10
  123. (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
  124. };
  125. xtal: xtal-clk {
  126. compatible = "fixed-clock";
  127. clock-frequency = <24000000>;
  128. clock-output-names = "xtal";
  129. #clock-cells = <0>;
  130. };
  131. soc {
  132. compatible = "simple-bus";
  133. #address-cells = <2>;
  134. #size-cells = <2>;
  135. ranges;
  136. usb0_phy: phy@c0000000 {
  137. compatible = "amlogic,meson-gxbb-usb2-phy";
  138. #phy-cells = <0>;
  139. reg = <0x0 0xc0000000 0x0 0x20>;
  140. resets = <&reset RESET_USB_OTG>;
  141. clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
  142. clock-names = "usb_general", "usb";
  143. status = "disabled";
  144. };
  145. usb1_phy: phy@c0000020 {
  146. compatible = "amlogic,meson-gxbb-usb2-phy";
  147. #phy-cells = <0>;
  148. reg = <0x0 0xc0000020 0x0 0x20>;
  149. clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
  150. clock-names = "usb_general", "usb";
  151. status = "disabled";
  152. };
  153. cbus: cbus@c1100000 {
  154. compatible = "simple-bus";
  155. reg = <0x0 0xc1100000 0x0 0x100000>;
  156. #address-cells = <2>;
  157. #size-cells = <2>;
  158. ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
  159. reset: reset-controller@4404 {
  160. compatible = "amlogic,meson-gxbb-reset";
  161. reg = <0x0 0x04404 0x0 0x20>;
  162. #reset-cells = <1>;
  163. };
  164. uart_A: serial@84c0 {
  165. compatible = "amlogic,meson-uart";
  166. reg = <0x0 0x84c0 0x0 0x14>;
  167. interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  168. clocks = <&xtal>;
  169. status = "disabled";
  170. };
  171. uart_B: serial@84dc {
  172. compatible = "amlogic,meson-uart";
  173. reg = <0x0 0x84dc 0x0 0x14>;
  174. interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
  175. clocks = <&xtal>;
  176. status = "disabled";
  177. };
  178. pwm_ab: pwm@8550 {
  179. compatible = "amlogic,meson-gxbb-pwm";
  180. reg = <0x0 0x08550 0x0 0x10>;
  181. #pwm-cells = <3>;
  182. status = "disabled";
  183. };
  184. pwm_cd: pwm@8650 {
  185. compatible = "amlogic,meson-gxbb-pwm";
  186. reg = <0x0 0x08650 0x0 0x10>;
  187. #pwm-cells = <3>;
  188. status = "disabled";
  189. };
  190. pwm_ef: pwm@86c0 {
  191. compatible = "amlogic,meson-gxbb-pwm";
  192. reg = <0x0 0x086c0 0x0 0x10>;
  193. #pwm-cells = <3>;
  194. status = "disabled";
  195. };
  196. uart_C: serial@8700 {
  197. compatible = "amlogic,meson-uart";
  198. reg = <0x0 0x8700 0x0 0x14>;
  199. interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
  200. clocks = <&xtal>;
  201. status = "disabled";
  202. };
  203. watchdog@98d0 {
  204. compatible = "amlogic,meson-gxbb-wdt";
  205. reg = <0x0 0x098d0 0x0 0x10>;
  206. clocks = <&xtal>;
  207. };
  208. spifc: spi@8c80 {
  209. compatible = "amlogic,meson-gxbb-spifc";
  210. reg = <0x0 0x08c80 0x0 0x80>;
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. clocks = <&clkc CLKID_SPI>;
  214. status = "disabled";
  215. };
  216. i2c_A: i2c@8500 {
  217. compatible = "amlogic,meson-gxbb-i2c";
  218. reg = <0x0 0x08500 0x0 0x20>;
  219. interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
  220. clocks = <&clkc CLKID_I2C>;
  221. #address-cells = <1>;
  222. #size-cells = <0>;
  223. status = "disabled";
  224. };
  225. i2c_B: i2c@87c0 {
  226. compatible = "amlogic,meson-gxbb-i2c";
  227. reg = <0x0 0x087c0 0x0 0x20>;
  228. interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
  229. clocks = <&clkc CLKID_I2C>;
  230. #address-cells = <1>;
  231. #size-cells = <0>;
  232. status = "disabled";
  233. };
  234. i2c_C: i2c@87e0 {
  235. compatible = "amlogic,meson-gxbb-i2c";
  236. reg = <0x0 0x087e0 0x0 0x20>;
  237. interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
  238. clocks = <&clkc CLKID_I2C>;
  239. #address-cells = <1>;
  240. #size-cells = <0>;
  241. status = "disabled";
  242. };
  243. };
  244. gic: interrupt-controller@c4301000 {
  245. compatible = "arm,gic-400";
  246. reg = <0x0 0xc4301000 0 0x1000>,
  247. <0x0 0xc4302000 0 0x2000>,
  248. <0x0 0xc4304000 0 0x2000>,
  249. <0x0 0xc4306000 0 0x2000>;
  250. interrupt-controller;
  251. interrupts = <GIC_PPI 9
  252. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  253. #interrupt-cells = <3>;
  254. #address-cells = <0>;
  255. };
  256. aobus: aobus@c8100000 {
  257. compatible = "simple-bus";
  258. reg = <0x0 0xc8100000 0x0 0x100000>;
  259. #address-cells = <2>;
  260. #size-cells = <2>;
  261. ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
  262. pinctrl_aobus: pinctrl@14 {
  263. compatible = "amlogic,meson-gxbb-aobus-pinctrl";
  264. #address-cells = <2>;
  265. #size-cells = <2>;
  266. ranges;
  267. gpio_ao: bank@14 {
  268. reg = <0x0 0x00014 0x0 0x8>,
  269. <0x0 0x0002c 0x0 0x4>,
  270. <0x0 0x00024 0x0 0x8>;
  271. reg-names = "mux", "pull", "gpio";
  272. gpio-controller;
  273. #gpio-cells = <2>;
  274. };
  275. uart_ao_a_pins: uart_ao_a {
  276. mux {
  277. groups = "uart_tx_ao_a", "uart_rx_ao_a";
  278. function = "uart_ao";
  279. };
  280. };
  281. remote_input_ao_pins: remote_input_ao {
  282. mux {
  283. groups = "remote_input_ao";
  284. function = "remote_input_ao";
  285. };
  286. };
  287. i2c_ao_pins: i2c_ao {
  288. mux {
  289. groups = "i2c_sck_ao",
  290. "i2c_sda_ao";
  291. function = "i2c_ao";
  292. };
  293. };
  294. pwm_ao_a_3_pins: pwm_ao_a_3 {
  295. mux {
  296. groups = "pwm_ao_a_3";
  297. function = "pwm_ao_a_3";
  298. };
  299. };
  300. pwm_ao_a_6_pins: pwm_ao_a_6 {
  301. mux {
  302. groups = "pwm_ao_a_6";
  303. function = "pwm_ao_a_6";
  304. };
  305. };
  306. pwm_ao_a_12_pins: pwm_ao_a_12 {
  307. mux {
  308. groups = "pwm_ao_a_12";
  309. function = "pwm_ao_a_12";
  310. };
  311. };
  312. pwm_ao_b_pins: pwm_ao_b {
  313. mux {
  314. groups = "pwm_ao_b";
  315. function = "pwm_ao_b";
  316. };
  317. };
  318. };
  319. clkc_AO: clock-controller@040 {
  320. compatible = "amlogic,gxbb-aoclkc";
  321. reg = <0x0 0x00040 0x0 0x4>;
  322. #clock-cells = <1>;
  323. #reset-cells = <1>;
  324. };
  325. uart_AO: serial@4c0 {
  326. compatible = "amlogic,meson-uart";
  327. reg = <0x0 0x004c0 0x0 0x14>;
  328. interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
  329. clocks = <&xtal>;
  330. status = "disabled";
  331. };
  332. ir: ir@580 {
  333. compatible = "amlogic,meson-gxbb-ir";
  334. reg = <0x0 0x00580 0x0 0x40>;
  335. interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
  336. status = "disabled";
  337. };
  338. pwm_ab_AO: pwm@550 {
  339. compatible = "amlogic,meson-gxbb-pwm";
  340. reg = <0x0 0x0550 0x0 0x10>;
  341. #pwm-cells = <3>;
  342. status = "disabled";
  343. };
  344. i2c_AO: i2c@500 {
  345. compatible = "amlogic,meson-gxbb-i2c";
  346. reg = <0x0 0x500 0x0 0x20>;
  347. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  348. clocks = <&clkc CLKID_AO_I2C>;
  349. #address-cells = <1>;
  350. #size-cells = <0>;
  351. status = "disabled";
  352. };
  353. };
  354. periphs: periphs@c8834000 {
  355. compatible = "simple-bus";
  356. reg = <0x0 0xc8834000 0x0 0x2000>;
  357. #address-cells = <2>;
  358. #size-cells = <2>;
  359. ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
  360. rng {
  361. compatible = "amlogic,meson-rng";
  362. reg = <0x0 0x0 0x0 0x4>;
  363. };
  364. pinctrl_periphs: pinctrl@4b0 {
  365. compatible = "amlogic,meson-gxbb-periphs-pinctrl";
  366. #address-cells = <2>;
  367. #size-cells = <2>;
  368. ranges;
  369. gpio: bank@4b0 {
  370. reg = <0x0 0x004b0 0x0 0x28>,
  371. <0x0 0x004e8 0x0 0x14>,
  372. <0x0 0x00120 0x0 0x14>,
  373. <0x0 0x00430 0x0 0x40>;
  374. reg-names = "mux", "pull", "pull-enable", "gpio";
  375. gpio-controller;
  376. #gpio-cells = <2>;
  377. };
  378. emmc_pins: emmc {
  379. mux {
  380. groups = "emmc_nand_d07",
  381. "emmc_cmd",
  382. "emmc_clk";
  383. function = "emmc";
  384. };
  385. };
  386. nor_pins: nor {
  387. mux {
  388. groups = "nor_d",
  389. "nor_q",
  390. "nor_c",
  391. "nor_cs";
  392. function = "nor";
  393. };
  394. };
  395. sdcard_pins: sdcard {
  396. mux {
  397. groups = "sdcard_d0",
  398. "sdcard_d1",
  399. "sdcard_d2",
  400. "sdcard_d3",
  401. "sdcard_cmd",
  402. "sdcard_clk";
  403. function = "sdcard";
  404. };
  405. };
  406. sdio_pins: sdio {
  407. mux {
  408. groups = "sdio_d0",
  409. "sdio_d1",
  410. "sdio_d2",
  411. "sdio_d3",
  412. "sdio_cmd",
  413. "sdio_clk";
  414. function = "sdio";
  415. };
  416. };
  417. sdio_irq_pins: sdio_irq {
  418. mux {
  419. groups = "sdio_irq";
  420. function = "sdio";
  421. };
  422. };
  423. uart_a_pins: uart_a {
  424. mux {
  425. groups = "uart_tx_a",
  426. "uart_rx_a";
  427. function = "uart_a";
  428. };
  429. };
  430. uart_b_pins: uart_b {
  431. mux {
  432. groups = "uart_tx_b",
  433. "uart_rx_b";
  434. function = "uart_b";
  435. };
  436. };
  437. uart_c_pins: uart_c {
  438. mux {
  439. groups = "uart_tx_c",
  440. "uart_rx_c";
  441. function = "uart_c";
  442. };
  443. };
  444. i2c_a_pins: i2c_a {
  445. mux {
  446. groups = "i2c_sck_a",
  447. "i2c_sda_a";
  448. function = "i2c_a";
  449. };
  450. };
  451. i2c_b_pins: i2c_b {
  452. mux {
  453. groups = "i2c_sck_b",
  454. "i2c_sda_b";
  455. function = "i2c_b";
  456. };
  457. };
  458. i2c_c_pins: i2c_c {
  459. mux {
  460. groups = "i2c_sck_c",
  461. "i2c_sda_c";
  462. function = "i2c_c";
  463. };
  464. };
  465. eth_pins: eth_c {
  466. mux {
  467. groups = "eth_mdio",
  468. "eth_mdc",
  469. "eth_clk_rx_clk",
  470. "eth_rx_dv",
  471. "eth_rxd0",
  472. "eth_rxd1",
  473. "eth_rxd2",
  474. "eth_rxd3",
  475. "eth_rgmii_tx_clk",
  476. "eth_tx_en",
  477. "eth_txd0",
  478. "eth_txd1",
  479. "eth_txd2",
  480. "eth_txd3";
  481. function = "eth";
  482. };
  483. };
  484. pwm_a_x_pins: pwm_a_x {
  485. mux {
  486. groups = "pwm_a_x";
  487. function = "pwm_a_x";
  488. };
  489. };
  490. pwm_a_y_pins: pwm_a_y {
  491. mux {
  492. groups = "pwm_a_y";
  493. function = "pwm_a_y";
  494. };
  495. };
  496. pwm_b_pins: pwm_b {
  497. mux {
  498. groups = "pwm_b";
  499. function = "pwm_b";
  500. };
  501. };
  502. pwm_d_pins: pwm_d {
  503. mux {
  504. groups = "pwm_d";
  505. function = "pwm_d";
  506. };
  507. };
  508. pwm_e_pins: pwm_e {
  509. mux {
  510. groups = "pwm_e";
  511. function = "pwm_e";
  512. };
  513. };
  514. pwm_f_x_pins: pwm_f_x {
  515. mux {
  516. groups = "pwm_f_x";
  517. function = "pwm_f_x";
  518. };
  519. };
  520. pwm_f_y_pins: pwm_f_y {
  521. mux {
  522. groups = "pwm_f_y";
  523. function = "pwm_f_y";
  524. };
  525. };
  526. };
  527. };
  528. hiubus: hiubus@c883c000 {
  529. compatible = "simple-bus";
  530. reg = <0x0 0xc883c000 0x0 0x2000>;
  531. #address-cells = <2>;
  532. #size-cells = <2>;
  533. ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
  534. clkc: clock-controller@0 {
  535. compatible = "amlogic,gxbb-clkc";
  536. #clock-cells = <1>;
  537. reg = <0x0 0x0 0x0 0x3db>;
  538. };
  539. mailbox: mailbox@404 {
  540. compatible = "amlogic,meson-gxbb-mhu";
  541. reg = <0 0x404 0 0x4c>;
  542. interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
  543. <0 209 IRQ_TYPE_EDGE_RISING>,
  544. <0 210 IRQ_TYPE_EDGE_RISING>;
  545. #mbox-cells = <1>;
  546. };
  547. };
  548. apb: apb@d0000000 {
  549. compatible = "simple-bus";
  550. reg = <0x0 0xd0000000 0x0 0x200000>;
  551. #address-cells = <2>;
  552. #size-cells = <2>;
  553. ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
  554. };
  555. usb0: usb@c9000000 {
  556. compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  557. reg = <0x0 0xc9000000 0x0 0x40000>;
  558. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  559. clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
  560. clock-names = "otg";
  561. phys = <&usb0_phy>;
  562. phy-names = "usb2-phy";
  563. dr_mode = "host";
  564. status = "disabled";
  565. };
  566. usb1: usb@c9100000 {
  567. compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  568. reg = <0x0 0xc9100000 0x0 0x40000>;
  569. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  570. clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  571. clock-names = "otg";
  572. phys = <&usb1_phy>;
  573. phy-names = "usb2-phy";
  574. dr_mode = "host";
  575. status = "disabled";
  576. };
  577. ethmac: ethernet@c9410000 {
  578. compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
  579. reg = <0x0 0xc9410000 0x0 0x10000
  580. 0x0 0xc8834540 0x0 0x4>;
  581. interrupts = <0 8 1>;
  582. interrupt-names = "macirq";
  583. clocks = <&clkc CLKID_ETH>,
  584. <&clkc CLKID_FCLK_DIV2>,
  585. <&clkc CLKID_MPLL2>;
  586. clock-names = "stmmaceth", "clkin0", "clkin1";
  587. phy-mode = "rgmii";
  588. status = "disabled";
  589. };
  590. };
  591. };