actions-common.c 4.2 KB

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  1. /*
  2. * arch/arm/probes/kprobes/actions-common.c
  3. *
  4. * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
  5. *
  6. * Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is
  7. * Copyright (C) 2006, 2007 Motorola Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/kprobes.h>
  15. #include <asm/opcodes.h>
  16. #include "core.h"
  17. static void __kprobes simulate_ldm1stm1(probes_opcode_t insn,
  18. struct arch_probes_insn *asi,
  19. struct pt_regs *regs)
  20. {
  21. int rn = (insn >> 16) & 0xf;
  22. int lbit = insn & (1 << 20);
  23. int wbit = insn & (1 << 21);
  24. int ubit = insn & (1 << 23);
  25. int pbit = insn & (1 << 24);
  26. long *addr = (long *)regs->uregs[rn];
  27. int reg_bit_vector;
  28. int reg_count;
  29. reg_count = 0;
  30. reg_bit_vector = insn & 0xffff;
  31. while (reg_bit_vector) {
  32. reg_bit_vector &= (reg_bit_vector - 1);
  33. ++reg_count;
  34. }
  35. if (!ubit)
  36. addr -= reg_count;
  37. addr += (!pbit == !ubit);
  38. reg_bit_vector = insn & 0xffff;
  39. while (reg_bit_vector) {
  40. int reg = __ffs(reg_bit_vector);
  41. reg_bit_vector &= (reg_bit_vector - 1);
  42. if (lbit)
  43. regs->uregs[reg] = *addr++;
  44. else
  45. *addr++ = regs->uregs[reg];
  46. }
  47. if (wbit) {
  48. if (!ubit)
  49. addr -= reg_count;
  50. addr -= (!pbit == !ubit);
  51. regs->uregs[rn] = (long)addr;
  52. }
  53. }
  54. static void __kprobes simulate_stm1_pc(probes_opcode_t insn,
  55. struct arch_probes_insn *asi,
  56. struct pt_regs *regs)
  57. {
  58. unsigned long addr = regs->ARM_pc - 4;
  59. regs->ARM_pc = (long)addr + str_pc_offset;
  60. simulate_ldm1stm1(insn, asi, regs);
  61. regs->ARM_pc = (long)addr + 4;
  62. }
  63. static void __kprobes simulate_ldm1_pc(probes_opcode_t insn,
  64. struct arch_probes_insn *asi,
  65. struct pt_regs *regs)
  66. {
  67. simulate_ldm1stm1(insn, asi, regs);
  68. load_write_pc(regs->ARM_pc, regs);
  69. }
  70. static void __kprobes
  71. emulate_generic_r0_12_noflags(probes_opcode_t insn,
  72. struct arch_probes_insn *asi, struct pt_regs *regs)
  73. {
  74. register void *rregs asm("r1") = regs;
  75. register void *rfn asm("lr") = asi->insn_fn;
  76. __asm__ __volatile__ (
  77. "stmdb sp!, {%[regs], r11} \n\t"
  78. "ldmia %[regs], {r0-r12} \n\t"
  79. #if __LINUX_ARM_ARCH__ >= 6
  80. "blx %[fn] \n\t"
  81. #else
  82. "str %[fn], [sp, #-4]! \n\t"
  83. "adr lr, 1f \n\t"
  84. "ldr pc, [sp], #4 \n\t"
  85. "1: \n\t"
  86. #endif
  87. "ldr lr, [sp], #4 \n\t" /* lr = regs */
  88. "stmia lr, {r0-r12} \n\t"
  89. "ldr r11, [sp], #4 \n\t"
  90. : [regs] "=r" (rregs), [fn] "=r" (rfn)
  91. : "0" (rregs), "1" (rfn)
  92. : "r0", "r2", "r3", "r4", "r5", "r6", "r7",
  93. "r8", "r9", "r10", "r12", "memory", "cc"
  94. );
  95. }
  96. static void __kprobes
  97. emulate_generic_r2_14_noflags(probes_opcode_t insn,
  98. struct arch_probes_insn *asi, struct pt_regs *regs)
  99. {
  100. emulate_generic_r0_12_noflags(insn, asi,
  101. (struct pt_regs *)(regs->uregs+2));
  102. }
  103. static void __kprobes
  104. emulate_ldm_r3_15(probes_opcode_t insn,
  105. struct arch_probes_insn *asi, struct pt_regs *regs)
  106. {
  107. emulate_generic_r0_12_noflags(insn, asi,
  108. (struct pt_regs *)(regs->uregs+3));
  109. load_write_pc(regs->ARM_pc, regs);
  110. }
  111. enum probes_insn __kprobes
  112. kprobe_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi,
  113. const struct decode_header *h)
  114. {
  115. probes_insn_handler_t *handler = 0;
  116. unsigned reglist = insn & 0xffff;
  117. int is_ldm = insn & 0x100000;
  118. int rn = (insn >> 16) & 0xf;
  119. if (rn <= 12 && (reglist & 0xe000) == 0) {
  120. /* Instruction only uses registers in the range R0..R12 */
  121. handler = emulate_generic_r0_12_noflags;
  122. } else if (rn >= 2 && (reglist & 0x8003) == 0) {
  123. /* Instruction only uses registers in the range R2..R14 */
  124. rn -= 2;
  125. reglist >>= 2;
  126. handler = emulate_generic_r2_14_noflags;
  127. } else if (rn >= 3 && (reglist & 0x0007) == 0) {
  128. /* Instruction only uses registers in the range R3..R15 */
  129. if (is_ldm && (reglist & 0x8000)) {
  130. rn -= 3;
  131. reglist >>= 3;
  132. handler = emulate_ldm_r3_15;
  133. }
  134. }
  135. if (handler) {
  136. /* We can emulate the instruction in (possibly) modified form */
  137. asi->insn[0] = __opcode_to_mem_arm((insn & 0xfff00000) |
  138. (rn << 16) | reglist);
  139. asi->insn_handler = handler;
  140. return INSN_GOOD;
  141. }
  142. /* Fallback to slower simulation... */
  143. if (reglist & 0x8000)
  144. handler = is_ldm ? simulate_ldm1_pc : simulate_stm1_pc;
  145. else
  146. handler = simulate_ldm1stm1;
  147. asi->insn_handler = handler;
  148. return INSN_GOOD_NO_SLOT;
  149. }