adma.c 5.1 KB

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  1. /*
  2. * platform device definitions for the iop3xx dma/xor engines
  3. * Copyright © 2006, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. #include <linux/platform_device.h>
  20. #include <asm/hardware/iop3xx.h>
  21. #include <linux/dma-mapping.h>
  22. #include <mach/adma.h>
  23. #include <asm/hardware/iop_adma.h>
  24. #ifdef CONFIG_ARCH_IOP32X
  25. #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
  26. #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
  27. #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
  28. #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
  29. #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
  30. #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
  31. #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
  32. #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
  33. #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
  34. #endif
  35. #ifdef CONFIG_ARCH_IOP33X
  36. #define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
  37. #define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
  38. #define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
  39. #define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
  40. #define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
  41. #define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
  42. #define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
  43. #define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
  44. #define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
  45. #endif
  46. /* AAU and DMA Channels */
  47. static struct resource iop3xx_dma_0_resources[] = {
  48. [0] = {
  49. .start = IOP3XX_DMA_PHYS_BASE(0),
  50. .end = IOP3XX_DMA_UPPER_PA(0),
  51. .flags = IORESOURCE_MEM,
  52. },
  53. [1] = {
  54. .start = IRQ_DMA0_EOT,
  55. .end = IRQ_DMA0_EOT,
  56. .flags = IORESOURCE_IRQ
  57. },
  58. [2] = {
  59. .start = IRQ_DMA0_EOC,
  60. .end = IRQ_DMA0_EOC,
  61. .flags = IORESOURCE_IRQ
  62. },
  63. [3] = {
  64. .start = IRQ_DMA0_ERR,
  65. .end = IRQ_DMA0_ERR,
  66. .flags = IORESOURCE_IRQ
  67. }
  68. };
  69. static struct resource iop3xx_dma_1_resources[] = {
  70. [0] = {
  71. .start = IOP3XX_DMA_PHYS_BASE(1),
  72. .end = IOP3XX_DMA_UPPER_PA(1),
  73. .flags = IORESOURCE_MEM,
  74. },
  75. [1] = {
  76. .start = IRQ_DMA1_EOT,
  77. .end = IRQ_DMA1_EOT,
  78. .flags = IORESOURCE_IRQ
  79. },
  80. [2] = {
  81. .start = IRQ_DMA1_EOC,
  82. .end = IRQ_DMA1_EOC,
  83. .flags = IORESOURCE_IRQ
  84. },
  85. [3] = {
  86. .start = IRQ_DMA1_ERR,
  87. .end = IRQ_DMA1_ERR,
  88. .flags = IORESOURCE_IRQ
  89. }
  90. };
  91. static struct resource iop3xx_aau_resources[] = {
  92. [0] = {
  93. .start = IOP3XX_AAU_PHYS_BASE,
  94. .end = IOP3XX_AAU_UPPER_PA,
  95. .flags = IORESOURCE_MEM,
  96. },
  97. [1] = {
  98. .start = IRQ_AA_EOT,
  99. .end = IRQ_AA_EOT,
  100. .flags = IORESOURCE_IRQ
  101. },
  102. [2] = {
  103. .start = IRQ_AA_EOC,
  104. .end = IRQ_AA_EOC,
  105. .flags = IORESOURCE_IRQ
  106. },
  107. [3] = {
  108. .start = IRQ_AA_ERR,
  109. .end = IRQ_AA_ERR,
  110. .flags = IORESOURCE_IRQ
  111. }
  112. };
  113. static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
  114. static struct iop_adma_platform_data iop3xx_dma_0_data = {
  115. .hw_id = DMA0_ID,
  116. .pool_size = PAGE_SIZE,
  117. };
  118. static struct iop_adma_platform_data iop3xx_dma_1_data = {
  119. .hw_id = DMA1_ID,
  120. .pool_size = PAGE_SIZE,
  121. };
  122. static struct iop_adma_platform_data iop3xx_aau_data = {
  123. .hw_id = AAU_ID,
  124. .pool_size = 3 * PAGE_SIZE,
  125. };
  126. struct platform_device iop3xx_dma_0_channel = {
  127. .name = "iop-adma",
  128. .id = 0,
  129. .num_resources = 4,
  130. .resource = iop3xx_dma_0_resources,
  131. .dev = {
  132. .dma_mask = &iop3xx_adma_dmamask,
  133. .coherent_dma_mask = DMA_BIT_MASK(64),
  134. .platform_data = (void *) &iop3xx_dma_0_data,
  135. },
  136. };
  137. struct platform_device iop3xx_dma_1_channel = {
  138. .name = "iop-adma",
  139. .id = 1,
  140. .num_resources = 4,
  141. .resource = iop3xx_dma_1_resources,
  142. .dev = {
  143. .dma_mask = &iop3xx_adma_dmamask,
  144. .coherent_dma_mask = DMA_BIT_MASK(64),
  145. .platform_data = (void *) &iop3xx_dma_1_data,
  146. },
  147. };
  148. struct platform_device iop3xx_aau_channel = {
  149. .name = "iop-adma",
  150. .id = 2,
  151. .num_resources = 4,
  152. .resource = iop3xx_aau_resources,
  153. .dev = {
  154. .dma_mask = &iop3xx_adma_dmamask,
  155. .coherent_dma_mask = DMA_BIT_MASK(64),
  156. .platform_data = (void *) &iop3xx_aau_data,
  157. },
  158. };
  159. static int __init iop3xx_adma_cap_init(void)
  160. {
  161. #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
  162. dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
  163. dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
  164. #else
  165. dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
  166. dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
  167. #endif
  168. #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
  169. dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
  170. dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
  171. #else
  172. dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
  173. dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
  174. #endif
  175. #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
  176. dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
  177. dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
  178. #else
  179. dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
  180. dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
  181. dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
  182. #endif
  183. return 0;
  184. }
  185. arch_initcall(iop3xx_adma_cap_init);