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arm
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mach-s3c24xx
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regs-mem.h

regs-mem.h 1.7 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
    3. 

  3.  *		http://www.simtec.co.uk/products/SWLINUX/
    4. 

  4.  *
    5. 

  5.  * This program is free software; you can redistribute it and/or modify
    6. 

  6.  * it under the terms of the GNU General Public License version 2 as
    7. 

  7.  * published by the Free Software Foundation.
    8. 

  8.  *
    9. 

  9.  * S3C2410 Memory Control register definitions
    10. 

  10.  */
    11. 

  11. 

  12. #ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
    13. 

  13. #define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
    14. 

  14. 

  15. #define S3C2410_MEMREG(x)		(S3C24XX_VA_MEMCTRL + (x))
    16. 

  16. 

  17. #define S3C2410_BWSCON			S3C2410_MEMREG(0x00)
    18. 

  18. #define S3C2410_BANKCON0		S3C2410_MEMREG(0x04)
    19. 

  19. #define S3C2410_BANKCON1		S3C2410_MEMREG(0x08)
    20. 

  20. #define S3C2410_BANKCON2		S3C2410_MEMREG(0x0C)
    21. 

  21. #define S3C2410_BANKCON3		S3C2410_MEMREG(0x10)
    22. 

  22. #define S3C2410_BANKCON4		S3C2410_MEMREG(0x14)
    23. 

  23. #define S3C2410_BANKCON5		S3C2410_MEMREG(0x18)
    24. 

  24. #define S3C2410_BANKCON6		S3C2410_MEMREG(0x1C)
    25. 

  25. #define S3C2410_BANKCON7		S3C2410_MEMREG(0x20)
    26. 

  26. #define S3C2410_REFRESH			S3C2410_MEMREG(0x24)
    27. 

  27. #define S3C2410_BANKSIZE		S3C2410_MEMREG(0x28)
    28. 

  28. 

  29. #define S3C2410_BWSCON_ST1		(1 << 7)
    30. 

  30. #define S3C2410_BWSCON_ST2		(1 << 11)
    31. 

  31. #define S3C2410_BWSCON_ST3		(1 << 15)
    32. 

  32. #define S3C2410_BWSCON_ST4		(1 << 19)
    33. 

  33. #define S3C2410_BWSCON_ST5		(1 << 23)
    34. 

  34. 

  35. #define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
    36. 

  36. 

  37. #define S3C2410_BWSCON_WS		(1 << 2)
    38. 

  38. 

  39. #define S3C2410_BANKCON_PMC16		(0x3)
    40. 

  40. 

  41. #define S3C2410_BANKCON_Tacp_SHIFT	(2)
    42. 

  42. #define S3C2410_BANKCON_Tcah_SHIFT	(4)
    43. 

  43. #define S3C2410_BANKCON_Tcoh_SHIFT	(6)
    44. 

  44. #define S3C2410_BANKCON_Tacc_SHIFT	(8)
    45. 

  45. #define S3C2410_BANKCON_Tcos_SHIFT	(11)
    46. 

  46. #define S3C2410_BANKCON_Tacs_SHIFT	(13)
    47. 

  47. 

  48. #define S3C2410_BANKCON_SDRAM		(0x3 << 15)
    49. 

  49. 

  50. #define S3C2410_REFRESH_SELF		(1 << 22)
    51. 

  51. 

  52. #define S3C2410_BANKSIZE_MASK		(0x7 << 0)
    53. 

  53. 

  54. #endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */
    55. 

  55.