vfpmacros.h 2.1 KB

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  1. /*
  2. * arch/arm/include/asm/vfpmacros.h
  3. *
  4. * Assembler-only file containing VFP macros and register definitions.
  5. */
  6. #include <asm/hwcap.h>
  7. #include <asm/vfp.h>
  8. @ Macros to allow building with old toolkits (with no VFP support)
  9. .macro VFPFMRX, rd, sysreg, cond
  10. MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg
  11. .endm
  12. .macro VFPFMXR, sysreg, rd, cond
  13. MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
  14. .endm
  15. @ read all the working registers back into the VFP
  16. .macro VFPFLDMIA, base, tmp
  17. #if __LINUX_ARM_ARCH__ < 6
  18. LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
  19. #else
  20. LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
  21. #endif
  22. #ifdef CONFIG_VFPv3
  23. #if __LINUX_ARM_ARCH__ <= 6
  24. ldr \tmp, =elf_hwcap @ may not have MVFR regs
  25. ldr \tmp, [\tmp, #0]
  26. tst \tmp, #HWCAP_VFPD32
  27. ldcnel p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
  28. addeq \base, \base, #32*4 @ step over unused register space
  29. #else
  30. VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
  31. and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
  32. cmp \tmp, #2 @ 32 x 64bit registers?
  33. ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
  34. addne \base, \base, #32*4 @ step over unused register space
  35. #endif
  36. #endif
  37. .endm
  38. @ write all the working registers out of the VFP
  39. .macro VFPFSTMIA, base, tmp
  40. #if __LINUX_ARM_ARCH__ < 6
  41. STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
  42. #else
  43. STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
  44. #endif
  45. #ifdef CONFIG_VFPv3
  46. #if __LINUX_ARM_ARCH__ <= 6
  47. ldr \tmp, =elf_hwcap @ may not have MVFR regs
  48. ldr \tmp, [\tmp, #0]
  49. tst \tmp, #HWCAP_VFPD32
  50. stcnel p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
  51. addeq \base, \base, #32*4 @ step over unused register space
  52. #else
  53. VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
  54. and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
  55. cmp \tmp, #2 @ 32 x 64bit registers?
  56. stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
  57. addne \base, \base, #32*4 @ step over unused register space
  58. #endif
  59. #endif
  60. .endm