cpufreq-dt.txt 1.5 KB

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  1. Generic cpufreq driver
  2. It is a generic DT based cpufreq driver for frequency management. It supports
  3. both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
  4. clock and voltage across all CPUs.
  5. Both required and optional properties listed below must be defined
  6. under node /cpus/cpu@0.
  7. Required properties:
  8. - None
  9. Optional properties:
  10. - operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt for
  11. details. OPPs *must* be supplied either via DT, i.e. this property, or
  12. populated at runtime.
  13. - clock-latency: Specify the possible maximum transition latency for clock,
  14. in unit of nanoseconds.
  15. - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
  16. - #cooling-cells:
  17. - cooling-min-level:
  18. - cooling-max-level:
  19. Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
  20. Examples:
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. compatible = "arm,cortex-a9";
  26. reg = <0>;
  27. next-level-cache = <&L2>;
  28. operating-points = <
  29. /* kHz uV */
  30. 792000 1100000
  31. 396000 950000
  32. 198000 850000
  33. >;
  34. clock-latency = <61036>; /* two CLK32 periods */
  35. #cooling-cells = <2>;
  36. cooling-min-level = <0>;
  37. cooling-max-level = <2>;
  38. };
  39. cpu@1 {
  40. compatible = "arm,cortex-a9";
  41. reg = <1>;
  42. next-level-cache = <&L2>;
  43. };
  44. cpu@2 {
  45. compatible = "arm,cortex-a9";
  46. reg = <2>;
  47. next-level-cache = <&L2>;
  48. };
  49. cpu@3 {
  50. compatible = "arm,cortex-a9";
  51. reg = <3>;
  52. next-level-cache = <&L2>;
  53. };
  54. };