arm_big_little_dt.txt 1.4 KB

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  1. Generic ARM big LITTLE cpufreq driver's DT glue
  2. -----------------------------------------------
  3. This is DT specific glue layer for generic cpufreq driver for big LITTLE
  4. systems.
  5. Both required and optional properties listed below must be defined
  6. under node /cpus/cpu@x. Where x is the first cpu inside a cluster.
  7. FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster
  8. must be present contiguously. Generic DT driver will check only node 'x' for
  9. cpu:x.
  10. Required properties:
  11. - operating-points: Refer to Documentation/devicetree/bindings/opp/opp.txt
  12. for details
  13. Optional properties:
  14. - clock-latency: Specify the possible maximum transition latency for clock,
  15. in unit of nanoseconds.
  16. Examples:
  17. cpus {
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. cpu@0 {
  21. compatible = "arm,cortex-a15";
  22. reg = <0>;
  23. next-level-cache = <&L2>;
  24. operating-points = <
  25. /* kHz uV */
  26. 792000 1100000
  27. 396000 950000
  28. 198000 850000
  29. >;
  30. clock-latency = <61036>; /* two CLK32 periods */
  31. };
  32. cpu@1 {
  33. compatible = "arm,cortex-a15";
  34. reg = <1>;
  35. next-level-cache = <&L2>;
  36. };
  37. cpu@100 {
  38. compatible = "arm,cortex-a7";
  39. reg = <100>;
  40. next-level-cache = <&L2>;
  41. operating-points = <
  42. /* kHz uV */
  43. 792000 950000
  44. 396000 750000
  45. 198000 450000
  46. >;
  47. clock-latency = <61036>; /* two CLK32 periods */
  48. };
  49. cpu@101 {
  50. compatible = "arm,cortex-a7";
  51. reg = <101>;
  52. next-level-cache = <&L2>;
  53. };
  54. };