marvell,berlin.txt 2.9 KB

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  1. Marvell Berlin SoC Family Device Tree Bindings
  2. ---------------------------------------------------------------
  3. Work in progress statement:
  4. Device tree files and bindings applying to Marvell Berlin SoCs and boards are
  5. considered "unstable". Any Marvell Berlin device tree binding may change at any
  6. time. Be sure to use a device tree binary and a kernel image generated from the
  7. same source tree.
  8. Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
  9. stable binding/ABI.
  10. ---------------------------------------------------------------
  11. Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
  12. shall have the following properties:
  13. * Required root node properties:
  14. compatible: must contain "marvell,berlin"
  15. In addition, the above compatible shall be extended with the specific
  16. SoC and board used. Currently known SoC compatibles are:
  17. "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
  18. "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
  19. "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
  20. "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
  21. "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
  22. * Example:
  23. / {
  24. model = "Sony NSZ-GS7";
  25. compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
  26. ...
  27. }
  28. * Marvell Berlin CPU control bindings
  29. CPU control register allows various operations on CPUs, like resetting them
  30. independently.
  31. Required properties:
  32. - compatible: should be "marvell,berlin-cpu-ctrl"
  33. - reg: address and length of the register set
  34. Example:
  35. cpu-ctrl@f7dd0000 {
  36. compatible = "marvell,berlin-cpu-ctrl";
  37. reg = <0xf7dd0000 0x10000>;
  38. };
  39. * Marvell Berlin2 chip control binding
  40. Marvell Berlin SoCs have a chip control register set providing several
  41. individual registers dealing with pinmux, padmux, clock, reset, and secondary
  42. CPU boot address. Unfortunately, the individual registers are spread among the
  43. chip control registers, so there should be a single DT node only providing the
  44. different functions which are described below.
  45. Required properties:
  46. - compatible:
  47. * the first and second values must be:
  48. "simple-mfd", "syscon"
  49. - reg: address and length of following register sets for
  50. BG2/BG2CD: chip control register set
  51. BG2Q: chip control register set and cpu pll registers
  52. * Marvell Berlin2 system control binding
  53. Marvell Berlin SoCs have a system control register set providing several
  54. individual registers dealing with pinmux, padmux, and reset.
  55. Required properties:
  56. - compatible:
  57. * the first and second values must be:
  58. "simple-mfd", "syscon"
  59. - reg: address and length of the system control register set
  60. Example:
  61. chip: chip-control@ea0000 {
  62. compatible = "simple-mfd", "syscon";
  63. reg = <0xea0000 0x400>;
  64. /* sub-device nodes */
  65. };
  66. sysctrl: system-controller@d000 {
  67. compatible = "simple-mfd", "syscon";
  68. reg = <0xd000 0x100>;
  69. /* sub-device nodes */
  70. };