silicon-errata.txt 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869
  1. Silicon Errata and Software Workarounds
  2. =======================================
  3. Author: Will Deacon <will.deacon@arm.com>
  4. Date : 27 November 2015
  5. It is an unfortunate fact of life that hardware is often produced with
  6. so-called "errata", which can cause it to deviate from the architecture
  7. under specific circumstances. For hardware produced by ARM, these
  8. errata are broadly classified into the following categories:
  9. Category A: A critical error without a viable workaround.
  10. Category B: A significant or critical error with an acceptable
  11. workaround.
  12. Category C: A minor error that is not expected to occur under normal
  13. operation.
  14. For more information, consult one of the "Software Developers Errata
  15. Notice" documents available on infocenter.arm.com (registration
  16. required).
  17. As far as Linux is concerned, Category B errata may require some special
  18. treatment in the operating system. For example, avoiding a particular
  19. sequence of code, or configuring the processor in a particular way. A
  20. less common situation may require similar actions in order to declassify
  21. a Category A erratum into a Category C erratum. These are collectively
  22. known as "software workarounds" and are only required in the minority of
  23. cases (e.g. those cases that both require a non-secure workaround *and*
  24. can be triggered by Linux).
  25. For software workarounds that may adversely impact systems unaffected by
  26. the erratum in question, a Kconfig entry is added under "Kernel
  27. Features" -> "ARM errata workarounds via the alternatives framework".
  28. These are enabled by default and patched in at runtime when an affected
  29. CPU is detected. For less-intrusive workarounds, a Kconfig option is not
  30. available and the code is structured (preferably with a comment) in such
  31. a way that the erratum will not be hit.
  32. This approach can make it slightly onerous to determine exactly which
  33. errata are worked around in an arbitrary kernel source tree, so this
  34. file acts as a registry of software workarounds in the Linux Kernel and
  35. will be updated when new workarounds are committed and backported to
  36. stable kernels.
  37. | Implementor | Component | Erratum ID | Kconfig |
  38. +----------------+-----------------+-----------------+-----------------------------+
  39. | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
  40. | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
  41. | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
  42. | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
  43. | ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
  44. | ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
  45. | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
  46. | ARM | Cortex-A57 | #852523 | N/A |
  47. | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
  48. | ARM | Cortex-A72 | #853709 | N/A |
  49. | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
  50. | ARM | MMU-500 | #841119,#826419 | N/A |
  51. | | | | |
  52. | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
  53. | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
  54. | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
  55. | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
  56. | Cavium | ThunderX SMMUv2 | #27704 | N/A |
  57. | | | | |
  58. | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
  59. | | | | |
  60. | Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |