genericirq.tmpl 17 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
  3. "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
  4. <book id="Generic-IRQ-Guide">
  5. <bookinfo>
  6. <title>Linux generic IRQ handling</title>
  7. <authorgroup>
  8. <author>
  9. <firstname>Thomas</firstname>
  10. <surname>Gleixner</surname>
  11. <affiliation>
  12. <address>
  13. <email>tglx@linutronix.de</email>
  14. </address>
  15. </affiliation>
  16. </author>
  17. <author>
  18. <firstname>Ingo</firstname>
  19. <surname>Molnar</surname>
  20. <affiliation>
  21. <address>
  22. <email>mingo@elte.hu</email>
  23. </address>
  24. </affiliation>
  25. </author>
  26. </authorgroup>
  27. <copyright>
  28. <year>2005-2010</year>
  29. <holder>Thomas Gleixner</holder>
  30. </copyright>
  31. <copyright>
  32. <year>2005-2006</year>
  33. <holder>Ingo Molnar</holder>
  34. </copyright>
  35. <legalnotice>
  36. <para>
  37. This documentation is free software; you can redistribute
  38. it and/or modify it under the terms of the GNU General Public
  39. License version 2 as published by the Free Software Foundation.
  40. </para>
  41. <para>
  42. This program is distributed in the hope that it will be
  43. useful, but WITHOUT ANY WARRANTY; without even the implied
  44. warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  45. See the GNU General Public License for more details.
  46. </para>
  47. <para>
  48. You should have received a copy of the GNU General Public
  49. License along with this program; if not, write to the Free
  50. Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  51. MA 02111-1307 USA
  52. </para>
  53. <para>
  54. For more details see the file COPYING in the source
  55. distribution of Linux.
  56. </para>
  57. </legalnotice>
  58. </bookinfo>
  59. <toc></toc>
  60. <chapter id="intro">
  61. <title>Introduction</title>
  62. <para>
  63. The generic interrupt handling layer is designed to provide a
  64. complete abstraction of interrupt handling for device drivers.
  65. It is able to handle all the different types of interrupt controller
  66. hardware. Device drivers use generic API functions to request, enable,
  67. disable and free interrupts. The drivers do not have to know anything
  68. about interrupt hardware details, so they can be used on different
  69. platforms without code changes.
  70. </para>
  71. <para>
  72. This documentation is provided to developers who want to implement
  73. an interrupt subsystem based for their architecture, with the help
  74. of the generic IRQ handling layer.
  75. </para>
  76. </chapter>
  77. <chapter id="rationale">
  78. <title>Rationale</title>
  79. <para>
  80. The original implementation of interrupt handling in Linux uses
  81. the __do_IRQ() super-handler, which is able to deal with every
  82. type of interrupt logic.
  83. </para>
  84. <para>
  85. Originally, Russell King identified different types of handlers to
  86. build a quite universal set for the ARM interrupt handler
  87. implementation in Linux 2.5/2.6. He distinguished between:
  88. <itemizedlist>
  89. <listitem><para>Level type</para></listitem>
  90. <listitem><para>Edge type</para></listitem>
  91. <listitem><para>Simple type</para></listitem>
  92. </itemizedlist>
  93. During the implementation we identified another type:
  94. <itemizedlist>
  95. <listitem><para>Fast EOI type</para></listitem>
  96. </itemizedlist>
  97. In the SMP world of the __do_IRQ() super-handler another type
  98. was identified:
  99. <itemizedlist>
  100. <listitem><para>Per CPU type</para></listitem>
  101. </itemizedlist>
  102. </para>
  103. <para>
  104. This split implementation of high-level IRQ handlers allows us to
  105. optimize the flow of the interrupt handling for each specific
  106. interrupt type. This reduces complexity in that particular code path
  107. and allows the optimized handling of a given type.
  108. </para>
  109. <para>
  110. The original general IRQ implementation used hw_interrupt_type
  111. structures and their ->ack(), ->end() [etc.] callbacks to
  112. differentiate the flow control in the super-handler. This leads to
  113. a mix of flow logic and low-level hardware logic, and it also leads
  114. to unnecessary code duplication: for example in i386, there is an
  115. ioapic_level_irq and an ioapic_edge_irq IRQ-type which share many
  116. of the low-level details but have different flow handling.
  117. </para>
  118. <para>
  119. A more natural abstraction is the clean separation of the
  120. 'irq flow' and the 'chip details'.
  121. </para>
  122. <para>
  123. Analysing a couple of architecture's IRQ subsystem implementations
  124. reveals that most of them can use a generic set of 'irq flow'
  125. methods and only need to add the chip-level specific code.
  126. The separation is also valuable for (sub)architectures
  127. which need specific quirks in the IRQ flow itself but not in the
  128. chip details - and thus provides a more transparent IRQ subsystem
  129. design.
  130. </para>
  131. <para>
  132. Each interrupt descriptor is assigned its own high-level flow
  133. handler, which is normally one of the generic
  134. implementations. (This high-level flow handler implementation also
  135. makes it simple to provide demultiplexing handlers which can be
  136. found in embedded platforms on various architectures.)
  137. </para>
  138. <para>
  139. The separation makes the generic interrupt handling layer more
  140. flexible and extensible. For example, an (sub)architecture can
  141. use a generic IRQ-flow implementation for 'level type' interrupts
  142. and add a (sub)architecture specific 'edge type' implementation.
  143. </para>
  144. <para>
  145. To make the transition to the new model easier and prevent the
  146. breakage of existing implementations, the __do_IRQ() super-handler
  147. is still available. This leads to a kind of duality for the time
  148. being. Over time the new model should be used in more and more
  149. architectures, as it enables smaller and cleaner IRQ subsystems.
  150. It's deprecated for three years now and about to be removed.
  151. </para>
  152. </chapter>
  153. <chapter id="bugs">
  154. <title>Known Bugs And Assumptions</title>
  155. <para>
  156. None (knock on wood).
  157. </para>
  158. </chapter>
  159. <chapter id="Abstraction">
  160. <title>Abstraction layers</title>
  161. <para>
  162. There are three main levels of abstraction in the interrupt code:
  163. <orderedlist>
  164. <listitem><para>High-level driver API</para></listitem>
  165. <listitem><para>High-level IRQ flow handlers</para></listitem>
  166. <listitem><para>Chip-level hardware encapsulation</para></listitem>
  167. </orderedlist>
  168. </para>
  169. <sect1 id="Interrupt_control_flow">
  170. <title>Interrupt control flow</title>
  171. <para>
  172. Each interrupt is described by an interrupt descriptor structure
  173. irq_desc. The interrupt is referenced by an 'unsigned int' numeric
  174. value which selects the corresponding interrupt description structure
  175. in the descriptor structures array.
  176. The descriptor structure contains status information and pointers
  177. to the interrupt flow method and the interrupt chip structure
  178. which are assigned to this interrupt.
  179. </para>
  180. <para>
  181. Whenever an interrupt triggers, the low-level architecture code calls
  182. into the generic interrupt code by calling desc->handle_irq().
  183. This high-level IRQ handling function only uses desc->irq_data.chip
  184. primitives referenced by the assigned chip descriptor structure.
  185. </para>
  186. </sect1>
  187. <sect1 id="Highlevel_Driver_API">
  188. <title>High-level Driver API</title>
  189. <para>
  190. The high-level Driver API consists of following functions:
  191. <itemizedlist>
  192. <listitem><para>request_irq()</para></listitem>
  193. <listitem><para>free_irq()</para></listitem>
  194. <listitem><para>disable_irq()</para></listitem>
  195. <listitem><para>enable_irq()</para></listitem>
  196. <listitem><para>disable_irq_nosync() (SMP only)</para></listitem>
  197. <listitem><para>synchronize_irq() (SMP only)</para></listitem>
  198. <listitem><para>irq_set_irq_type()</para></listitem>
  199. <listitem><para>irq_set_irq_wake()</para></listitem>
  200. <listitem><para>irq_set_handler_data()</para></listitem>
  201. <listitem><para>irq_set_chip()</para></listitem>
  202. <listitem><para>irq_set_chip_data()</para></listitem>
  203. </itemizedlist>
  204. See the autogenerated function documentation for details.
  205. </para>
  206. </sect1>
  207. <sect1 id="Highlevel_IRQ_flow_handlers">
  208. <title>High-level IRQ flow handlers</title>
  209. <para>
  210. The generic layer provides a set of pre-defined irq-flow methods:
  211. <itemizedlist>
  212. <listitem><para>handle_level_irq</para></listitem>
  213. <listitem><para>handle_edge_irq</para></listitem>
  214. <listitem><para>handle_fasteoi_irq</para></listitem>
  215. <listitem><para>handle_simple_irq</para></listitem>
  216. <listitem><para>handle_percpu_irq</para></listitem>
  217. <listitem><para>handle_edge_eoi_irq</para></listitem>
  218. <listitem><para>handle_bad_irq</para></listitem>
  219. </itemizedlist>
  220. The interrupt flow handlers (either pre-defined or architecture
  221. specific) are assigned to specific interrupts by the architecture
  222. either during bootup or during device initialization.
  223. </para>
  224. <sect2 id="Default_flow_implementations">
  225. <title>Default flow implementations</title>
  226. <sect3 id="Helper_functions">
  227. <title>Helper functions</title>
  228. <para>
  229. The helper functions call the chip primitives and
  230. are used by the default flow implementations.
  231. The following helper functions are implemented (simplified excerpt):
  232. <programlisting>
  233. default_enable(struct irq_data *data)
  234. {
  235. desc->irq_data.chip->irq_unmask(data);
  236. }
  237. default_disable(struct irq_data *data)
  238. {
  239. if (!delay_disable(data))
  240. desc->irq_data.chip->irq_mask(data);
  241. }
  242. default_ack(struct irq_data *data)
  243. {
  244. chip->irq_ack(data);
  245. }
  246. default_mask_ack(struct irq_data *data)
  247. {
  248. if (chip->irq_mask_ack) {
  249. chip->irq_mask_ack(data);
  250. } else {
  251. chip->irq_mask(data);
  252. chip->irq_ack(data);
  253. }
  254. }
  255. noop(struct irq_data *data))
  256. {
  257. }
  258. </programlisting>
  259. </para>
  260. </sect3>
  261. </sect2>
  262. <sect2 id="Default_flow_handler_implementations">
  263. <title>Default flow handler implementations</title>
  264. <sect3 id="Default_Level_IRQ_flow_handler">
  265. <title>Default Level IRQ flow handler</title>
  266. <para>
  267. handle_level_irq provides a generic implementation
  268. for level-triggered interrupts.
  269. </para>
  270. <para>
  271. The following control flow is implemented (simplified excerpt):
  272. <programlisting>
  273. desc->irq_data.chip->irq_mask_ack();
  274. handle_irq_event(desc->action);
  275. desc->irq_data.chip->irq_unmask();
  276. </programlisting>
  277. </para>
  278. </sect3>
  279. <sect3 id="Default_FASTEOI_IRQ_flow_handler">
  280. <title>Default Fast EOI IRQ flow handler</title>
  281. <para>
  282. handle_fasteoi_irq provides a generic implementation
  283. for interrupts, which only need an EOI at the end of
  284. the handler.
  285. </para>
  286. <para>
  287. The following control flow is implemented (simplified excerpt):
  288. <programlisting>
  289. handle_irq_event(desc->action);
  290. desc->irq_data.chip->irq_eoi();
  291. </programlisting>
  292. </para>
  293. </sect3>
  294. <sect3 id="Default_Edge_IRQ_flow_handler">
  295. <title>Default Edge IRQ flow handler</title>
  296. <para>
  297. handle_edge_irq provides a generic implementation
  298. for edge-triggered interrupts.
  299. </para>
  300. <para>
  301. The following control flow is implemented (simplified excerpt):
  302. <programlisting>
  303. if (desc->status &amp; running) {
  304. desc->irq_data.chip->irq_mask_ack();
  305. desc->status |= pending | masked;
  306. return;
  307. }
  308. desc->irq_data.chip->irq_ack();
  309. desc->status |= running;
  310. do {
  311. if (desc->status &amp; masked)
  312. desc->irq_data.chip->irq_unmask();
  313. desc->status &amp;= ~pending;
  314. handle_irq_event(desc->action);
  315. } while (status &amp; pending);
  316. desc->status &amp;= ~running;
  317. </programlisting>
  318. </para>
  319. </sect3>
  320. <sect3 id="Default_simple_IRQ_flow_handler">
  321. <title>Default simple IRQ flow handler</title>
  322. <para>
  323. handle_simple_irq provides a generic implementation
  324. for simple interrupts.
  325. </para>
  326. <para>
  327. Note: The simple flow handler does not call any
  328. handler/chip primitives.
  329. </para>
  330. <para>
  331. The following control flow is implemented (simplified excerpt):
  332. <programlisting>
  333. handle_irq_event(desc->action);
  334. </programlisting>
  335. </para>
  336. </sect3>
  337. <sect3 id="Default_per_CPU_flow_handler">
  338. <title>Default per CPU flow handler</title>
  339. <para>
  340. handle_percpu_irq provides a generic implementation
  341. for per CPU interrupts.
  342. </para>
  343. <para>
  344. Per CPU interrupts are only available on SMP and
  345. the handler provides a simplified version without
  346. locking.
  347. </para>
  348. <para>
  349. The following control flow is implemented (simplified excerpt):
  350. <programlisting>
  351. if (desc->irq_data.chip->irq_ack)
  352. desc->irq_data.chip->irq_ack();
  353. handle_irq_event(desc->action);
  354. if (desc->irq_data.chip->irq_eoi)
  355. desc->irq_data.chip->irq_eoi();
  356. </programlisting>
  357. </para>
  358. </sect3>
  359. <sect3 id="EOI_Edge_IRQ_flow_handler">
  360. <title>EOI Edge IRQ flow handler</title>
  361. <para>
  362. handle_edge_eoi_irq provides an abnomination of the edge
  363. handler which is solely used to tame a badly wreckaged
  364. irq controller on powerpc/cell.
  365. </para>
  366. </sect3>
  367. <sect3 id="BAD_IRQ_flow_handler">
  368. <title>Bad IRQ flow handler</title>
  369. <para>
  370. handle_bad_irq is used for spurious interrupts which
  371. have no real handler assigned..
  372. </para>
  373. </sect3>
  374. </sect2>
  375. <sect2 id="Quirks_and_optimizations">
  376. <title>Quirks and optimizations</title>
  377. <para>
  378. The generic functions are intended for 'clean' architectures and chips,
  379. which have no platform-specific IRQ handling quirks. If an architecture
  380. needs to implement quirks on the 'flow' level then it can do so by
  381. overriding the high-level irq-flow handler.
  382. </para>
  383. </sect2>
  384. <sect2 id="Delayed_interrupt_disable">
  385. <title>Delayed interrupt disable</title>
  386. <para>
  387. This per interrupt selectable feature, which was introduced by Russell
  388. King in the ARM interrupt implementation, does not mask an interrupt
  389. at the hardware level when disable_irq() is called. The interrupt is
  390. kept enabled and is masked in the flow handler when an interrupt event
  391. happens. This prevents losing edge interrupts on hardware which does
  392. not store an edge interrupt event while the interrupt is disabled at
  393. the hardware level. When an interrupt arrives while the IRQ_DISABLED
  394. flag is set, then the interrupt is masked at the hardware level and
  395. the IRQ_PENDING bit is set. When the interrupt is re-enabled by
  396. enable_irq() the pending bit is checked and if it is set, the
  397. interrupt is resent either via hardware or by a software resend
  398. mechanism. (It's necessary to enable CONFIG_HARDIRQS_SW_RESEND when
  399. you want to use the delayed interrupt disable feature and your
  400. hardware is not capable of retriggering an interrupt.)
  401. The delayed interrupt disable is not configurable.
  402. </para>
  403. </sect2>
  404. </sect1>
  405. <sect1 id="Chiplevel_hardware_encapsulation">
  406. <title>Chip-level hardware encapsulation</title>
  407. <para>
  408. The chip-level hardware descriptor structure irq_chip
  409. contains all the direct chip relevant functions, which
  410. can be utilized by the irq flow implementations.
  411. <itemizedlist>
  412. <listitem><para>irq_ack()</para></listitem>
  413. <listitem><para>irq_mask_ack() - Optional, recommended for performance</para></listitem>
  414. <listitem><para>irq_mask()</para></listitem>
  415. <listitem><para>irq_unmask()</para></listitem>
  416. <listitem><para>irq_eoi() - Optional, required for EOI flow handlers</para></listitem>
  417. <listitem><para>irq_retrigger() - Optional</para></listitem>
  418. <listitem><para>irq_set_type() - Optional</para></listitem>
  419. <listitem><para>irq_set_wake() - Optional</para></listitem>
  420. </itemizedlist>
  421. These primitives are strictly intended to mean what they say: ack means
  422. ACK, masking means masking of an IRQ line, etc. It is up to the flow
  423. handler(s) to use these basic units of low-level functionality.
  424. </para>
  425. </sect1>
  426. </chapter>
  427. <chapter id="doirq">
  428. <title>__do_IRQ entry point</title>
  429. <para>
  430. The original implementation __do_IRQ() was an alternative entry
  431. point for all types of interrupts. It no longer exists.
  432. </para>
  433. <para>
  434. This handler turned out to be not suitable for all
  435. interrupt hardware and was therefore reimplemented with split
  436. functionality for edge/level/simple/percpu interrupts. This is not
  437. only a functional optimization. It also shortens code paths for
  438. interrupts.
  439. </para>
  440. </chapter>
  441. <chapter id="locking">
  442. <title>Locking on SMP</title>
  443. <para>
  444. The locking of chip registers is up to the architecture that
  445. defines the chip primitives. The per-irq structure is
  446. protected via desc->lock, by the generic layer.
  447. </para>
  448. </chapter>
  449. <chapter id="genericchip">
  450. <title>Generic interrupt chip</title>
  451. <para>
  452. To avoid copies of identical implementations of IRQ chips the
  453. core provides a configurable generic interrupt chip
  454. implementation. Developers should check carefully whether the
  455. generic chip fits their needs before implementing the same
  456. functionality slightly differently themselves.
  457. </para>
  458. !Ekernel/irq/generic-chip.c
  459. </chapter>
  460. <chapter id="structs">
  461. <title>Structures</title>
  462. <para>
  463. This chapter contains the autogenerated documentation of the structures which are
  464. used in the generic IRQ layer.
  465. </para>
  466. !Iinclude/linux/irq.h
  467. !Iinclude/linux/interrupt.h
  468. </chapter>
  469. <chapter id="pubfunctions">
  470. <title>Public Functions Provided</title>
  471. <para>
  472. This chapter contains the autogenerated documentation of the kernel API functions
  473. which are exported.
  474. </para>
  475. !Ekernel/irq/manage.c
  476. !Ekernel/irq/chip.c
  477. </chapter>
  478. <chapter id="intfunctions">
  479. <title>Internal Functions Provided</title>
  480. <para>
  481. This chapter contains the autogenerated documentation of the internal functions.
  482. </para>
  483. !Ikernel/irq/irqdesc.c
  484. !Ikernel/irq/handle.c
  485. !Ikernel/irq/chip.c
  486. </chapter>
  487. <chapter id="credits">
  488. <title>Credits</title>
  489. <para>
  490. The following people have contributed to this document:
  491. <orderedlist>
  492. <listitem><para>Thomas Gleixner<email>tglx@linutronix.de</email></para></listitem>
  493. <listitem><para>Ingo Molnar<email>mingo@elte.hu</email></para></listitem>
  494. </orderedlist>
  495. </para>
  496. </chapter>
  497. </book>