#161 t440p, resume from suspend issue

Open
opened 2 years ago by jrhoades · 11 comments
jrhoades commented 2 years ago

Using a t440p, with Debian bullseye (kernel 5.10.140-1), finding that:

  1. after entering suspend state (systemctl suspend),
  2. pressing the power button either restarts (or enters normal boot-up), resulting in the normal osboot prompt, and not resuming from suspend.

Searching online, I found some guidance with coreboot issue #412 (https://ticket.coreboot.org/issues/412), implying that there could be a potential issue with flashing method could cause the issue.

I attempted to re-flash osboot using the following:

sudo ./flashrom/flashrom -p internal --ifd -i bios -w ./bin/t440p_12mb/grub_t440p_12mb_libgfxinit_corebootfb_ukqwerty.rom --noverify-all

...after which, the flashrom prompted indicated VERIFIED. However, resume-from-suspend issue persists (enters into restart/normal boot routine after suspend).

See full cbmem output below, but following coreboot issue #412, the sizing issue log warnings are present in this excerpt:

SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!!
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.

...full cbmem output (as attachments don't seem to allow .log files):


coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 bootblock starting (log level: 0)...
CBFS: Found 'fallback/romstage' @0x80 size 0x7f48 in mcache @0xff7c2e2c
BS: bootblock times (exec / console): total (unknown) / 0 ms


coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 romstage starting (log level: 7)...
Setting up local APIC 0x0
Disabling Watchdog reboot... done.
SMBus controller enabled
Setting up static northbridge registers... done.
Started PEG11 link training.
Temporarily hiding PEG11.
Started PEG10 link training.
Temporarily hiding PEG10.
Initializing IGD...
Back from haswell_early_initialization()
CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4700MQ CPU @ 2.40GHz
AES supported, TXT NOT supported, VT supported
PCH type: QM87, device id: 8c4f, rev id 5
Starting UEFI PEI System Agent
FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
CBFS: Found 'mrc.bin' @0xb6fdc0 size 0x2e6e4 in mcache @0xff7c3270
System Agent: Starting up...
System Agent: Initializing PCH
install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USB)
System Agent: Initializing PCH (SA Init)
System Agent: Initializing PCH (Me UMA)
System Agent: Initializing Memory
System Agent: Done.
Sanity checking heap.
MRC Version 1.6.1 Build 2
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00620020):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 8192 MB width x8 or x32 dual rank, selected
   DIMMB 0 MB width x8 or x32 single rank
memcfg channel[1] config (00620020):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 8192 MB width x8 or x32 dual rank, selected
   DIMMB 0 MB width x8 or x32 single rank
CBMEM:
IMD: root @ 0x7f7ff000 254 entries.
IMD: root @ 0x7f7fec00 62 entries.
External stage cache:
IMD: root @ 0x7fbff000 254 entries.
IMD: root @ 0x7fbfec00 62 entries.
Unhiding PEG10.
Unhiding PEG11.
SMM Memory Map
SMRAM       : 0x7f800000 0x800000
 Subregion 0: 0x7f800000 0x300000
 Subregion 1: 0x7fb00000 0x100000
 Subregion 2: 0x7fc00000 0x400000
MTRR Range: Start=7f000000 End=80000000 (Size 1000000)
MTRR Range: Start=ff800000 End=0 (Size 800000)
Normal boot
CBFS: Found 'fallback/postcar' @0x34580 size 0x50f0 in mcache @0xff7c3074
Loading module at 0x7f7cf000 with entry 0x7f7cf031. filesize: 0x4d28 memsize: 0x9038
Processing 226 relocs. Offset value of 0x7d7cf000
BS: romstage times (exec / console): total (unknown) / 301 ms


coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 postcar starting (log level: 7)...
Normal boot
CBFS: Found 'fallback/ramstage' @0x13540 size 0x1c40d in mcache @0x7f7dd10c
Loading module at 0x7f781000 with entry 0x7f781000. filesize: 0x37998 memsize: 0x4ce10
Processing 3973 relocs. Offset value of 0x7e981000
BS: postcar times (exec / console): total (unknown) / 0 ms


coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 ramstage starting (log level: 7)...
Normal boot
Enumerating buses...
Root Device scanning...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0c04] enabled
PCI: Static device PCI: 00:01.0 not found, disabling it.
PCI: 00:01.1 [8086/0c05] disabled
PCI: 00:02.0 [8086/0416] enabled
PCI: 00:03.0 [8086/0c0c] enabled
PCI: 00:04.0 [8086/0c03] enabled
PCI: 00:14.0 [8086/8c31] enabled
PCI: 00:16.0 [8086/8c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.2: Disabling device
PCI: 00:16.3: Disabling device
PCI: 00:19.0 [8086/153a] enabled
PCI: 00:1a.0 [8086/8c2d] enabled
PCI: 00:1b.0 [8086/8c20] enabled
PCIe Root Port 1 ASPM is disabled
PCI: 00:1c.0 [8086/8c10] enabled
PCIe Root Port 2 ASPM is disabled
PCI: 00:1c.1 [8086/8c12] enabled
PCI: 00:1c.2 [8086/8c14] disabled
PCI: 00:1c.3 [8086/8c16] disabled
Adjusted number of PCIe root ports to 5 as per strpfusecfg2
PCI: 00:1c.2: Disabling device
PCI: 00:1c.3: Disabling device
PCI: 00:1c.4: Disabling device
PCI: 00:1c.4 [8086/8c18] disabled
PCI: 00:1d.0 [8086/8c26] enabled
PCI: 00:1f.0 [8086/8c4f] enabled
PCI: 00:1f.2 [8086/8c03] enabled
PCI: 00:1f.3 [8086/8c22] enabled
PCI: 00:1f.5: Disabling device
PCI: 00:1f.6: Disabling device
PCI: Leftover static devices:
PCI: 00:01.0
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:1c.5
PCI: 00:1c.6
PCI: 00:1c.7
PCI: 00:1f.5
PCI: 00:1f.6
PCI: Check your devicetree.cb.
PCI: 00:1c.0 scanning...
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [10ec/5227] enabled
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
PCIe: Max_Payload_Size adjusted to 128
PCI: 01:00.0: Enabled LTR
scan_bus: bus PCI: 00:1c.0 finished in 0 msecs
PCI: 00:1c.1 scanning...
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [8086/08b2] enabled
Enabling Common Clock Configuration
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
PCI: 02:00.0: Enabled LTR
scan_bus: bus PCI: 00:1c.1 finished in 0 msecs
PCI: 00:1f.0 scanning...
No CMOS option 'touchpad'.
PMH7: ID 05 Revision 01
PNP: 00ff.1 enabled
H8: EC Firmware ID GLHT25WW-3.23, Version 8.01A
H8: BDC detection not implemented. Assuming BDC installed
No CMOS option 'bluetooth'.
H8: WWAN detection not implemented. Assuming WWAN installed
No CMOS option 'wwan'.
PNP: 00ff.2 enabled
PNP: 0c31.0 enabled
scan_bus: bus PCI: 00:1f.0 finished in 5 msecs
PCI: 00:1f.3 scanning...
scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
scan_bus: bus DOMAIN: 0000 finished in 5 msecs
scan_bus: bus Root Device finished in 5 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms
FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes)
FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
flash size 0x2800000 bytes
SF: Detected 00 0000 with sector size 0x1000, total 0x2800000
SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!!
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
SF: Successfully written 2 bytes @ 0x20000
SF: Successfully written 2 bytes @ 0x20002
SF: Successfully written 16 bytes @ 0x20020
SF: Successfully written 4052 bytes @ 0x20030
MRC: updated 'RW_MRC_CACHE'.
BS: BS_DEV_ENUMERATE exit times (exec / console): 9 / 0 ms
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.
mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.
mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.
mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.
mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff.
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
MC MAP: TOM: 0x400000000
MC MAP: TOUUD: 0x47de00000
MC MAP: MESEG_BASE: 0x7ffff00000
MC MAP: MESEG_LIMIT: 0xfffff
MC MAP: REMAP_BASE: 0x400000000
MC MAP: REMAP_LIMIT: 0x47ddfffff
MC MAP: TOLUD: 0x82200000
MC MAP: BGSM: 0x80000000
MC MAP: BDSM: 0x80200000
MC MAP: TSEGMB: 0x7f800000
MC MAP: GGC: 0x209
MC MAP: DPR: 0x7f800001
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
Done reading resources.
=== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
 PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
 PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
 PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 01:00.0 10 *  [0x0 - 0xfff] mem
 PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
 PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done
 PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 02:00.0 10 *  [0x0 - 0x1fff] mem
 PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
 update_constraints: PCI: 00:1f.0 84 base 00001600 limit 0000167f io (fixed)
 update_constraints: PCI: 00:1f.0 88 base 000015e0 limit 000015ef io (fixed)
 update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed)
 update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
 DOMAIN: 0000: Resource ranges:
 * Base: 1000, Size: 5e0, Tag: 100
 * Base: 15f0, Size: 10, Tag: 100
 * Base: 1680, Size: e980, Tag: 100
  PCI: 00:02.0 20 *  [0x1000 - 0x103f] limit: 103f io
  PCI: 00:19.0 18 *  [0x1040 - 0x105f] limit: 105f io
  PCI: 00:1f.2 20 *  [0x1060 - 0x107f] limit: 107f io
  PCI: 00:1f.2 10 *  [0x1080 - 0x1087] limit: 1087 io
  PCI: 00:1f.2 18 *  [0x1088 - 0x108f] limit: 108f io
  PCI: 00:1f.2 14 *  [0x1090 - 0x1093] limit: 1093 io
  PCI: 00:1f.2 1c *  [0x1094 - 0x1097] limit: 1097 io
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
 update_constraints: PCI: 00:00.0 48 base fed10000 limit fed17fff mem (fixed)
 update_constraints: PCI: 00:00.0 68 base fed18000 limit fed18fff mem (fixed)
 update_constraints: PCI: 00:00.0 40 base fed19000 limit fed19fff mem (fixed)
 update_constraints: PCI: 00:00.0 5420 base fed84000 limit fed84fff mem (fixed)
 update_constraints: PCI: 00:00.0 5408 base fed80000 limit fed83fff mem (fixed)
 update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
 update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
 update_constraints: PCI: 00:00.0 01 base 000c0000 limit 7f7fffff mem (fixed)
 update_constraints: PCI: 00:00.0 02 base 7f800000 limit 7fffffff mem (fixed)
 update_constraints: PCI: 00:00.0 03 base 80000000 limit 821fffff mem (fixed)
 update_constraints: PCI: 00:00.0 04 base 100000000 limit 47ddfffff mem (fixed)
 update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed)
 update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed)
 update_constraints: PCI: 00:1f.0 31fe base fec00000 limit ffffffff mem (fixed)
 update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
 DOMAIN: 0000: Resource ranges:
 * Base: 82200000, Size: 6de00000, Tag: 200
 * Base: f4000000, Size: ac00000, Tag: 200
 * Base: 47de00000, Size: 7b82200000, Tag: 100200
  PCI: 00:02.0 18 *  [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
  PCI: 00:02.0 10 *  [0x82400000 - 0x827fffff] limit: 827fffff mem
  PCI: 00:1c.0 20 *  [0x82200000 - 0x822fffff] limit: 822fffff mem
  PCI: 00:1c.1 20 *  [0x82300000 - 0x823fffff] limit: 823fffff mem
  PCI: 00:19.0 10 *  [0x82800000 - 0x8281ffff] limit: 8281ffff mem
  PCI: 00:14.0 10 *  [0x82820000 - 0x8282ffff] limit: 8282ffff mem
  PCI: 00:04.0 10 *  [0x82830000 - 0x82837fff] limit: 82837fff mem
  PCI: 00:03.0 10 *  [0x82838000 - 0x8283bfff] limit: 8283bfff mem
  PCI: 00:1b.0 10 *  [0x8283c000 - 0x8283ffff] limit: 8283ffff mem
  PCI: 00:19.0 14 *  [0x82840000 - 0x82840fff] limit: 82840fff mem
  PCI: 00:1f.2 24 *  [0x82841000 - 0x828417ff] limit: 828417ff mem
  PCI: 00:1a.0 10 *  [0x82842000 - 0x828423ff] limit: 828423ff mem
  PCI: 00:1d.0 10 *  [0x82843000 - 0x828433ff] limit: 828433ff mem
  PCI: 00:1f.3 10 *  [0x82844000 - 0x828440ff] limit: 828440ff mem
  PCI: 00:16.0 10 *  [0x82845000 - 0x8284500f] limit: 8284500f mem
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
PCI: 00:1c.0 mem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff
 PCI: 00:1c.0: Resource ranges:
 * Base: 82200000, Size: 100000, Tag: 200
  PCI: 01:00.0 10 *  [0x82200000 - 0x82200fff] limit: 82200fff mem
PCI: 00:1c.0 mem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff done
PCI: 00:1c.1 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff
 PCI: 00:1c.1: Resource ranges:
 * Base: 82300000, Size: 100000, Tag: 200
  PCI: 02:00.0 10 *  [0x82300000 - 0x82301fff] limit: 82301fff mem
PCI: 00:1c.1 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff done
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
PCI: 00:02.0 10 <- [0x0082400000 - 0x00827fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:03.0 10 <- [0x0082838000 - 0x008283bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:04.0 10 <- [0x0082830000 - 0x0082837fff] size 0x00008000 gran 0x0f mem64
PCI: 00:14.0 10 <- [0x0082820000 - 0x008282ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:16.0 10 <- [0x0082845000 - 0x008284500f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x0082800000 - 0x008281ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x0082840000 - 0x0082840fff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 10 <- [0x0082842000 - 0x00828423ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x008283c000 - 0x008283ffff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x0082200000 - 0x00822fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 01:00.0 10 <- [0x0082200000 - 0x0082200fff] size 0x00001000 gran 0x0c mem
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.1 20 <- [0x0082300000 - 0x00823fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 02:00.0 10 <- [0x0082300000 - 0x0082301fff] size 0x00002000 gran 0x0d mem64
PCI: 00:1d.0 10 <- [0x0082843000 - 0x00828433ff] size 0x00000400 gran 0x0a mem
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
PCI: 00:1f.2 10 <- [0x0000001080 - 0x0000001087] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000001090 - 0x0000001093] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000001088 - 0x000000108f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000001094 - 0x0000001097] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x0082841000 - 0x00828417ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x0082844000 - 0x00828440ff] size 0x00000100 gran 0x08 mem64
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
Enabling resources...
PCI: 00:00.0 subsystem <- 17aa/220e
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 17aa/220e
PCI: 00:02.0 cmd <- 03
PCI: 00:03.0 subsystem <- 17aa/220e
PCI: 00:03.0 cmd <- 02
PCI: 00:04.0 cmd <- 02
PCI: 00:14.0 subsystem <- 17aa/220e
PCI: 00:14.0 cmd <- 102
PCI: 00:16.0 subsystem <- 17aa/220e
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 17aa/220e
PCI: 00:19.0 cmd <- 103
PCI: 00:1a.0 subsystem <- 17aa/220e
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 17aa/220e
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0013
PCI: 00:1c.0 subsystem <- 17aa/220e
PCI: 00:1c.0 cmd <- 06
PCI: 00:1c.1 bridge ctrl <- 0013
PCI: 00:1c.1 subsystem <- 17aa/220e
PCI: 00:1c.1 cmd <- 06
PCI: 00:1d.0 subsystem <- 17aa/220e
PCI: 00:1d.0 cmd <- 102
PCI: 00:1f.0 subsystem <- 17aa/220e
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 17aa/220e
PCI: 00:1f.2 cmd <- 103
PCI: 00:1f.3 subsystem <- 17aa/220e
PCI: 00:1f.3 cmd <- 103
PCI: 01:00.0 cmd <- 02
PCI: 02:00.0 cmd <- 02
done.
Found TPM ST33ZP24 by ST Microelectronics
TPM: Startup
TPM: command 0x99 returned 0x0
TPM: Asserting physical presence
TPM: command 0x4000000a returned 0x0
TPM: command 0x65 returned 0x0
TPM: flags disable=0, deactivated=0, nvlocked=1
TPM: setup succeeded
BS: BS_DEV_INIT entry times (exec / console): 45 / 0 ms
Initializing devices...
CPU_CLUSTER: 0 init
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 0
0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1
0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0
0x0000000100000000 - 0x000000047de00000 size 0x37de00000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 4/5.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000007ff0000000 type 0
MTRR: 1 base 0x0000000090000000 mask 0x0000007ff0000000 type 1
MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Initializing VR config.
CPU has 4 cores, 8 threads enabled.
Setting up SMI for CPU
Will perform SMM setup.
CBFS: Found 'cpu_microcode_blob.bin' @0x8080 size 0xb400 in mcache @0x7f7dd0ac
microcode: sig=0x306c3 pf=0x10 revision=0x28
CPU: Intel(R) Core(TM) i7-4700MQ CPU @ 2.40GHz.
Setting up local APIC 0x0
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
Processing 18 relocs. Offset value of 0x00030000
Attempting to start 7 APs
Starting CPUs in xapic mode
Waiting for 10ms after sending INIT.
Waiting for SIPI to complete...
done.
Waiting for SIPI to complete...
Setting up local APIC 0x1
done.
AP: slot 1 apic_id 1, MCU rev: 0x00000028
Setting up local APIC 0x2
Setting up local APIC 0x3
AP: slot 2 apic_id 2, MCU rev: 0x00000028
AP: slot 3 apic_id 3, MCU rev: 0x00000028
Setting up local APIC 0x4
Setting up local APIC 0x5
AP: slot 4 apic_id 4, MCU rev: 0x00000028
AP: slot 6 apic_id 5, MCU rev: 0x00000028
Setting up local APIC 0x7
Setting up local APIC 0x6
AP: slot 5 apic_id 7, MCU rev: 0x00000028
AP: slot 7 apic_id 6, MCU rev: 0x00000028
smm_stub_place_stacks: cpus: 8 : stack space: needed -> 2000
smm_stub_place_stacks: exit, stack_top 0x7f802000
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8
Processing 11 relocs. Offset value of 0x00038000
smm_module_setup_stub: stack_end = 0x7f800000
smm_module_setup_stub: stack_top = 0x7f802000
smm_module_setup_stub: stack_size = 0x400
smm_module_setup_stub: runtime.start32_offset = 0x4c
smm_module_setup_stub: runtime.smm_size = 0x10000
SMM Module: stub loaded at 0x00038000. Will call 0x7f79f56a
Installing permanent SMM handler to 0x7f800000
smm_load_module: total_smm_space_needed 8960, available -> 300000
Loading module at 0x7fafa000 with entry 0x7fafa6fd. filesize: 0x1918 memsize: 0x5960
Processing 80 relocs. Offset value of 0x7fafa000
smm_load_module: smram_start: 0x0x7f800000
smm_load_module: smram_end: 0x7fb00000
smm_load_module: stack_top: 0x7f802000
smm_load_module: handler start 0x7fafa6fd
smm_load_module: handler_size 62c0
smm_load_module: fxsave_area 0x7faff000
smm_load_module: fxsave_size 1000
smm_load_module: CONFIG_MSEG_SIZE 0x0
smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
smm_load_module: handler_mod_params.smbase = 0x7f800000
smm_load_module: per_cpu_save_state_size = 0x400
smm_load_module: num_cpus = 0x8
smm_load_module: total_save_state_size = 0x2000
smm_load_module: cpu0 entry: 0x7faea000
smm_create_map: cpus allowed in one segment 30
smm_create_map: min # of segments needed 1
smm_stub_place_stacks: cpus: 8 : stack space: needed -> 2000
smm_stub_place_stacks: exit, stack_top 0x7f802000
Loading module at 0x7faf2000 with entry 0x7faf2000. filesize: 0x1e8 memsize: 0x1e8
Processing 11 relocs. Offset value of 0x7faf2000
smm_place_entry_code: smbase 7fae8400, stack_top 7f802000
SMM Module: placing smm entry code at 7faf1c00,  cpu # 0x1
smm_place_entry_code: copying from 7faf2000 to 7faf1c00 0x1e8 bytes
SMM Module: placing smm entry code at 7faf1800,  cpu # 0x2
smm_place_entry_code: copying from 7faf2000 to 7faf1800 0x1e8 bytes
SMM Module: placing smm entry code at 7faf1400,  cpu # 0x3
smm_place_entry_code: copying from 7faf2000 to 7faf1400 0x1e8 bytes
SMM Module: placing smm entry code at 7faf1000,  cpu # 0x4
smm_place_entry_code: copying from 7faf2000 to 7faf1000 0x1e8 bytes
SMM Module: placing smm entry code at 7faf0c00,  cpu # 0x5
smm_place_entry_code: copying from 7faf2000 to 7faf0c00 0x1e8 bytes
SMM Module: placing smm entry code at 7faf0800,  cpu # 0x6
smm_place_entry_code: copying from 7faf2000 to 7faf0800 0x1e8 bytes
SMM Module: placing smm entry code at 7faf0400,  cpu # 0x7
smm_place_entry_code: copying from 7faf2000 to 7faf0400 0x1e8 bytes
smm_module_setup_stub: stack_end = 0x7f800000
smm_module_setup_stub: stack_top = 0x7f802000
smm_module_setup_stub: stack_size = 0x400
smm_module_setup_stub: runtime.start32_offset = 0x4c
smm_module_setup_stub: runtime.smm_size = 0x300000
SMM Module: stub loaded at 0x7faf2000. Will call 0x7fafa6fd
Initializing Southbridge SMI...
SMI_STS: MCSMI PM1 
TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea000, cpu = 0
In relocation handler: CPU 0
New SMBASE=0x7faea000 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9c00, cpu = 1
In relocation handler: CPU 1
New SMBASE=0x7fae9c00 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae8400, cpu = 7
In relocation handler: CPU 7
New SMBASE=0x7fae8400 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae8c00, cpu = 5
In relocation handler: CPU 5
New SMBASE=0x7fae8c00 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae8800, cpu = 6
In relocation handler: CPU 6
New SMBASE=0x7fae8800 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9000, cpu = 4
In relocation handler: CPU 4
New SMBASE=0x7fae9000 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9800, cpu = 2
In relocation handler: CPU 2
New SMBASE=0x7fae9800 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9400, cpu = 3
In relocation handler: CPU 3
New SMBASE=0x7fae9400 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
Initializing CPU #0
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
Setting up local APIC 0x0
IA32_FEATURE_CONTROL already locked; VMX status: enabled
IA32_FEATURE_CONTROL already locked
cpu: energy policy set to 6
Turbo is available but hidden
Turbo is available and visible
CPU #0 initialized
Initializing CPU #1
Initializing CPU #5
Initializing CPU #7
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
Initializing CPU #4
Initializing CPU #6
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
Initializing CPU #2
Initializing CPU #3
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
Setting up local APIC 0x1
Setting up local APIC 0x7
Setting up local APIC 0x6
IA32_FEATURE_CONTROL already locked; IA32_FEATURE_CONTROL already locked; VMX status: enabled
VMX status: enabled
IA32_FEATURE_CONTROL already locked
IA32_FEATURE_CONTROL already locked
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
IA32_FEATURE_CONTROL already locked; VMX status: enabled
Setting up local APIC 0x2
Setting up local APIC 0x4
Setting up local APIC 0x5
IA32_FEATURE_CONTROL already locked; IA32_FEATURE_CONTROL already locked; VMX status: enabled
VMX status: enabled
IA32_FEATURE_CONTROL already locked
IA32_FEATURE_CONTROL already locked
IA32_FEATURE_CONTROL already locked
IA32_FEATURE_CONTROL already locked; VMX status: enabled
Setting up local APIC 0x3
IA32_FEATURE_CONTROL already locked
IA32_FEATURE_CONTROL already locked; VMX status: enabled
cpu: energy policy set to 6
cpu: energy policy set to 6
CPU #7 initialized
CPU #5 initialized
IA32_FEATURE_CONTROL already locked
cpu: energy policy set to 6
CPU #1 initialized
cpu: energy policy set to 6
cpu: energy policy set to 6
cpu: energy policy set to 6
CPU #2 initialized
CPU #6 initialized
CPU #4 initialized
cpu: energy policy set to 6
CPU #3 initialized
bsp_do_flight_plan done after 3 msecs.
CPU: frequency set to 3400
Enabling SMIs.
Locking SMM.
CPU_CLUSTER: 0 init finished in 18 msecs
PCI: 00:00.0 init
Disabling PEG12.
Disabling PEG11.
Disabling PEG10.
Disabling "device 7".
Set BIOS_RESET_CPL
CPU TDP: 47 Watts
PCI: 00:00.0 init finished in 1 msecs
PCI: 00:02.0 init
CBFS: Found 'vbt.bin' @0x338c0 size 0x582 in mcache @0x7f7dd1f4
Found a VBT of 4608 bytes after decompression
GMA: Found VBT in CBFS
GMA: Found valid VBT in CBFS
GT Power Management Init
GMA: Setting backlight PWM frequency to 135MHz / 128 / 4794 = 220Hz
framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
                   x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000
GT Power Management Init (post VBIOS)
PCI: 00:02.0 init finished in 208 msecs
PCI: 00:03.0 init
Mini-HD: base = 0x82838000
HDA: No codec!
PCI: 00:03.0 init finished in 51 msecs
PCI: 00:04.0 init
PCI: 00:04.0 init finished in 0 msecs
PCI: 00:14.0 init
PCI: 00:14.0 init finished in 0 msecs
PCI: 00:16.0 init
intel_me_path: mbp is not ready!
ME: BIOS path: Error
ME: MBP not ready
PCI: 00:16.0 init finished in 0 msecs
PCI: 00:19.0 init
PCI: 00:19.0 init finished in 0 msecs
PCI: 00:1a.0 init
EHCI: Setting up controller.. done.
PCI: 00:1a.0 init finished in 0 msecs
PCI: 00:1b.0 init
Azalia: base = 0x8283c000
Azalia: codec_mask = 01
azalia_audio: Initializing codec #0
azalia_audio: codec viddid: 10ec0292
azalia_audio: verb_size: 128
azalia_audio: verb loaded.
PCI: 00:1b.0 init finished in 7 msecs
PCI: 00:1c.0 init
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 0 msecs
PCI: 00:1c.1 init
Initializing PCH PCIe bridge.
PCI: 00:1c.1 init finished in 0 msecs
PCI: 00:1d.0 init
EHCI: Setting up controller.. done.
PCI: 00:1d.0 init finished in 0 msecs
PCI: 00:1f.0 init
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: ID = 0x02
IOAPIC: 24 interrupts
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
Set power off after power failure.
NMI sources enabled.
LynxPoint H PM init
RTC: failed = 0x0
RTC Init
apm_control: Disabling ACPI.
APMC done.
PCI: 00:1f.0 init finished in 0 msecs
PCI: 00:1f.2 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: 0x82841000
PCI: 00:1f.2 init finished in 0 msecs
PCI: 00:1f.3 init
PCI: 00:1f.3 init finished in 0 msecs
PCI: 01:00.0 init
PCI: 01:00.0 init finished in 0 msecs
PCI: 02:00.0 init
PCI: 02:00.0 init finished in 0 msecs
PNP: 00ff.2 init
PNP: 00ff.2 init finished in 0 msecs
Devices initialized
BS: BS_DEV_INIT run times (exec / console): 287 / 0 ms
clear_memory: Clearing DRAM 0000000000000000-0000000000005000
clear_memory: Clearing DRAM 000000000000a000-00000000000a0000
clear_memory: Clearing DRAM 00000000000c0000-000000007f76e000
clear_memory: Clearing DRAM 000000007f800000-0000000080000000
clear_memory: Clearing DRAM 0000000100000000-000000047de00000
memset_pae: Using virtual address 0x00200000 as scratchpad
memset_pae: Using address 0x00005000 for page tables
clear_memory: Clearing DRAM 0000000000005000-000000000000a000
BS: BS_DEV_INIT exit times (exec / console): 783 / 0 ms
Finalize devices...
PCI: 00:00.0 final
PCI: 00:16.0 final
ME: MBP cleared
PCI: 00:1b.0 final
PCI: 00:1f.0 final
apm_control: Finalizing SMM.
APMC done.
Devices finalized
CBFS: Found 'fallback/dsdt.aml' @0x30240 size 0x3652 in mcache @0x7f7dd1c8
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7f742000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
ACPI: added table 1/32, length now 40
ACPI:     * SSDT
Found 1 CPU(s) with 8 core(s) each.
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
PSS: 2401MHz power 47000 control 0x2200 status 0x2200
PSS: 2400MHz power 47000 control 0x1800 status 0x1800
PSS: 2000MHz power 37350 control 0x1400 status 0x1400
PSS: 1600MHz power 28516 control 0x1000 status 0x1000
PSS: 1200MHz power 20398 control 0xc00 status 0xc00
PSS: 800MHz power 12927 control 0x800 status 0x800
Generating ACPI PIRQ entries
ACPI:    * H8
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN detection not implemented. Assuming WWAN installed
\_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:    * TCPA
TCPA log created at 0x7f732000
ACPI: added table 4/32, length now 52
ACPI:    * MADT
ACPI: added table 5/32, length now 56
current = 7f748230
ACPI:    * HPET
ACPI: added table 6/32, length now 60
current = 7f748270
ACPI: done.
ACPI tables: 25200 bytes.
smbios_write_tables: 7f731000
SMBIOS firmware version is set to coreboot_version: '4.15-204-gdfa70bd036'
Create SMBIOS type 16
Create SMBIOS type 17
Create SMBIOS type 20
PCI: 02:00.0 (unknown)
SMBIOS tables: 1120 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 2068
Writing coreboot table at 0x7f766000
CBFS: Found 'cmos_layout.bin' @0x33fc0 size 0x574 in mcache @0x7f7dd24c
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000007f730fff: RAM
 4. 000000007f731000-000000007f780fff: CONFIGURATION TABLES
 5. 000000007f781000-000000007f7cdfff: RAMSTAGE
 6. 000000007f7ce000-000000007f7fffff: CONFIGURATION TABLES
 7. 000000007f800000-00000000821fffff: RESERVED
 8. 00000000f0000000-00000000f3ffffff: RESERVED
 9. 00000000fed10000-00000000fed19fff: RESERVED
10. 00000000fed40000-00000000fed44fff: RESERVED
11. 00000000fed80000-00000000fed84fff: RESERVED
12. 0000000100000000-000000047ddfffff: RAM
Wrote coreboot table at: 0x7f766000, 0x988 bytes, checksum 6d1e
coreboot table: 2464 bytes.
IMD ROOT    0. 0x7f7ff000 0x00001000
IMD SMALL   1. 0x7f7fe000 0x00001000
CONSOLE     2. 0x7f7de000 0x00020000
RO MCACHE   3. 0x7f7dd000 0x000004f4
TIME STAMP  4. 0x7f7dc000 0x00000910
MRC DATA    5. 0x7f7db000 0x00000fe4
MEM INFO    6. 0x7f7da000 0x000003b8
ROMSTG STCK 7. 0x7f7d9000 0x00001000
AFTER CAR   8. 0x7f7ce000 0x0000b000
RAMSTAGE    9. 0x7f780000 0x0004e000
SMM BACKUP 10. 0x7f770000 0x00010000
4f444749   11. 0x7f76e000 0x00002000
COREBOOT   12. 0x7f766000 0x00008000
ACPI       13. 0x7f742000 0x00024000
TCPA TCGLOG14. 0x7f732000 0x00010000
SMBIOS     15. 0x7f731000 0x00001000
IMD small region:
  IMD ROOT    0. 0x7f7fec00 0x00000400
  FMAP        1. 0x7f7feb20 0x000000e0
  ROMSTAGE    2. 0x7f7feb00 0x00000004
  ACPI GNVS   3. 0x7f7fea40 0x000000b0
BS: BS_WRITE_TABLES run times (exec / console): 5 / 0 ms
CBFS: Found 'fallback/payload' @0x396c0 size 0xf894 in mcache @0x7f7dd2b8
Checking segment from ROM address 0xff4698ec
Payload being loaded at below 1MiB without region being marked as RAM usable.
Checking segment from ROM address 0xff469908
Loading segment from ROM address 0xff4698ec
  code (compression=1)
  New segment dstaddr 0x000e3b80 memsize 0x1c480 srcaddr 0xff469924 filesize 0xf85c
Loading Segment: addr: 0x000e3b80 memsz: 0x000000000001c480 filesz: 0x000000000000f85c
using LZMA
Loading segment from ROM address 0xff469908
  Entry Point 0x000fd776
BS: BS_PAYLOAD_LOAD run times (exec / console): 25 / 0 ms
ICH-NM10-PCH: watchdog disabled
Jumping to boot code at 0x000fd776(0x7f766000)

Using a t440p, with Debian bullseye (kernel 5.10.140-1), finding that: 1. after entering suspend state (`systemctl suspend`), 2. pressing the power button either restarts (or enters normal boot-up), resulting in the normal osboot prompt, and not resuming from suspend. Searching online, I found some guidance with coreboot issue #412 (<https://ticket.coreboot.org/issues/412>), implying that there could be a potential issue with flashing method could cause the issue. I attempted to re-flash osboot using the following: ``` sudo ./flashrom/flashrom -p internal --ifd -i bios -w ./bin/t440p_12mb/grub_t440p_12mb_libgfxinit_corebootfb_ukqwerty.rom --noverify-all ``` ...after which, the flashrom prompted indicated `VERIFIED`. However, resume-from-suspend issue persists (enters into restart/normal boot routine after suspend). See full cbmem output below, but following coreboot issue #412, the sizing issue log warnings are present in this excerpt: ``` SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!! MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. ``` ...full cbmem output (as attachments don't seem to allow .log files): ``` coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 bootblock starting (log level: 0)... CBFS: Found 'fallback/romstage' @0x80 size 0x7f48 in mcache @0xff7c2e2c BS: bootblock times (exec / console): total (unknown) / 0 ms coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 romstage starting (log level: 7)... Setting up local APIC 0x0 Disabling Watchdog reboot... done. SMBus controller enabled Setting up static northbridge registers... done. Started PEG11 link training. Temporarily hiding PEG11. Started PEG10 link training. Temporarily hiding PEG10. Initializing IGD... Back from haswell_early_initialization() CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4700MQ CPU @ 2.40GHz AES supported, TXT NOT supported, VT supported PCH type: QM87, device id: 8c4f, rev id 5 Starting UEFI PEI System Agent FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' CBFS: Found 'mrc.bin' @0xb6fdc0 size 0x2e6e4 in mcache @0xff7c3270 System Agent: Starting up... System Agent: Initializing PCH install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845} install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276} System Agent: Initializing PCH (SMBUS) System Agent: Initializing PCH (USB) System Agent: Initializing PCH (SA Init) System Agent: Initializing PCH (Me UMA) System Agent: Initializing Memory System Agent: Done. Sanity checking heap. MRC Version 1.6.1 Build 2 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00620020): ECC inactive enhanced interleave mode on rank interleave on DIMMA 8192 MB width x8 or x32 dual rank, selected DIMMB 0 MB width x8 or x32 single rank memcfg channel[1] config (00620020): ECC inactive enhanced interleave mode on rank interleave on DIMMA 8192 MB width x8 or x32 dual rank, selected DIMMB 0 MB width x8 or x32 single rank CBMEM: IMD: root @ 0x7f7ff000 254 entries. IMD: root @ 0x7f7fec00 62 entries. External stage cache: IMD: root @ 0x7fbff000 254 entries. IMD: root @ 0x7fbfec00 62 entries. Unhiding PEG10. Unhiding PEG11. SMM Memory Map SMRAM : 0x7f800000 0x800000 Subregion 0: 0x7f800000 0x300000 Subregion 1: 0x7fb00000 0x100000 Subregion 2: 0x7fc00000 0x400000 MTRR Range: Start=7f000000 End=80000000 (Size 1000000) MTRR Range: Start=ff800000 End=0 (Size 800000) Normal boot CBFS: Found 'fallback/postcar' @0x34580 size 0x50f0 in mcache @0xff7c3074 Loading module at 0x7f7cf000 with entry 0x7f7cf031. filesize: 0x4d28 memsize: 0x9038 Processing 226 relocs. Offset value of 0x7d7cf000 BS: romstage times (exec / console): total (unknown) / 301 ms coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 postcar starting (log level: 7)... Normal boot CBFS: Found 'fallback/ramstage' @0x13540 size 0x1c40d in mcache @0x7f7dd10c Loading module at 0x7f781000 with entry 0x7f781000. filesize: 0x37998 memsize: 0x4ce10 Processing 3973 relocs. Offset value of 0x7e981000 BS: postcar times (exec / console): total (unknown) / 0 ms coreboot-4.15-204-gdfa70bd036 Sat Oct 15 04:42:05 UTC 2022 ramstage starting (log level: 7)... Normal boot Enumerating buses... Root Device scanning... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0c04] enabled PCI: Static device PCI: 00:01.0 not found, disabling it. PCI: 00:01.1 [8086/0c05] disabled PCI: 00:02.0 [8086/0416] enabled PCI: 00:03.0 [8086/0c0c] enabled PCI: 00:04.0 [8086/0c03] enabled PCI: 00:14.0 [8086/8c31] enabled PCI: 00:16.0 [8086/8c3a] enabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:19.0 [8086/153a] enabled PCI: 00:1a.0 [8086/8c2d] enabled PCI: 00:1b.0 [8086/8c20] enabled PCIe Root Port 1 ASPM is disabled PCI: 00:1c.0 [8086/8c10] enabled PCIe Root Port 2 ASPM is disabled PCI: 00:1c.1 [8086/8c12] enabled PCI: 00:1c.2 [8086/8c14] disabled PCI: 00:1c.3 [8086/8c16] disabled Adjusted number of PCIe root ports to 5 as per strpfusecfg2 PCI: 00:1c.2: Disabling device PCI: 00:1c.3: Disabling device PCI: 00:1c.4: Disabling device PCI: 00:1c.4 [8086/8c18] disabled PCI: 00:1d.0 [8086/8c26] enabled PCI: 00:1f.0 [8086/8c4f] enabled PCI: 00:1f.2 [8086/8c03] enabled PCI: 00:1f.3 [8086/8c22] enabled PCI: 00:1f.5: Disabling device PCI: 00:1f.6: Disabling device PCI: Leftover static devices: PCI: 00:01.0 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:1c.5 PCI: 00:1c.6 PCI: 00:1c.7 PCI: 00:1f.5 PCI: 00:1f.6 PCI: Check your devicetree.cb. PCI: 00:1c.0 scanning... PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [10ec/5227] enabled Enabling Common Clock Configuration ASPM: Enabled L0s and L1 PCIe: Max_Payload_Size adjusted to 128 PCI: 01:00.0: Enabled LTR scan_bus: bus PCI: 00:1c.0 finished in 0 msecs PCI: 00:1c.1 scanning... PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [8086/08b2] enabled Enabling Common Clock Configuration ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 PCI: 02:00.0: Enabled LTR scan_bus: bus PCI: 00:1c.1 finished in 0 msecs PCI: 00:1f.0 scanning... No CMOS option 'touchpad'. PMH7: ID 05 Revision 01 PNP: 00ff.1 enabled H8: EC Firmware ID GLHT25WW-3.23, Version 8.01A H8: BDC detection not implemented. Assuming BDC installed No CMOS option 'bluetooth'. H8: WWAN detection not implemented. Assuming WWAN installed No CMOS option 'wwan'. PNP: 00ff.2 enabled PNP: 0c31.0 enabled scan_bus: bus PCI: 00:1f.0 finished in 5 msecs PCI: 00:1f.3 scanning... scan_bus: bus PCI: 00:1f.3 finished in 0 msecs scan_bus: bus DOMAIN: 0000 finished in 5 msecs scan_bus: bus Root Device finished in 5 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes) FMAP: area RW_MRC_CACHE found @ 20000 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. flash size 0x2800000 bytes SF: Detected 00 0000 with sector size 0x1000, total 0x2800000 SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!! MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. SF: Successfully written 2 bytes @ 0x20000 SF: Successfully written 2 bytes @ 0x20002 SF: Successfully written 16 bytes @ 0x20020 SF: Successfully written 4052 bytes @ 0x20030 MRC: updated 'RW_MRC_CACHE'. BS: BS_DEV_ENUMERATE exit times (exec / console): 9 / 0 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. MC MAP: TOM: 0x400000000 MC MAP: TOUUD: 0x47de00000 MC MAP: MESEG_BASE: 0x7ffff00000 MC MAP: MESEG_LIMIT: 0xfffff MC MAP: REMAP_BASE: 0x400000000 MC MAP: REMAP_LIMIT: 0x47ddfffff MC MAP: TOLUD: 0x82200000 MC MAP: BGSM: 0x80000000 MC MAP: BDSM: 0x80200000 MC MAP: TSEGMB: 0x7f800000 MC MAP: GGC: 0x209 MC MAP: DPR: 0x7f800001 PNP: 00ff.1 missing read_resources PNP: 00ff.2 missing read_resources Done reading resources. === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xfff] mem PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0x1fff] mem PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) update_constraints: PCI: 00:1f.0 84 base 00001600 limit 0000167f io (fixed) update_constraints: PCI: 00:1f.0 88 base 000015e0 limit 000015ef io (fixed) update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed) update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: 5e0, Tag: 100 * Base: 15f0, Size: 10, Tag: 100 * Base: 1680, Size: e980, Tag: 100 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff update_constraints: PCI: 00:00.0 48 base fed10000 limit fed17fff mem (fixed) update_constraints: PCI: 00:00.0 68 base fed18000 limit fed18fff mem (fixed) update_constraints: PCI: 00:00.0 40 base fed19000 limit fed19fff mem (fixed) update_constraints: PCI: 00:00.0 5420 base fed84000 limit fed84fff mem (fixed) update_constraints: PCI: 00:00.0 5408 base fed80000 limit fed83fff mem (fixed) update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) update_constraints: PCI: 00:00.0 01 base 000c0000 limit 7f7fffff mem (fixed) update_constraints: PCI: 00:00.0 02 base 7f800000 limit 7fffffff mem (fixed) update_constraints: PCI: 00:00.0 03 base 80000000 limit 821fffff mem (fixed) update_constraints: PCI: 00:00.0 04 base 100000000 limit 47ddfffff mem (fixed) update_constraints: PCI: 00:00.0 05 base 000a0000 limit 000bffff mem (fixed) update_constraints: PCI: 00:00.0 06 base 000c0000 limit 000fffff mem (fixed) update_constraints: PCI: 00:1f.0 31fe base fec00000 limit ffffffff mem (fixed) update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: 82200000, Size: 6de00000, Tag: 200 * Base: f4000000, Size: ac00000, Tag: 200 * Base: 47de00000, Size: 7b82200000, Tag: 100200 PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem PCI: 00:02.0 10 * [0x82400000 - 0x827fffff] limit: 827fffff mem PCI: 00:1c.0 20 * [0x82200000 - 0x822fffff] limit: 822fffff mem PCI: 00:1c.1 20 * [0x82300000 - 0x823fffff] limit: 823fffff mem PCI: 00:19.0 10 * [0x82800000 - 0x8281ffff] limit: 8281ffff mem PCI: 00:14.0 10 * [0x82820000 - 0x8282ffff] limit: 8282ffff mem PCI: 00:04.0 10 * [0x82830000 - 0x82837fff] limit: 82837fff mem PCI: 00:03.0 10 * [0x82838000 - 0x8283bfff] limit: 8283bfff mem PCI: 00:1b.0 10 * [0x8283c000 - 0x8283ffff] limit: 8283ffff mem PCI: 00:19.0 14 * [0x82840000 - 0x82840fff] limit: 82840fff mem PCI: 00:1f.2 24 * [0x82841000 - 0x828417ff] limit: 828417ff mem PCI: 00:1a.0 10 * [0x82842000 - 0x828423ff] limit: 828423ff mem PCI: 00:1d.0 10 * [0x82843000 - 0x828433ff] limit: 828433ff mem PCI: 00:1f.3 10 * [0x82844000 - 0x828440ff] limit: 828440ff mem PCI: 00:16.0 10 * [0x82845000 - 0x8284500f] limit: 8284500f mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done PCI: 00:1c.0 mem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff PCI: 00:1c.0: Resource ranges: * Base: 82200000, Size: 100000, Tag: 200 PCI: 01:00.0 10 * [0x82200000 - 0x82200fff] limit: 82200fff mem PCI: 00:1c.0 mem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff done PCI: 00:1c.1 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff PCI: 00:1c.1: Resource ranges: * Base: 82300000, Size: 100000, Tag: 200 PCI: 02:00.0 10 * [0x82300000 - 0x82301fff] limit: 82301fff mem PCI: 00:1c.1 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === PCI: 00:02.0 10 <- [0x0082400000 - 0x00827fffff] size 0x00400000 gran 0x16 mem64 PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:03.0 10 <- [0x0082838000 - 0x008283bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:04.0 10 <- [0x0082830000 - 0x0082837fff] size 0x00008000 gran 0x0f mem64 PCI: 00:14.0 10 <- [0x0082820000 - 0x008282ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:16.0 10 <- [0x0082845000 - 0x008284500f] size 0x00000010 gran 0x04 mem64 PCI: 00:19.0 10 <- [0x0082800000 - 0x008281ffff] size 0x00020000 gran 0x11 mem PCI: 00:19.0 14 <- [0x0082840000 - 0x0082840fff] size 0x00001000 gran 0x0c mem PCI: 00:19.0 18 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io PCI: 00:1a.0 10 <- [0x0082842000 - 0x00828423ff] size 0x00000400 gran 0x0a mem PCI: 00:1b.0 10 <- [0x008283c000 - 0x008283ffff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x0082200000 - 0x00822fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 10 <- [0x0082200000 - 0x0082200fff] size 0x00001000 gran 0x0c mem PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:1c.1 20 <- [0x0082300000 - 0x00823fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 02:00.0 10 <- [0x0082300000 - 0x0082301fff] size 0x00002000 gran 0x0d mem64 PCI: 00:1d.0 10 <- [0x0082843000 - 0x00828433ff] size 0x00000400 gran 0x0a mem PNP: 00ff.1 missing set_resources PNP: 00ff.2 missing set_resources PCI: 00:1f.2 10 <- [0x0000001080 - 0x0000001087] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000001090 - 0x0000001093] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000001088 - 0x000000108f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000001094 - 0x0000001097] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x0082841000 - 0x00828417ff] size 0x00000800 gran 0x0b mem PCI: 00:1f.3 10 <- [0x0082844000 - 0x00828440ff] size 0x00000100 gran 0x08 mem64 Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms Enabling resources... PCI: 00:00.0 subsystem <- 17aa/220e PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 17aa/220e PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 subsystem <- 17aa/220e PCI: 00:03.0 cmd <- 02 PCI: 00:04.0 cmd <- 02 PCI: 00:14.0 subsystem <- 17aa/220e PCI: 00:14.0 cmd <- 102 PCI: 00:16.0 subsystem <- 17aa/220e PCI: 00:16.0 cmd <- 02 PCI: 00:19.0 subsystem <- 17aa/220e PCI: 00:19.0 cmd <- 103 PCI: 00:1a.0 subsystem <- 17aa/220e PCI: 00:1a.0 cmd <- 102 PCI: 00:1b.0 subsystem <- 17aa/220e PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0013 PCI: 00:1c.0 subsystem <- 17aa/220e PCI: 00:1c.0 cmd <- 06 PCI: 00:1c.1 bridge ctrl <- 0013 PCI: 00:1c.1 subsystem <- 17aa/220e PCI: 00:1c.1 cmd <- 06 PCI: 00:1d.0 subsystem <- 17aa/220e PCI: 00:1d.0 cmd <- 102 PCI: 00:1f.0 subsystem <- 17aa/220e PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 17aa/220e PCI: 00:1f.2 cmd <- 103 PCI: 00:1f.3 subsystem <- 17aa/220e PCI: 00:1f.3 cmd <- 103 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 cmd <- 02 done. Found TPM ST33ZP24 by ST Microelectronics TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 TPM: setup succeeded BS: BS_DEV_INIT entry times (exec / console): 45 / 0 ms Initializing devices... CPU_CLUSTER: 0 init MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 0 0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1 0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0 0x0000000100000000 - 0x000000047de00000 size 0x37de00000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 4/5. MTRR: WB selected as default type. MTRR: 0 base 0x0000000080000000 mask 0x0000007ff0000000 type 0 MTRR: 1 base 0x0000000090000000 mask 0x0000007ff0000000 type 1 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0 MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Initializing VR config. CPU has 4 cores, 8 threads enabled. Setting up SMI for CPU Will perform SMM setup. CBFS: Found 'cpu_microcode_blob.bin' @0x8080 size 0xb400 in mcache @0x7f7dd0ac microcode: sig=0x306c3 pf=0x10 revision=0x28 CPU: Intel(R) Core(TM) i7-4700MQ CPU @ 2.40GHz. Setting up local APIC 0x0 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 Processing 18 relocs. Offset value of 0x00030000 Attempting to start 7 APs Starting CPUs in xapic mode Waiting for 10ms after sending INIT. Waiting for SIPI to complete... done. Waiting for SIPI to complete... Setting up local APIC 0x1 done. AP: slot 1 apic_id 1, MCU rev: 0x00000028 Setting up local APIC 0x2 Setting up local APIC 0x3 AP: slot 2 apic_id 2, MCU rev: 0x00000028 AP: slot 3 apic_id 3, MCU rev: 0x00000028 Setting up local APIC 0x4 Setting up local APIC 0x5 AP: slot 4 apic_id 4, MCU rev: 0x00000028 AP: slot 6 apic_id 5, MCU rev: 0x00000028 Setting up local APIC 0x7 Setting up local APIC 0x6 AP: slot 5 apic_id 7, MCU rev: 0x00000028 AP: slot 7 apic_id 6, MCU rev: 0x00000028 smm_stub_place_stacks: cpus: 8 : stack space: needed -> 2000 smm_stub_place_stacks: exit, stack_top 0x7f802000 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8 Processing 11 relocs. Offset value of 0x00038000 smm_module_setup_stub: stack_end = 0x7f800000 smm_module_setup_stub: stack_top = 0x7f802000 smm_module_setup_stub: stack_size = 0x400 smm_module_setup_stub: runtime.start32_offset = 0x4c smm_module_setup_stub: runtime.smm_size = 0x10000 SMM Module: stub loaded at 0x00038000. Will call 0x7f79f56a Installing permanent SMM handler to 0x7f800000 smm_load_module: total_smm_space_needed 8960, available -> 300000 Loading module at 0x7fafa000 with entry 0x7fafa6fd. filesize: 0x1918 memsize: 0x5960 Processing 80 relocs. Offset value of 0x7fafa000 smm_load_module: smram_start: 0x0x7f800000 smm_load_module: smram_end: 0x7fb00000 smm_load_module: stack_top: 0x7f802000 smm_load_module: handler start 0x7fafa6fd smm_load_module: handler_size 62c0 smm_load_module: fxsave_area 0x7faff000 smm_load_module: fxsave_size 1000 smm_load_module: CONFIG_MSEG_SIZE 0x0 smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0 smm_load_module: handler_mod_params.smbase = 0x7f800000 smm_load_module: per_cpu_save_state_size = 0x400 smm_load_module: num_cpus = 0x8 smm_load_module: total_save_state_size = 0x2000 smm_load_module: cpu0 entry: 0x7faea000 smm_create_map: cpus allowed in one segment 30 smm_create_map: min # of segments needed 1 smm_stub_place_stacks: cpus: 8 : stack space: needed -> 2000 smm_stub_place_stacks: exit, stack_top 0x7f802000 Loading module at 0x7faf2000 with entry 0x7faf2000. filesize: 0x1e8 memsize: 0x1e8 Processing 11 relocs. Offset value of 0x7faf2000 smm_place_entry_code: smbase 7fae8400, stack_top 7f802000 SMM Module: placing smm entry code at 7faf1c00, cpu # 0x1 smm_place_entry_code: copying from 7faf2000 to 7faf1c00 0x1e8 bytes SMM Module: placing smm entry code at 7faf1800, cpu # 0x2 smm_place_entry_code: copying from 7faf2000 to 7faf1800 0x1e8 bytes SMM Module: placing smm entry code at 7faf1400, cpu # 0x3 smm_place_entry_code: copying from 7faf2000 to 7faf1400 0x1e8 bytes SMM Module: placing smm entry code at 7faf1000, cpu # 0x4 smm_place_entry_code: copying from 7faf2000 to 7faf1000 0x1e8 bytes SMM Module: placing smm entry code at 7faf0c00, cpu # 0x5 smm_place_entry_code: copying from 7faf2000 to 7faf0c00 0x1e8 bytes SMM Module: placing smm entry code at 7faf0800, cpu # 0x6 smm_place_entry_code: copying from 7faf2000 to 7faf0800 0x1e8 bytes SMM Module: placing smm entry code at 7faf0400, cpu # 0x7 smm_place_entry_code: copying from 7faf2000 to 7faf0400 0x1e8 bytes smm_module_setup_stub: stack_end = 0x7f800000 smm_module_setup_stub: stack_top = 0x7f802000 smm_module_setup_stub: stack_size = 0x400 smm_module_setup_stub: runtime.start32_offset = 0x4c smm_module_setup_stub: runtime.smm_size = 0x300000 SMM Module: stub loaded at 0x7faf2000. Will call 0x7fafa6fd Initializing Southbridge SMI... SMI_STS: MCSMI PM1 TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea000, cpu = 0 In relocation handler: CPU 0 New SMBASE=0x7faea000 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9c00, cpu = 1 In relocation handler: CPU 1 New SMBASE=0x7fae9c00 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae8400, cpu = 7 In relocation handler: CPU 7 New SMBASE=0x7fae8400 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae8c00, cpu = 5 In relocation handler: CPU 5 New SMBASE=0x7fae8c00 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae8800, cpu = 6 In relocation handler: CPU 6 New SMBASE=0x7fae8800 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9000, cpu = 4 In relocation handler: CPU 4 New SMBASE=0x7fae9000 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9800, cpu = 2 In relocation handler: CPU 2 New SMBASE=0x7fae9800 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fae9400, cpu = 3 In relocation handler: CPU 3 New SMBASE=0x7fae9400 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date Initializing CPU #0 CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 Setting up local APIC 0x0 IA32_FEATURE_CONTROL already locked; VMX status: enabled IA32_FEATURE_CONTROL already locked cpu: energy policy set to 6 Turbo is available but hidden Turbo is available and visible CPU #0 initialized Initializing CPU #1 Initializing CPU #5 Initializing CPU #7 CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 Initializing CPU #4 Initializing CPU #6 CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 Initializing CPU #2 Initializing CPU #3 CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 Setting up local APIC 0x1 Setting up local APIC 0x7 Setting up local APIC 0x6 IA32_FEATURE_CONTROL already locked; IA32_FEATURE_CONTROL already locked; VMX status: enabled VMX status: enabled IA32_FEATURE_CONTROL already locked IA32_FEATURE_CONTROL already locked CPU: vendor Intel device 306c3 CPU: family 06, model 3c, stepping 03 IA32_FEATURE_CONTROL already locked; VMX status: enabled Setting up local APIC 0x2 Setting up local APIC 0x4 Setting up local APIC 0x5 IA32_FEATURE_CONTROL already locked; IA32_FEATURE_CONTROL already locked; VMX status: enabled VMX status: enabled IA32_FEATURE_CONTROL already locked IA32_FEATURE_CONTROL already locked IA32_FEATURE_CONTROL already locked IA32_FEATURE_CONTROL already locked; VMX status: enabled Setting up local APIC 0x3 IA32_FEATURE_CONTROL already locked IA32_FEATURE_CONTROL already locked; VMX status: enabled cpu: energy policy set to 6 cpu: energy policy set to 6 CPU #7 initialized CPU #5 initialized IA32_FEATURE_CONTROL already locked cpu: energy policy set to 6 CPU #1 initialized cpu: energy policy set to 6 cpu: energy policy set to 6 cpu: energy policy set to 6 CPU #2 initialized CPU #6 initialized CPU #4 initialized cpu: energy policy set to 6 CPU #3 initialized bsp_do_flight_plan done after 3 msecs. CPU: frequency set to 3400 Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 18 msecs PCI: 00:00.0 init Disabling PEG12. Disabling PEG11. Disabling PEG10. Disabling "device 7". Set BIOS_RESET_CPL CPU TDP: 47 Watts PCI: 00:00.0 init finished in 1 msecs PCI: 00:02.0 init CBFS: Found 'vbt.bin' @0x338c0 size 0x582 in mcache @0x7f7dd1f4 Found a VBT of 4608 bytes after decompression GMA: Found VBT in CBFS GMA: Found valid VBT in CBFS GT Power Management Init GMA: Setting backlight PWM frequency to 135MHz / 128 / 4794 = 220Hz framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000 GT Power Management Init (post VBIOS) PCI: 00:02.0 init finished in 208 msecs PCI: 00:03.0 init Mini-HD: base = 0x82838000 HDA: No codec! PCI: 00:03.0 init finished in 51 msecs PCI: 00:04.0 init PCI: 00:04.0 init finished in 0 msecs PCI: 00:14.0 init PCI: 00:14.0 init finished in 0 msecs PCI: 00:16.0 init intel_me_path: mbp is not ready! ME: BIOS path: Error ME: MBP not ready PCI: 00:16.0 init finished in 0 msecs PCI: 00:19.0 init PCI: 00:19.0 init finished in 0 msecs PCI: 00:1a.0 init EHCI: Setting up controller.. done. PCI: 00:1a.0 init finished in 0 msecs PCI: 00:1b.0 init Azalia: base = 0x8283c000 Azalia: codec_mask = 01 azalia_audio: Initializing codec #0 azalia_audio: codec viddid: 10ec0292 azalia_audio: verb_size: 128 azalia_audio: verb loaded. PCI: 00:1b.0 init finished in 7 msecs PCI: 00:1c.0 init Initializing PCH PCIe bridge. PCI: 00:1c.0 init finished in 0 msecs PCI: 00:1c.1 init Initializing PCH PCIe bridge. PCI: 00:1c.1 init finished in 0 msecs PCI: 00:1d.0 init EHCI: Setting up controller.. done. PCI: 00:1d.0 init finished in 0 msecs PCI: 00:1f.0 init pch: lpc_init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: ID = 0x02 IOAPIC: 24 interrupts IOAPIC: Clearing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 Set power off after power failure. NMI sources enabled. LynxPoint H PM init RTC: failed = 0x0 RTC Init apm_control: Disabling ACPI. APMC done. PCI: 00:1f.0 init finished in 0 msecs PCI: 00:1f.2 init SATA: Initializing... SATA: Controller in AHCI mode. ABAR: 0x82841000 PCI: 00:1f.2 init finished in 0 msecs PCI: 00:1f.3 init PCI: 00:1f.3 init finished in 0 msecs PCI: 01:00.0 init PCI: 01:00.0 init finished in 0 msecs PCI: 02:00.0 init PCI: 02:00.0 init finished in 0 msecs PNP: 00ff.2 init PNP: 00ff.2 init finished in 0 msecs Devices initialized BS: BS_DEV_INIT run times (exec / console): 287 / 0 ms clear_memory: Clearing DRAM 0000000000000000-0000000000005000 clear_memory: Clearing DRAM 000000000000a000-00000000000a0000 clear_memory: Clearing DRAM 00000000000c0000-000000007f76e000 clear_memory: Clearing DRAM 000000007f800000-0000000080000000 clear_memory: Clearing DRAM 0000000100000000-000000047de00000 memset_pae: Using virtual address 0x00200000 as scratchpad memset_pae: Using address 0x00005000 for page tables clear_memory: Clearing DRAM 0000000000005000-000000000000a000 BS: BS_DEV_INIT exit times (exec / console): 783 / 0 ms Finalize devices... PCI: 00:00.0 final PCI: 00:16.0 final ME: MBP cleared PCI: 00:1b.0 final PCI: 00:1f.0 final apm_control: Finalizing SMM. APMC done. Devices finalized CBFS: Found 'fallback/dsdt.aml' @0x30240 size 0x3652 in mcache @0x7f7dd1c8 CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 7f742000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * SSDT Found 1 CPU(s) with 8 core(s) each. PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 PSS: 2401MHz power 47000 control 0x2200 status 0x2200 PSS: 2400MHz power 47000 control 0x1800 status 0x1800 PSS: 2000MHz power 37350 control 0x1400 status 0x1400 PSS: 1600MHz power 28516 control 0x1000 status 0x1000 PSS: 1200MHz power 20398 control 0xc00 status 0xc00 PSS: 800MHz power 12927 control 0x800 status 0x800 Generating ACPI PIRQ entries ACPI: * H8 H8: BDC detection not implemented. Assuming BDC installed H8: WWAN detection not implemented. Assuming WWAN installed \_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at 0x7f732000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = 7f748230 ACPI: * HPET ACPI: added table 6/32, length now 60 current = 7f748270 ACPI: done. ACPI tables: 25200 bytes. smbios_write_tables: 7f731000 SMBIOS firmware version is set to coreboot_version: '4.15-204-gdfa70bd036' Create SMBIOS type 16 Create SMBIOS type 17 Create SMBIOS type 20 PCI: 02:00.0 (unknown) SMBIOS tables: 1120 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 2068 Writing coreboot table at 0x7f766000 CBFS: Found 'cmos_layout.bin' @0x33fc0 size 0x574 in mcache @0x7f7dd24c 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007f730fff: RAM 4. 000000007f731000-000000007f780fff: CONFIGURATION TABLES 5. 000000007f781000-000000007f7cdfff: RAMSTAGE 6. 000000007f7ce000-000000007f7fffff: CONFIGURATION TABLES 7. 000000007f800000-00000000821fffff: RESERVED 8. 00000000f0000000-00000000f3ffffff: RESERVED 9. 00000000fed10000-00000000fed19fff: RESERVED 10. 00000000fed40000-00000000fed44fff: RESERVED 11. 00000000fed80000-00000000fed84fff: RESERVED 12. 0000000100000000-000000047ddfffff: RAM Wrote coreboot table at: 0x7f766000, 0x988 bytes, checksum 6d1e coreboot table: 2464 bytes. IMD ROOT 0. 0x7f7ff000 0x00001000 IMD SMALL 1. 0x7f7fe000 0x00001000 CONSOLE 2. 0x7f7de000 0x00020000 RO MCACHE 3. 0x7f7dd000 0x000004f4 TIME STAMP 4. 0x7f7dc000 0x00000910 MRC DATA 5. 0x7f7db000 0x00000fe4 MEM INFO 6. 0x7f7da000 0x000003b8 ROMSTG STCK 7. 0x7f7d9000 0x00001000 AFTER CAR 8. 0x7f7ce000 0x0000b000 RAMSTAGE 9. 0x7f780000 0x0004e000 SMM BACKUP 10. 0x7f770000 0x00010000 4f444749 11. 0x7f76e000 0x00002000 COREBOOT 12. 0x7f766000 0x00008000 ACPI 13. 0x7f742000 0x00024000 TCPA TCGLOG14. 0x7f732000 0x00010000 SMBIOS 15. 0x7f731000 0x00001000 IMD small region: IMD ROOT 0. 0x7f7fec00 0x00000400 FMAP 1. 0x7f7feb20 0x000000e0 ROMSTAGE 2. 0x7f7feb00 0x00000004 ACPI GNVS 3. 0x7f7fea40 0x000000b0 BS: BS_WRITE_TABLES run times (exec / console): 5 / 0 ms CBFS: Found 'fallback/payload' @0x396c0 size 0xf894 in mcache @0x7f7dd2b8 Checking segment from ROM address 0xff4698ec Payload being loaded at below 1MiB without region being marked as RAM usable. Checking segment from ROM address 0xff469908 Loading segment from ROM address 0xff4698ec code (compression=1) New segment dstaddr 0x000e3b80 memsize 0x1c480 srcaddr 0xff469924 filesize 0xf85c Loading Segment: addr: 0x000e3b80 memsz: 0x000000000001c480 filesz: 0x000000000000f85c using LZMA Loading segment from ROM address 0xff469908 Entry Point 0x000fd776 BS: BS_PAYLOAD_LOAD run times (exec / console): 25 / 0 ms ICH-NM10-PCH: watchdog disabled Jumping to boot code at 0x000fd776(0x7f766000) ```
jrhoades commented 2 years ago
Poster

Some updates from the coreboot folks here: https://ticket.coreboot.org/issues/432

Their investigations seem to point to a potential issue with the ifd blob as used within the osbmk process.

I noticed that the documentation for the ifd for the t440p referenced the need to track down the ifd yourself: https://osboot.org/docs/build/#optional-extract-binary-blobs

...but during my osbmk compilation step this appeared to have been taken care of as a result of the ifd.bin extracted from a Lenovo source. This ticket seems to have addressed this, but maybe introduced something to related here: #129

Some updates from the coreboot folks here: https://ticket.coreboot.org/issues/432 Their investigations seem to point to a potential issue with the ifd blob as used within the osbmk process. I noticed that the documentation for the ifd for the t440p referenced the need to track down the ifd yourself: https://osboot.org/docs/build/#optional-extract-binary-blobs ...but during my osbmk compilation step this appeared to have been taken care of as a result of the ifd.bin extracted from a Lenovo source. This ticket seems to have addressed this, but maybe introduced something to related here: https://notabug.org/osboot/osbmk/issues/129

Thank you for a detailed bug report, I have the same issue with an osboot-flashed T440p (already discussed with the developer over e-mail and IRC) and would be interested to have the bug fix too when it is available.

The bug reproduces for me using both Ubuntu 22.04 and Debian 11 with all updates, the only difference (AFAIR) is that in Debian the suspended laptop powers on by keyboard and in Ubuntu it does not. In either case the power button continues to fade in and out after the botched resume. The BIOS identifies itself as follows:

Handle 0x0000, DMI type 0, 26 bytes
BIOS Information
        Vendor: coreboot
        Version: 4.15-204-gcf1d1fa672
        Release Date: 03/20/2022
        ROM Size: 12 MB
        Characteristics:
                PCI is supported
                PC Card (PCMCIA) is supported
                BIOS is upgradeable
                Selectable boot is supported
                ACPI is supported
                Targeted content distribution is supported
        BIOS Revision: 4.15
        Firmware Revision: 0.0
Thank you for a detailed bug report, I have the same issue with an osboot-flashed T440p (already discussed with the developer over e-mail and IRC) and would be interested to have the bug fix too when it is available. The bug reproduces for me using both Ubuntu 22.04 and Debian 11 with all updates, the only difference (AFAIR) is that in Debian the suspended laptop powers on by keyboard and in Ubuntu it does not. In either case the power button continues to fade in and out after the botched resume. The BIOS identifies itself as follows: ```text Handle 0x0000, DMI type 0, 26 bytes BIOS Information Vendor: coreboot Version: 4.15-204-gcf1d1fa672 Release Date: 03/20/2022 ROM Size: 12 MB Characteristics: PCI is supported PC Card (PCMCIA) is supported BIOS is upgradeable Selectable boot is supported ACPI is supported Targeted content distribution is supported BIOS Revision: 4.15 Firmware Revision: 0.0 ```
jrhoades commented 2 years ago
Poster

Just thinking out loud: the t440p ifd.bin blob is committed part of the osbmk repo. But looking at the obwww repo, this commit added documentation talking about how to extract or download the binary blobs from board: 85dbbf2abb

The docs referenced this command:

./build descriptors intel_blobs t440p_12mb /path/to/12mb_backup.rom

...but running that just comes back with a USAGE message.

Running:

./build descriptors list

...shows:

Available options for mode 'descriptors':

ich9m

Running the command with ich9m:

./build descriptors ich9m t440p_12mb /path/to/12mb_backup.rom

Appears to perform operations with ich9utils, but I'm sort of out of my depth in terms of what to do with it.

Given that my device is already flashed (likely with an invalid ifd.bin), and the ifd.bin provided with the osbmk repo appears to have a sizing issue, I'm wondering the best way to get the ifd.bin to correct the issue myself.

I found where osbmk extracts the ME bin from a Lenovo firmware patch, but I didn't find anything similar for getting your own ifd.bin (sketchy-looking Google results aside).

Just thinking out loud: the t440p `ifd.bin` blob is committed part of the osbmk repo. But looking at the obwww repo, this commit added documentation talking about how to extract or download the binary blobs from board: <https://notabug.org/osboot/osbwww/commit/85dbbf2abb4207e206a15669797ad76ccf46517f> The docs referenced this command: ``` ./build descriptors intel_blobs t440p_12mb /path/to/12mb_backup.rom ``` ...but running that just comes back with a `USAGE` message. Running: ``` ./build descriptors list ``` ...shows: ``` Available options for mode 'descriptors': ich9m ``` Running the command with `ich9m`: ``` ./build descriptors ich9m t440p_12mb /path/to/12mb_backup.rom ``` Appears to perform operations with ich9utils, but I'm sort of out of my depth in terms of what to do with it. Given that my device is already flashed (likely with an invalid `ifd.bin`), and the `ifd.bin` provided with the osbmk repo appears to have a sizing issue, I'm wondering the best way to get the `ifd.bin` to correct the issue myself. I found where osbmk extracts the ME bin from a Lenovo firmware patch, but I didn't find anything similar for getting your own `ifd.bin` (sketchy-looking Google results aside).

The firmware descriptor for this board is manually modified, which may have caused the issue. I pulled the ifd from a donor board with the factory 9.0 ME version. Since Lenovo only offers updates for download (not the factory version) I manually resized the region's to match the size of the newer ME automatically downloaded in osbmk.

You are on the right track to try manually extracting the blobs and flashing with that instead. I forgot to update the documentation when I cleaned up the way blobs are dealt with. The correct command is

./blobutil extract

Rather than

./build descriptors

The firmware descriptor for this board is manually modified, which may have caused the issue. I pulled the ifd from a donor board with the factory 9.0 ME version. Since Lenovo only offers updates for download (not the factory version) I manually resized the region's to match the size of the newer ME automatically downloaded in osbmk. You are on the right track to try manually extracting the blobs and flashing with that instead. I forgot to update the documentation when I cleaned up the way blobs are dealt with. The correct command is `./blobutil extract` Rather than `./build descriptors`
dovsienko commented 1 year ago

In case it helps to fix this problem, flashing the most recent release of Skulls coreboot distribution on the T440p laptop makes the problem disappear: suspend and resume work normally as expected.

In case it helps to fix this problem, flashing the most recent release of Skulls coreboot distribution on the T440p laptop makes the problem disappear: suspend and resume work normally as expected.
Nazar65 commented 1 year ago

Hello there, i just have same issue and was trying to build rom with original ifd.bin and me extracted from original rom. But issue is there, even i have builded the obmk with a commit before ifd.bin was added, still same issue. Laptop gets restarted after suspend.

Hello there, i just have same issue and was trying to build rom with original ifd.bin and me extracted from original rom. But issue is there, even i have builded the obmk with a commit before ifd.bin was added, still same issue. Laptop gets restarted after suspend.
jrhoades commented 1 year ago
Poster

@Nazar65, thanks for the confirmation.

In this last week I tried building from the new LBMK scripts after the libreboot / osboot project merge (see: https://notabug.org/libreboot/lbmk.git). However, the image produced had the same issue as before.

For what it's worth, I was able to get a working "wake from suspend" using the Skulls coreboot (at version 1.0.6, if that helps): https://github.com/merge/skulls/releases/tag/1.0.6 (thanks, @dovsienko)

@Nazar65, thanks for the confirmation. In this last week I tried building from the new LBMK scripts after the libreboot / osboot project merge (see: https://notabug.org/libreboot/lbmk.git). However, the image produced had the same issue as before. For what it's worth, I was able to get a working "wake from suspend" using the Skulls coreboot (at version 1.0.6, if that helps): https://github.com/merge/skulls/releases/tag/1.0.6 (thanks, @dovsienko)
Nazar65 commented 1 year ago

I will switch to coreboot for now, since there it is working as well for me, i have followed this instructions https://blog.0xcb.dev/lenovo-t440p-coreboot/ with latest coreboot suspend and wakeup works just fine. Will wait for some updates here.

I will switch to coreboot for now, since there it is working as well for me, i have followed this instructions https://blog.0xcb.dev/lenovo-t440p-coreboot/ with latest coreboot suspend and wakeup works just fine. Will wait for some updates here.
Nazar65 commented 1 year ago

Hello i managed to fix this by building my own coreboot with my .config file, looks like the problem is in one of the config there. I have builded my own coreboot and then added grub payload from libreboot with configurations and etc. And now suspend and wake works just fine

Hello i managed to fix this by building my own coreboot with my .config file, looks like the problem is in one of the config there. I have builded my own coreboot and then added grub payload from libreboot with configurations and etc. And now suspend and wake works just fine
shmalebx9 commented 1 year ago

Nazar65 can you let me know the coreboot version you built from and the sha1sum hash of the ifd you used. If I have those I can figure out how to solve this issue permanently in lbmk. I'll leave instructions below on how to get that info, but please don't be offended if you think I'm treating you like a n00b, I'm only trying to make things quick and easy for you. I really would appreciate your help.

For the coreboot revision: git log -1 | awk 'NR==1 {print $2}' in the coreboot directory.

For the ifd hash: sha1sum /path/to/descriptor

Nazar65 can you let me know the coreboot version you built from and the sha1sum hash of the ifd you used. If I have those I can figure out how to solve this issue permanently in lbmk. I'll leave instructions below on how to get that info, but please don't be offended if you think I'm treating you like a n00b, I'm only trying to make things quick and easy for you. I really would appreciate your help. **For the coreboot revision:** `git log -1 | awk 'NR==1 {print $2}'` in the coreboot directory. **For the ifd hash:** `sha1sum /path/to/descriptor`
Nazar65 commented 1 year ago

Hello @shmalebx9 the git revision of coreboot is "f4c97ea131" and the sha1sum for ifd is "71f9d5eee3" it was extracted from the original rom

Hello @shmalebx9 the git revision of coreboot is "f4c97ea131944c7be940b35361407e4b63a14faf" and the sha1sum for ifd is "71f9d5eee376a637879d035ef82f52982a43e8e8" it was extracted from the original rom
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