dv-bfin_otp.c 8.0 KB

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  1. /* Blackfin One-Time Programmable Memory (OTP) model
  2. Copyright (C) 2010-2015 Free Software Foundation, Inc.
  3. Contributed by Analog Devices, Inc.
  4. This file is part of simulators.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 3 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program. If not, see <http://www.gnu.org/licenses/>. */
  15. #include "config.h"
  16. #include "sim-main.h"
  17. #include "devices.h"
  18. #include "dv-bfin_otp.h"
  19. /* XXX: No public documentation on this interface. This seems to work
  20. with the on-chip ROM functions though and was figured out by
  21. disassembling & walking that code. */
  22. /* XXX: About only thing that should be done here are CRC fields. And
  23. supposedly there is an interrupt that could be generated. */
  24. struct bfin_otp
  25. {
  26. bu32 base;
  27. /* The actual OTP storage -- 0x200 pages, each page is 128bits.
  28. While certain pages have predefined and/or secure access, we don't
  29. bother trying to implement that coverage. All pages are open for
  30. reading & writing. */
  31. bu32 mem[0x200 * 4];
  32. /* Order after here is important -- matches hardware MMR layout. */
  33. bu16 BFIN_MMR_16(control);
  34. bu16 BFIN_MMR_16(ben);
  35. bu16 BFIN_MMR_16(status);
  36. bu32 timing;
  37. bu32 _pad0[28];
  38. bu32 data0, data1, data2, data3;
  39. };
  40. #define mmr_base() offsetof(struct bfin_otp, control)
  41. #define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base())
  42. #define mmr_idx(mmr) (mmr_offset (mmr) / 4)
  43. static const char * const mmr_names[] =
  44. {
  45. "OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING",
  46. [mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3",
  47. };
  48. #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
  49. /* XXX: This probably misbehaves with big endian hosts. */
  50. static void
  51. bfin_otp_transfer (struct bfin_otp *otp, void *vdst, void *vsrc)
  52. {
  53. bu8 *dst = vdst, *src = vsrc;
  54. int bidx;
  55. for (bidx = 0; bidx < 16; ++bidx)
  56. if (otp->ben & (1 << bidx))
  57. dst[bidx] = src[bidx];
  58. }
  59. static void
  60. bfin_otp_read_page (struct bfin_otp *otp, bu16 page)
  61. {
  62. bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]);
  63. }
  64. static void
  65. bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2])
  66. {
  67. bfin_otp_transfer (otp, &otp->mem[page * 4], val);
  68. }
  69. static void
  70. bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi)
  71. {
  72. bu64 val[2] = { lo, hi };
  73. bfin_otp_write_page_val (otp, page, val);
  74. }
  75. static void
  76. bfin_otp_write_page (struct bfin_otp *otp, bu16 page)
  77. {
  78. bfin_otp_write_page_val (otp, page, (void *)&otp->data0);
  79. }
  80. static unsigned
  81. bfin_otp_io_write_buffer (struct hw *me, const void *source, int space,
  82. address_word addr, unsigned nr_bytes)
  83. {
  84. struct bfin_otp *otp = hw_data (me);
  85. bu32 mmr_off;
  86. bu32 value;
  87. bu16 *value16p;
  88. bu32 *value32p;
  89. void *valuep;
  90. if (nr_bytes == 4)
  91. value = dv_load_4 (source);
  92. else
  93. value = dv_load_2 (source);
  94. mmr_off = addr - otp->base;
  95. valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
  96. value16p = valuep;
  97. value32p = valuep;
  98. HW_TRACE_WRITE ();
  99. switch (mmr_off)
  100. {
  101. case mmr_offset(control):
  102. {
  103. int page;
  104. dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  105. /* XXX: Seems like these bits aren't writable. */
  106. *value16p = value & 0x39FF;
  107. /* Low bits seem to be the page address. */
  108. page = value & PAGE_ADDR;
  109. /* Write operation. */
  110. if (value & DO_WRITE)
  111. bfin_otp_write_page (otp, page);
  112. /* Read operation. */
  113. if (value & DO_READ)
  114. bfin_otp_read_page (otp, page);
  115. otp->status |= STATUS_DONE;
  116. break;
  117. }
  118. case mmr_offset(ben):
  119. dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  120. /* XXX: All bits seem to be writable. */
  121. *value16p = value;
  122. break;
  123. case mmr_offset(status):
  124. dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  125. /* XXX: All bits seem to be W1C. */
  126. dv_w1c_2 (value16p, value, -1);
  127. break;
  128. case mmr_offset(timing):
  129. case mmr_offset(data0):
  130. case mmr_offset(data1):
  131. case mmr_offset(data2):
  132. case mmr_offset(data3):
  133. dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
  134. *value32p = value;
  135. break;
  136. default:
  137. dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
  138. break;
  139. }
  140. return nr_bytes;
  141. }
  142. static unsigned
  143. bfin_otp_io_read_buffer (struct hw *me, void *dest, int space,
  144. address_word addr, unsigned nr_bytes)
  145. {
  146. struct bfin_otp *otp = hw_data (me);
  147. bu32 mmr_off;
  148. bu16 *value16p;
  149. bu32 *value32p;
  150. void *valuep;
  151. mmr_off = addr - otp->base;
  152. valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
  153. value16p = valuep;
  154. value32p = valuep;
  155. HW_TRACE_READ ();
  156. switch (mmr_off)
  157. {
  158. case mmr_offset(control):
  159. case mmr_offset(ben):
  160. case mmr_offset(status):
  161. dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
  162. dv_store_2 (dest, *value16p);
  163. break;
  164. case mmr_offset(timing):
  165. case mmr_offset(data0):
  166. case mmr_offset(data1):
  167. case mmr_offset(data2):
  168. case mmr_offset(data3):
  169. dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
  170. dv_store_4 (dest, *value32p);
  171. break;
  172. default:
  173. dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
  174. break;
  175. }
  176. return nr_bytes;
  177. }
  178. static void
  179. attach_bfin_otp_regs (struct hw *me, struct bfin_otp *otp)
  180. {
  181. address_word attach_address;
  182. int attach_space;
  183. unsigned attach_size;
  184. reg_property_spec reg;
  185. if (hw_find_property (me, "reg") == NULL)
  186. hw_abort (me, "Missing \"reg\" property");
  187. if (!hw_find_reg_array_property (me, "reg", 0, &reg))
  188. hw_abort (me, "\"reg\" property must contain three addr/size entries");
  189. hw_unit_address_to_attach_address (hw_parent (me),
  190. &reg.address,
  191. &attach_space, &attach_address, me);
  192. hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
  193. if (attach_size != BFIN_MMR_OTP_SIZE)
  194. hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE);
  195. hw_attach_address (hw_parent (me),
  196. 0, attach_space, attach_address, attach_size, me);
  197. otp->base = attach_address;
  198. }
  199. static const struct hw_port_descriptor bfin_otp_ports[] =
  200. {
  201. { "stat", 0, 0, output_port, },
  202. { NULL, 0, 0, 0, },
  203. };
  204. static void
  205. bfin_otp_finish (struct hw *me)
  206. {
  207. char part_str[16];
  208. struct bfin_otp *otp;
  209. unsigned int fps03;
  210. int type = hw_find_integer_property (me, "type");
  211. otp = HW_ZALLOC (me, struct bfin_otp);
  212. set_hw_data (me, otp);
  213. set_hw_io_read_buffer (me, bfin_otp_io_read_buffer);
  214. set_hw_io_write_buffer (me, bfin_otp_io_write_buffer);
  215. set_hw_ports (me, bfin_otp_ports);
  216. attach_bfin_otp_regs (me, otp);
  217. /* Initialize the OTP. */
  218. otp->ben = 0xFFFF;
  219. otp->timing = 0x00001485;
  220. /* Semi-random value for unique chip id. */
  221. bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp);
  222. memset (part_str, 0, sizeof (part_str));
  223. sprintf (part_str, "ADSP-BF%iX", type);
  224. switch (type)
  225. {
  226. case 512:
  227. fps03 = FPS03_BF512;
  228. break;
  229. case 514:
  230. fps03 = FPS03_BF514;
  231. break;
  232. case 516:
  233. fps03 = FPS03_BF516;
  234. break;
  235. case 518:
  236. fps03 = FPS03_BF518;
  237. break;
  238. case 522:
  239. fps03 = FPS03_BF522;
  240. break;
  241. case 523:
  242. fps03 = FPS03_BF523;
  243. break;
  244. case 524:
  245. fps03 = FPS03_BF524;
  246. break;
  247. case 525:
  248. fps03 = FPS03_BF525;
  249. break;
  250. case 526:
  251. fps03 = FPS03_BF526;
  252. break;
  253. case 527:
  254. fps03 = FPS03_BF527;
  255. break;
  256. default:
  257. fps03 = 0;
  258. break;
  259. }
  260. part_str[14] = (fps03 >> 0);
  261. part_str[15] = (fps03 >> 8);
  262. bfin_otp_write_page_val (otp, FPS03, (void *)part_str);
  263. }
  264. const struct hw_descriptor dv_bfin_otp_descriptor[] =
  265. {
  266. {"bfin_otp", bfin_otp_finish,},
  267. {NULL, NULL},
  268. };