dv-bfin_eppi.c 7.1 KB

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  1. /* Blackfin Enhanced Parallel Port Interface (EPPI) model
  2. For "new style" PPIs on BF54x/etc... parts.
  3. Copyright (C) 2010-2015 Free Software Foundation, Inc.
  4. Contributed by Analog Devices, Inc.
  5. This file is part of simulators.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 3 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program. If not, see <http://www.gnu.org/licenses/>. */
  16. #include "config.h"
  17. #include "sim-main.h"
  18. #include "devices.h"
  19. #include "dv-bfin_eppi.h"
  20. #include "gui.h"
  21. /* XXX: TX is merely a stub. */
  22. struct bfin_eppi
  23. {
  24. /* This top portion matches common dv_bfin struct. */
  25. bu32 base;
  26. struct hw *dma_master;
  27. bool acked;
  28. struct hw_event *handler;
  29. char saved_byte;
  30. int saved_count;
  31. /* GUI state. */
  32. void *gui_state;
  33. int color;
  34. /* Order after here is important -- matches hardware MMR layout. */
  35. bu16 BFIN_MMR_16(status);
  36. bu16 BFIN_MMR_16(hcount);
  37. bu16 BFIN_MMR_16(hdelay);
  38. bu16 BFIN_MMR_16(vcount);
  39. bu16 BFIN_MMR_16(vdelay);
  40. bu16 BFIN_MMR_16(frame);
  41. bu16 BFIN_MMR_16(line);
  42. bu16 BFIN_MMR_16(clkdiv);
  43. bu32 control, fs1w_hbl, fs1p_avpl, fsw2_lvb, fs2p_lavf, clip, err;
  44. };
  45. #define mmr_base() offsetof(struct bfin_eppi, status)
  46. #define mmr_offset(mmr) (offsetof(struct bfin_eppi, mmr) - mmr_base())
  47. static const char * const mmr_names[] =
  48. {
  49. "EPPI_STATUS", "EPPI_HCOUNT", "EPPI_HDELAY", "EPPI_VCOUNT", "EPPI_VDELAY",
  50. "EPPI_FRAME", "EPPI_LINE", "EPPI_CLKDIV", "EPPI_CONTROL", "EPPI_FS1W_HBL",
  51. "EPPI_FS1P_AVPL", "EPPI_FS2W_LVB", "EPPI_FS2P_LAVF", "EPPI_CLIP", "EPPI_ERR",
  52. };
  53. #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
  54. static void
  55. bfin_eppi_gui_setup (struct bfin_eppi *eppi)
  56. {
  57. /* If we are in RX mode, nothing to do. */
  58. if (!(eppi->control & PORT_DIR))
  59. return;
  60. eppi->gui_state = bfin_gui_setup (eppi->gui_state,
  61. eppi->control & PORT_EN,
  62. eppi->hcount,
  63. eppi->vcount,
  64. eppi->color);
  65. }
  66. static unsigned
  67. bfin_eppi_io_write_buffer (struct hw *me, const void *source,
  68. int space, address_word addr, unsigned nr_bytes)
  69. {
  70. struct bfin_eppi *eppi = hw_data (me);
  71. bu32 mmr_off;
  72. bu32 value;
  73. bu16 *value16p;
  74. bu32 *value32p;
  75. void *valuep;
  76. if (nr_bytes == 4)
  77. value = dv_load_4 (source);
  78. else
  79. value = dv_load_2 (source);
  80. mmr_off = addr - eppi->base;
  81. valuep = (void *)((unsigned long)eppi + mmr_base() + mmr_off);
  82. value16p = valuep;
  83. value32p = valuep;
  84. HW_TRACE_WRITE ();
  85. switch (mmr_off)
  86. {
  87. case mmr_offset(status):
  88. dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  89. dv_w1c_2 (value16p, value, 0x1ff);
  90. break;
  91. case mmr_offset(hcount):
  92. case mmr_offset(hdelay):
  93. case mmr_offset(vcount):
  94. case mmr_offset(vdelay):
  95. case mmr_offset(frame):
  96. case mmr_offset(line):
  97. case mmr_offset(clkdiv):
  98. dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  99. *value16p = value;
  100. break;
  101. case mmr_offset(control):
  102. *value32p = value;
  103. bfin_eppi_gui_setup (eppi);
  104. break;
  105. case mmr_offset(fs1w_hbl):
  106. case mmr_offset(fs1p_avpl):
  107. case mmr_offset(fsw2_lvb):
  108. case mmr_offset(fs2p_lavf):
  109. case mmr_offset(clip):
  110. case mmr_offset(err):
  111. dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
  112. *value32p = value;
  113. break;
  114. default:
  115. dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
  116. break;
  117. }
  118. return nr_bytes;
  119. }
  120. static unsigned
  121. bfin_eppi_io_read_buffer (struct hw *me, void *dest,
  122. int space, address_word addr, unsigned nr_bytes)
  123. {
  124. struct bfin_eppi *eppi = hw_data (me);
  125. bu32 mmr_off;
  126. bu16 *value16p;
  127. bu32 *value32p;
  128. void *valuep;
  129. mmr_off = addr - eppi->base;
  130. valuep = (void *)((unsigned long)eppi + mmr_base() + mmr_off);
  131. value16p = valuep;
  132. value32p = valuep;
  133. HW_TRACE_READ ();
  134. switch (mmr_off)
  135. {
  136. case mmr_offset(status):
  137. case mmr_offset(hcount):
  138. case mmr_offset(hdelay):
  139. case mmr_offset(vcount):
  140. case mmr_offset(vdelay):
  141. case mmr_offset(frame):
  142. case mmr_offset(line):
  143. case mmr_offset(clkdiv):
  144. dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
  145. dv_store_2 (dest, *value16p);
  146. break;
  147. case mmr_offset(control):
  148. case mmr_offset(fs1w_hbl):
  149. case mmr_offset(fs1p_avpl):
  150. case mmr_offset(fsw2_lvb):
  151. case mmr_offset(fs2p_lavf):
  152. case mmr_offset(clip):
  153. case mmr_offset(err):
  154. dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
  155. dv_store_4 (dest, *value32p);
  156. break;
  157. default:
  158. dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
  159. break;
  160. }
  161. return nr_bytes;
  162. }
  163. static unsigned
  164. bfin_eppi_dma_read_buffer (struct hw *me, void *dest, int space,
  165. unsigned_word addr, unsigned nr_bytes)
  166. {
  167. HW_TRACE_DMA_READ ();
  168. return 0;
  169. }
  170. static unsigned
  171. bfin_eppi_dma_write_buffer (struct hw *me, const void *source,
  172. int space, unsigned_word addr,
  173. unsigned nr_bytes,
  174. int violate_read_only_section)
  175. {
  176. struct bfin_eppi *eppi = hw_data (me);
  177. HW_TRACE_DMA_WRITE ();
  178. return bfin_gui_update (eppi->gui_state, source, nr_bytes);
  179. }
  180. static const struct hw_port_descriptor bfin_eppi_ports[] =
  181. {
  182. { "stat", 0, 0, output_port, },
  183. { NULL, 0, 0, 0, },
  184. };
  185. static void
  186. attach_bfin_eppi_regs (struct hw *me, struct bfin_eppi *eppi)
  187. {
  188. address_word attach_address;
  189. int attach_space;
  190. unsigned attach_size;
  191. reg_property_spec reg;
  192. if (hw_find_property (me, "reg") == NULL)
  193. hw_abort (me, "Missing \"reg\" property");
  194. if (!hw_find_reg_array_property (me, "reg", 0, &reg))
  195. hw_abort (me, "\"reg\" property must contain three addr/size entries");
  196. hw_unit_address_to_attach_address (hw_parent (me),
  197. &reg.address,
  198. &attach_space, &attach_address, me);
  199. hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
  200. if (attach_size != BFIN_MMR_EPPI_SIZE)
  201. hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EPPI_SIZE);
  202. hw_attach_address (hw_parent (me),
  203. 0, attach_space, attach_address, attach_size, me);
  204. eppi->base = attach_address;
  205. }
  206. static void
  207. bfin_eppi_finish (struct hw *me)
  208. {
  209. struct bfin_eppi *eppi;
  210. const char *color;
  211. eppi = HW_ZALLOC (me, struct bfin_eppi);
  212. set_hw_data (me, eppi);
  213. set_hw_io_read_buffer (me, bfin_eppi_io_read_buffer);
  214. set_hw_io_write_buffer (me, bfin_eppi_io_write_buffer);
  215. set_hw_dma_read_buffer (me, bfin_eppi_dma_read_buffer);
  216. set_hw_dma_write_buffer (me, bfin_eppi_dma_write_buffer);
  217. set_hw_ports (me, bfin_eppi_ports);
  218. attach_bfin_eppi_regs (me, eppi);
  219. /* Initialize the EPPI. */
  220. if (hw_find_property (me, "color"))
  221. color = hw_find_string_property (me, "color");
  222. else
  223. color = NULL;
  224. eppi->color = bfin_gui_color (color);
  225. }
  226. const struct hw_descriptor dv_bfin_eppi_descriptor[] =
  227. {
  228. {"bfin_eppi", bfin_eppi_finish,},
  229. {NULL, NULL},
  230. };