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or1k-desc.c

or1k-desc.c 150 KB
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
  1. /* CPU data for or1k.
    2. 

  2. 

  3. THIS FILE IS MACHINE GENERATED WITH CGEN.
    4. 

  4. 

  5. Copyright (C) 1996-2015 Free Software Foundation, Inc.
    6. 

  6. 

  7. This file is part of the GNU Binutils and/or GDB, the GNU debugger.
    8. 

  8. 

  9.    This file is free software; you can redistribute it and/or modify
    10. 

  10.    it under the terms of the GNU General Public License as published by
    11. 

  11.    the Free Software Foundation; either version 3, or (at your option)
    12. 

  12.    any later version.
    13. 

  13. 

  14.    It is distributed in the hope that it will be useful, but WITHOUT
    15. 

  15.    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
    16. 

  16.    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
    17. 

  17.    License for more details.
    18. 

  18. 

  19.    You should have received a copy of the GNU General Public License along
    20. 

  20.    with this program; if not, write to the Free Software Foundation, Inc.,
    21. 

  21.    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
    22. 

  22. 

  23. */
    24. 

  24. 

  25. #include "sysdep.h"
    26. 

  26. #include <stdio.h>
    27. 

  27. #include <stdarg.h>
    28. 

  28. #include "ansidecl.h"
    29. 

  29. #include "bfd.h"
    30. 

  30. #include "symcat.h"
    31. 

  31. #include "or1k-desc.h"
    32. 

  32. #include "or1k-opc.h"
    33. 

  33. #include "opintl.h"
    34. 

  34. #include "libiberty.h"
    35. 

  35. #include "xregex.h"
    36. 

  36. 

  37. /* Attributes.  */
    38. 

  38. 

  39. static const CGEN_ATTR_ENTRY bool_attr[] =
    40. 

  40. {
    41. 

  41.   { "#f", 0 },
    42. 

  42.   { "#t", 1 },
    43. 

  43.   { 0, 0 }
    44. 

  44. };
    45. 

  45. 

  46. static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
    47. 

  47. {
    48. 

  48.   { "base", MACH_BASE },
    49. 

  49.   { "or32", MACH_OR32 },
    50. 

  50.   { "or32nd", MACH_OR32ND },
    51. 

  51.   { "or64", MACH_OR64 },
    52. 

  52.   { "or64nd", MACH_OR64ND },
    53. 

  53.   { "max", MACH_MAX },
    54. 

  54.   { 0, 0 }
    55. 

  55. };
    56. 

  56. 

  57. static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
    58. 

  58. {
    59. 

  59.   { "openrisc", ISA_OPENRISC },
    60. 

  60.   { "max", ISA_MAX },
    61. 

  61.   { 0, 0 }
    62. 

  62. };
    63. 

  63. 

  64. const CGEN_ATTR_TABLE or1k_cgen_ifield_attr_table[] =
    65. 

  65. {
    66. 

  66.   { "MACH", & MACH_attr[0], & MACH_attr[0] },
    67. 

  67.   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
    68. 

  68.   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
    69. 

  69.   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
    70. 

  70.   { "RESERVED", &bool_attr[0], &bool_attr[0] },
    71. 

  71.   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
    72. 

  72.   { "SIGNED", &bool_attr[0], &bool_attr[0] },
    73. 

  73.   { 0, 0, 0 }
    74. 

  74. };
    75. 

  75. 

  76. const CGEN_ATTR_TABLE or1k_cgen_hardware_attr_table[] =
    77. 

  77. {
    78. 

  78.   { "MACH", & MACH_attr[0], & MACH_attr[0] },
    79. 

  79.   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
    80. 

  80.   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
    81. 

  81.   { "PC", &bool_attr[0], &bool_attr[0] },
    82. 

  82.   { "PROFILE", &bool_attr[0], &bool_attr[0] },
    83. 

  83.   { 0, 0, 0 }
    84. 

  84. };
    85. 

  85. 

  86. const CGEN_ATTR_TABLE or1k_cgen_operand_attr_table[] =
    87. 

  87. {
    88. 

  88.   { "MACH", & MACH_attr[0], & MACH_attr[0] },
    89. 

  89.   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
    90. 

  90.   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
    91. 

  91.   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
    92. 

  92.   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
    93. 

  93.   { "SIGNED", &bool_attr[0], &bool_attr[0] },
    94. 

  94.   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
    95. 

  95.   { "RELAX", &bool_attr[0], &bool_attr[0] },
    96. 

  96.   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
    97. 

  97.   { 0, 0, 0 }
    98. 

  98. };
    99. 

  99. 

  100. const CGEN_ATTR_TABLE or1k_cgen_insn_attr_table[] =
    101. 

  101. {
    102. 

  102.   { "MACH", & MACH_attr[0], & MACH_attr[0] },
    103. 

  103.   { "ALIAS", &bool_attr[0], &bool_attr[0] },
    104. 

  104.   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
    105. 

  105.   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
    106. 

  106.   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
    107. 

  107.   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
    108. 

  108.   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
    109. 

  109.   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
    110. 

  110.   { "RELAXED", &bool_attr[0], &bool_attr[0] },
    111. 

  111.   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
    112. 

  112.   { "PBB", &bool_attr[0], &bool_attr[0] },
    113. 

  113.   { "DELAYED-CTI", &bool_attr[0], &bool_attr[0] },
    114. 

  114.   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
    115. 

  115.   { "FORCED-CTI", &bool_attr[0], &bool_attr[0] },
    116. 

  116.   { 0, 0, 0 }
    117. 

  117. };
    118. 

  118. 

  119. /* Instruction set variants.  */
    120. 

  120. 

  121. static const CGEN_ISA or1k_cgen_isa_table[] = {
    122. 

  122.   { "openrisc", 32, 32, 32, 32 },
    123. 

  123.   { 0, 0, 0, 0, 0 }
    124. 

  124. };
    125. 

  125. 

  126. /* Machine variants.  */
    127. 

  127. 

  128. static const CGEN_MACH or1k_cgen_mach_table[] = {
    129. 

  129.   { "or32", "or1k", MACH_OR32, 0 },
    130. 

  130.   { "or32nd", "or1knd", MACH_OR32ND, 0 },
    131. 

  131.   { "or64", "or1k64", MACH_OR64, 0 },
    132. 

  132.   { "or64nd", "or1k64nd", MACH_OR64ND, 0 },
    133. 

  133.   { 0, 0, 0, 0 }
    134. 

  134. };
    135. 

  135. 

  136. static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
    137. 

  137. {
    138. 

  138.   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
    139. 

  139.   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
    140. 

  140.   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
    141. 

  141.   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
    142. 

  142.   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
    143. 

  143.   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
    144. 

  144.   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
    145. 

  145.   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
    146. 

  146.   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
    147. 

  147.   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
    148. 

  148.   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
    149. 

  149.   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
    150. 

  150.   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
    151. 

  151.   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
    152. 

  152.   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
    153. 

  153.   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
    154. 

  154.   { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
    155. 

  155.   { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
    156. 

  156.   { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
    157. 

  157.   { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
    158. 

  158.   { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
    159. 

  159.   { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
    160. 

  160.   { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
    161. 

  161.   { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
    162. 

  162.   { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
    163. 

  163.   { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
    164. 

  164.   { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
    165. 

  165.   { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
    166. 

  166.   { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
    167. 

  167.   { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
    168. 

  168.   { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
    169. 

  169.   { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
    170. 

  170.   { "lr", 9, {0, {{{0, 0}}}}, 0, 0 },
    171. 

  171.   { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
    172. 

  172.   { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
    173. 

  173. };
    174. 

  174. 

  175. CGEN_KEYWORD or1k_cgen_opval_h_fsr =
    176. 

  176. {
    177. 

  177.   & or1k_cgen_opval_h_fsr_entries[0],
    178. 

  178.   35,
    179. 

  179.   0, 0, 0, 0, ""
    180. 

  180. };
    181. 

  181. 

  182. static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] =
    183. 

  183. {
    184. 

  184.   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
    185. 

  185.   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
    186. 

  186.   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
    187. 

  187.   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
    188. 

  188.   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
    189. 

  189.   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
    190. 

  190.   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
    191. 

  191.   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
    192. 

  192.   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
    193. 

  193.   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
    194. 

  194.   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
    195. 

  195.   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
    196. 

  196.   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
    197. 

  197.   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
    198. 

  198.   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
    199. 

  199.   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
    200. 

  200.   { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
    201. 

  201.   { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
    202. 

  202.   { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
    203. 

  203.   { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
    204. 

  204.   { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
    205. 

  205.   { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
    206. 

  206.   { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
    207. 

  207.   { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
    208. 

  208.   { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
    209. 

  209.   { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
    210. 

  210.   { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
    211. 

  211.   { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
    212. 

  212.   { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
    213. 

  213.   { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
    214. 

  214.   { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
    215. 

  215.   { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
    216. 

  216.   { "lr", 9, {0, {{{0, 0}}}}, 0, 0 },
    217. 

  217.   { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
    218. 

  218.   { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
    219. 

  219. };
    220. 

  220. 

  221. CGEN_KEYWORD or1k_cgen_opval_h_fdr =
    222. 

  222. {
    223. 

  223.   & or1k_cgen_opval_h_fdr_entries[0],
    224. 

  224.   35,
    225. 

  225.   0, 0, 0, 0, ""
    226. 

  226. };
    227. 

  227. 

  228. static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
    229. 

  229. {
    230. 

  230.   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
    231. 

  231.   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
    232. 

  232.   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
    233. 

  233.   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
    234. 

  234.   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
    235. 

  235.   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
    236. 

  236.   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
    237. 

  237.   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
    238. 

  238.   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
    239. 

  239.   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
    240. 

  240.   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
    241. 

  241.   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
    242. 

  242.   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
    243. 

  243.   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
    244. 

  244.   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
    245. 

  245.   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
    246. 

  246.   { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
    247. 

  247.   { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
    248. 

  248.   { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
    249. 

  249.   { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
    250. 

  250.   { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
    251. 

  251.   { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
    252. 

  252.   { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
    253. 

  253.   { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
    254. 

  254.   { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
    255. 

  255.   { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
    256. 

  256.   { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
    257. 

  257.   { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
    258. 

  258.   { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
    259. 

  259.   { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
    260. 

  260.   { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
    261. 

  261.   { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
    262. 

  262.   { "lr", 9, {0, {{{0, 0}}}}, 0, 0 },
    263. 

  263.   { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
    264. 

  264.   { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
    265. 

  265. };
    266. 

  266. 

  267. CGEN_KEYWORD or1k_cgen_opval_h_gpr =
    268. 

  268. {
    269. 

  269.   & or1k_cgen_opval_h_gpr_entries[0],
    270. 

  270.   35,
    271. 

  271.   0, 0, 0, 0, ""
    272. 

  272. };
    273. 

  273. 

  274. 

  275. /* The hardware table.  */
    276. 

  276. 

  277. #define A(a) (1 << CGEN_HW_##a)
    278. 

  278. 

  279. const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
    280. 

  280. {
    281. 

  281.   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    282. 

  282.   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    283. 

  283.   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    284. 

  284.   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    285. 

  285.   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    286. 

  286.   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    287. 

  287.   { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    288. 

  288.   { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    289. 

  289.   { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    290. 

  290.   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    291. 

  291.   { "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    292. 

  292.   { "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    293. 

  293.   { "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    294. 

  294.   { "h-sys-dmmucfgr", HW_H_SYS_DMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    295. 

  295.   { "h-sys-immucfgr", HW_H_SYS_IMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    296. 

  296.   { "h-sys-dccfgr", HW_H_SYS_DCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    297. 

  297.   { "h-sys-iccfgr", HW_H_SYS_ICCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    298. 

  298.   { "h-sys-dcfgr", HW_H_SYS_DCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    299. 

  299.   { "h-sys-pccfgr", HW_H_SYS_PCCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    300. 

  300.   { "h-sys-npc", HW_H_SYS_NPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    301. 

  301.   { "h-sys-sr", HW_H_SYS_SR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    302. 

  302.   { "h-sys-ppc", HW_H_SYS_PPC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    303. 

  303.   { "h-sys-fpcsr", HW_H_SYS_FPCSR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    304. 

  304.   { "h-sys-epcr0", HW_H_SYS_EPCR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    305. 

  305.   { "h-sys-epcr1", HW_H_SYS_EPCR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    306. 

  306.   { "h-sys-epcr2", HW_H_SYS_EPCR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    307. 

  307.   { "h-sys-epcr3", HW_H_SYS_EPCR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    308. 

  308.   { "h-sys-epcr4", HW_H_SYS_EPCR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    309. 

  309.   { "h-sys-epcr5", HW_H_SYS_EPCR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    310. 

  310.   { "h-sys-epcr6", HW_H_SYS_EPCR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    311. 

  311.   { "h-sys-epcr7", HW_H_SYS_EPCR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    312. 

  312.   { "h-sys-epcr8", HW_H_SYS_EPCR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    313. 

  313.   { "h-sys-epcr9", HW_H_SYS_EPCR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    314. 

  314.   { "h-sys-epcr10", HW_H_SYS_EPCR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    315. 

  315.   { "h-sys-epcr11", HW_H_SYS_EPCR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    316. 

  316.   { "h-sys-epcr12", HW_H_SYS_EPCR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    317. 

  317.   { "h-sys-epcr13", HW_H_SYS_EPCR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    318. 

  318.   { "h-sys-epcr14", HW_H_SYS_EPCR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    319. 

  319.   { "h-sys-epcr15", HW_H_SYS_EPCR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    320. 

  320.   { "h-sys-eear0", HW_H_SYS_EEAR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    321. 

  321.   { "h-sys-eear1", HW_H_SYS_EEAR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    322. 

  322.   { "h-sys-eear2", HW_H_SYS_EEAR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    323. 

  323.   { "h-sys-eear3", HW_H_SYS_EEAR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    324. 

  324.   { "h-sys-eear4", HW_H_SYS_EEAR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    325. 

  325.   { "h-sys-eear5", HW_H_SYS_EEAR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    326. 

  326.   { "h-sys-eear6", HW_H_SYS_EEAR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    327. 

  327.   { "h-sys-eear7", HW_H_SYS_EEAR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    328. 

  328.   { "h-sys-eear8", HW_H_SYS_EEAR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    329. 

  329.   { "h-sys-eear9", HW_H_SYS_EEAR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    330. 

  330.   { "h-sys-eear10", HW_H_SYS_EEAR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    331. 

  331.   { "h-sys-eear11", HW_H_SYS_EEAR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    332. 

  332.   { "h-sys-eear12", HW_H_SYS_EEAR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    333. 

  333.   { "h-sys-eear13", HW_H_SYS_EEAR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    334. 

  334.   { "h-sys-eear14", HW_H_SYS_EEAR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    335. 

  335.   { "h-sys-eear15", HW_H_SYS_EEAR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    336. 

  336.   { "h-sys-esr0", HW_H_SYS_ESR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    337. 

  337.   { "h-sys-esr1", HW_H_SYS_ESR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    338. 

  338.   { "h-sys-esr2", HW_H_SYS_ESR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    339. 

  339.   { "h-sys-esr3", HW_H_SYS_ESR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    340. 

  340.   { "h-sys-esr4", HW_H_SYS_ESR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    341. 

  341.   { "h-sys-esr5", HW_H_SYS_ESR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    342. 

  342.   { "h-sys-esr6", HW_H_SYS_ESR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    343. 

  343.   { "h-sys-esr7", HW_H_SYS_ESR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    344. 

  344.   { "h-sys-esr8", HW_H_SYS_ESR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    345. 

  345.   { "h-sys-esr9", HW_H_SYS_ESR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    346. 

  346.   { "h-sys-esr10", HW_H_SYS_ESR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    347. 

  347.   { "h-sys-esr11", HW_H_SYS_ESR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    348. 

  348.   { "h-sys-esr12", HW_H_SYS_ESR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    349. 

  349.   { "h-sys-esr13", HW_H_SYS_ESR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    350. 

  350.   { "h-sys-esr14", HW_H_SYS_ESR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    351. 

  351.   { "h-sys-esr15", HW_H_SYS_ESR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    352. 

  352.   { "h-sys-gpr0", HW_H_SYS_GPR0, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    353. 

  353.   { "h-sys-gpr1", HW_H_SYS_GPR1, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    354. 

  354.   { "h-sys-gpr2", HW_H_SYS_GPR2, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    355. 

  355.   { "h-sys-gpr3", HW_H_SYS_GPR3, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    356. 

  356.   { "h-sys-gpr4", HW_H_SYS_GPR4, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    357. 

  357.   { "h-sys-gpr5", HW_H_SYS_GPR5, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    358. 

  358.   { "h-sys-gpr6", HW_H_SYS_GPR6, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    359. 

  359.   { "h-sys-gpr7", HW_H_SYS_GPR7, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    360. 

  360.   { "h-sys-gpr8", HW_H_SYS_GPR8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    361. 

  361.   { "h-sys-gpr9", HW_H_SYS_GPR9, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    362. 

  362.   { "h-sys-gpr10", HW_H_SYS_GPR10, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    363. 

  363.   { "h-sys-gpr11", HW_H_SYS_GPR11, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    364. 

  364.   { "h-sys-gpr12", HW_H_SYS_GPR12, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    365. 

  365.   { "h-sys-gpr13", HW_H_SYS_GPR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    366. 

  366.   { "h-sys-gpr14", HW_H_SYS_GPR14, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    367. 

  367.   { "h-sys-gpr15", HW_H_SYS_GPR15, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    368. 

  368.   { "h-sys-gpr16", HW_H_SYS_GPR16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    369. 

  369.   { "h-sys-gpr17", HW_H_SYS_GPR17, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    370. 

  370.   { "h-sys-gpr18", HW_H_SYS_GPR18, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    371. 

  371.   { "h-sys-gpr19", HW_H_SYS_GPR19, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    372. 

  372.   { "h-sys-gpr20", HW_H_SYS_GPR20, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    373. 

  373.   { "h-sys-gpr21", HW_H_SYS_GPR21, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    374. 

  374.   { "h-sys-gpr22", HW_H_SYS_GPR22, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    375. 

  375.   { "h-sys-gpr23", HW_H_SYS_GPR23, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    376. 

  376.   { "h-sys-gpr24", HW_H_SYS_GPR24, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    377. 

  377.   { "h-sys-gpr25", HW_H_SYS_GPR25, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    378. 

  378.   { "h-sys-gpr26", HW_H_SYS_GPR26, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    379. 

  379.   { "h-sys-gpr27", HW_H_SYS_GPR27, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    380. 

  380.   { "h-sys-gpr28", HW_H_SYS_GPR28, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    381. 

  381.   { "h-sys-gpr29", HW_H_SYS_GPR29, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    382. 

  382.   { "h-sys-gpr30", HW_H_SYS_GPR30, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    383. 

  383.   { "h-sys-gpr31", HW_H_SYS_GPR31, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    384. 

  384.   { "h-sys-gpr32", HW_H_SYS_GPR32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    385. 

  385.   { "h-sys-gpr33", HW_H_SYS_GPR33, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    386. 

  386.   { "h-sys-gpr34", HW_H_SYS_GPR34, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    387. 

  387.   { "h-sys-gpr35", HW_H_SYS_GPR35, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    388. 

  388.   { "h-sys-gpr36", HW_H_SYS_GPR36, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    389. 

  389.   { "h-sys-gpr37", HW_H_SYS_GPR37, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    390. 

  390.   { "h-sys-gpr38", HW_H_SYS_GPR38, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    391. 

  391.   { "h-sys-gpr39", HW_H_SYS_GPR39, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    392. 

  392.   { "h-sys-gpr40", HW_H_SYS_GPR40, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    393. 

  393.   { "h-sys-gpr41", HW_H_SYS_GPR41, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    394. 

  394.   { "h-sys-gpr42", HW_H_SYS_GPR42, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    395. 

  395.   { "h-sys-gpr43", HW_H_SYS_GPR43, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    396. 

  396.   { "h-sys-gpr44", HW_H_SYS_GPR44, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    397. 

  397.   { "h-sys-gpr45", HW_H_SYS_GPR45, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    398. 

  398.   { "h-sys-gpr46", HW_H_SYS_GPR46, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    399. 

  399.   { "h-sys-gpr47", HW_H_SYS_GPR47, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    400. 

  400.   { "h-sys-gpr48", HW_H_SYS_GPR48, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    401. 

  401.   { "h-sys-gpr49", HW_H_SYS_GPR49, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    402. 

  402.   { "h-sys-gpr50", HW_H_SYS_GPR50, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    403. 

  403.   { "h-sys-gpr51", HW_H_SYS_GPR51, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    404. 

  404.   { "h-sys-gpr52", HW_H_SYS_GPR52, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    405. 

  405.   { "h-sys-gpr53", HW_H_SYS_GPR53, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    406. 

  406.   { "h-sys-gpr54", HW_H_SYS_GPR54, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    407. 

  407.   { "h-sys-gpr55", HW_H_SYS_GPR55, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    408. 

  408.   { "h-sys-gpr56", HW_H_SYS_GPR56, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    409. 

  409.   { "h-sys-gpr57", HW_H_SYS_GPR57, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    410. 

  410.   { "h-sys-gpr58", HW_H_SYS_GPR58, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    411. 

  411.   { "h-sys-gpr59", HW_H_SYS_GPR59, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    412. 

  412.   { "h-sys-gpr60", HW_H_SYS_GPR60, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    413. 

  413.   { "h-sys-gpr61", HW_H_SYS_GPR61, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    414. 

  414.   { "h-sys-gpr62", HW_H_SYS_GPR62, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    415. 

  415.   { "h-sys-gpr63", HW_H_SYS_GPR63, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    416. 

  416.   { "h-sys-gpr64", HW_H_SYS_GPR64, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    417. 

  417.   { "h-sys-gpr65", HW_H_SYS_GPR65, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    418. 

  418.   { "h-sys-gpr66", HW_H_SYS_GPR66, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    419. 

  419.   { "h-sys-gpr67", HW_H_SYS_GPR67, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    420. 

  420.   { "h-sys-gpr68", HW_H_SYS_GPR68, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    421. 

  421.   { "h-sys-gpr69", HW_H_SYS_GPR69, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    422. 

  422.   { "h-sys-gpr70", HW_H_SYS_GPR70, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    423. 

  423.   { "h-sys-gpr71", HW_H_SYS_GPR71, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    424. 

  424.   { "h-sys-gpr72", HW_H_SYS_GPR72, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    425. 

  425.   { "h-sys-gpr73", HW_H_SYS_GPR73, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    426. 

  426.   { "h-sys-gpr74", HW_H_SYS_GPR74, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    427. 

  427.   { "h-sys-gpr75", HW_H_SYS_GPR75, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    428. 

  428.   { "h-sys-gpr76", HW_H_SYS_GPR76, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    429. 

  429.   { "h-sys-gpr77", HW_H_SYS_GPR77, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    430. 

  430.   { "h-sys-gpr78", HW_H_SYS_GPR78, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    431. 

  431.   { "h-sys-gpr79", HW_H_SYS_GPR79, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    432. 

  432.   { "h-sys-gpr80", HW_H_SYS_GPR80, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    433. 

  433.   { "h-sys-gpr81", HW_H_SYS_GPR81, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    434. 

  434.   { "h-sys-gpr82", HW_H_SYS_GPR82, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    435. 

  435.   { "h-sys-gpr83", HW_H_SYS_GPR83, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    436. 

  436.   { "h-sys-gpr84", HW_H_SYS_GPR84, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    437. 

  437.   { "h-sys-gpr85", HW_H_SYS_GPR85, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    438. 

  438.   { "h-sys-gpr86", HW_H_SYS_GPR86, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    439. 

  439.   { "h-sys-gpr87", HW_H_SYS_GPR87, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    440. 

  440.   { "h-sys-gpr88", HW_H_SYS_GPR88, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    441. 

  441.   { "h-sys-gpr89", HW_H_SYS_GPR89, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    442. 

  442.   { "h-sys-gpr90", HW_H_SYS_GPR90, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    443. 

  443.   { "h-sys-gpr91", HW_H_SYS_GPR91, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    444. 

  444.   { "h-sys-gpr92", HW_H_SYS_GPR92, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    445. 

  445.   { "h-sys-gpr93", HW_H_SYS_GPR93, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    446. 

  446.   { "h-sys-gpr94", HW_H_SYS_GPR94, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    447. 

  447.   { "h-sys-gpr95", HW_H_SYS_GPR95, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    448. 

  448.   { "h-sys-gpr96", HW_H_SYS_GPR96, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    449. 

  449.   { "h-sys-gpr97", HW_H_SYS_GPR97, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    450. 

  450.   { "h-sys-gpr98", HW_H_SYS_GPR98, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    451. 

  451.   { "h-sys-gpr99", HW_H_SYS_GPR99, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    452. 

  452.   { "h-sys-gpr100", HW_H_SYS_GPR100, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    453. 

  453.   { "h-sys-gpr101", HW_H_SYS_GPR101, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    454. 

  454.   { "h-sys-gpr102", HW_H_SYS_GPR102, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    455. 

  455.   { "h-sys-gpr103", HW_H_SYS_GPR103, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    456. 

  456.   { "h-sys-gpr104", HW_H_SYS_GPR104, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    457. 

  457.   { "h-sys-gpr105", HW_H_SYS_GPR105, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    458. 

  458.   { "h-sys-gpr106", HW_H_SYS_GPR106, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    459. 

  459.   { "h-sys-gpr107", HW_H_SYS_GPR107, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    460. 

  460.   { "h-sys-gpr108", HW_H_SYS_GPR108, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    461. 

  461.   { "h-sys-gpr109", HW_H_SYS_GPR109, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    462. 

  462.   { "h-sys-gpr110", HW_H_SYS_GPR110, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    463. 

  463.   { "h-sys-gpr111", HW_H_SYS_GPR111, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    464. 

  464.   { "h-sys-gpr112", HW_H_SYS_GPR112, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    465. 

  465.   { "h-sys-gpr113", HW_H_SYS_GPR113, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    466. 

  466.   { "h-sys-gpr114", HW_H_SYS_GPR114, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    467. 

  467.   { "h-sys-gpr115", HW_H_SYS_GPR115, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    468. 

  468.   { "h-sys-gpr116", HW_H_SYS_GPR116, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    469. 

  469.   { "h-sys-gpr117", HW_H_SYS_GPR117, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    470. 

  470.   { "h-sys-gpr118", HW_H_SYS_GPR118, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    471. 

  471.   { "h-sys-gpr119", HW_H_SYS_GPR119, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    472. 

  472.   { "h-sys-gpr120", HW_H_SYS_GPR120, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    473. 

  473.   { "h-sys-gpr121", HW_H_SYS_GPR121, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    474. 

  474.   { "h-sys-gpr122", HW_H_SYS_GPR122, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    475. 

  475.   { "h-sys-gpr123", HW_H_SYS_GPR123, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    476. 

  476.   { "h-sys-gpr124", HW_H_SYS_GPR124, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    477. 

  477.   { "h-sys-gpr125", HW_H_SYS_GPR125, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    478. 

  478.   { "h-sys-gpr126", HW_H_SYS_GPR126, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    479. 

  479.   { "h-sys-gpr127", HW_H_SYS_GPR127, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    480. 

  480.   { "h-sys-gpr128", HW_H_SYS_GPR128, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    481. 

  481.   { "h-sys-gpr129", HW_H_SYS_GPR129, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    482. 

  482.   { "h-sys-gpr130", HW_H_SYS_GPR130, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    483. 

  483.   { "h-sys-gpr131", HW_H_SYS_GPR131, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    484. 

  484.   { "h-sys-gpr132", HW_H_SYS_GPR132, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    485. 

  485.   { "h-sys-gpr133", HW_H_SYS_GPR133, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    486. 

  486.   { "h-sys-gpr134", HW_H_SYS_GPR134, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    487. 

  487.   { "h-sys-gpr135", HW_H_SYS_GPR135, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    488. 

  488.   { "h-sys-gpr136", HW_H_SYS_GPR136, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    489. 

  489.   { "h-sys-gpr137", HW_H_SYS_GPR137, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    490. 

  490.   { "h-sys-gpr138", HW_H_SYS_GPR138, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    491. 

  491.   { "h-sys-gpr139", HW_H_SYS_GPR139, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    492. 

  492.   { "h-sys-gpr140", HW_H_SYS_GPR140, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    493. 

  493.   { "h-sys-gpr141", HW_H_SYS_GPR141, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    494. 

  494.   { "h-sys-gpr142", HW_H_SYS_GPR142, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    495. 

  495.   { "h-sys-gpr143", HW_H_SYS_GPR143, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    496. 

  496.   { "h-sys-gpr144", HW_H_SYS_GPR144, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    497. 

  497.   { "h-sys-gpr145", HW_H_SYS_GPR145, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    498. 

  498.   { "h-sys-gpr146", HW_H_SYS_GPR146, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    499. 

  499.   { "h-sys-gpr147", HW_H_SYS_GPR147, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    500. 

  500.   { "h-sys-gpr148", HW_H_SYS_GPR148, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    501. 

  501.   { "h-sys-gpr149", HW_H_SYS_GPR149, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    502. 

  502.   { "h-sys-gpr150", HW_H_SYS_GPR150, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    503. 

  503.   { "h-sys-gpr151", HW_H_SYS_GPR151, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    504. 

  504.   { "h-sys-gpr152", HW_H_SYS_GPR152, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    505. 

  505.   { "h-sys-gpr153", HW_H_SYS_GPR153, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    506. 

  506.   { "h-sys-gpr154", HW_H_SYS_GPR154, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    507. 

  507.   { "h-sys-gpr155", HW_H_SYS_GPR155, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    508. 

  508.   { "h-sys-gpr156", HW_H_SYS_GPR156, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    509. 

  509.   { "h-sys-gpr157", HW_H_SYS_GPR157, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    510. 

  510.   { "h-sys-gpr158", HW_H_SYS_GPR158, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    511. 

  511.   { "h-sys-gpr159", HW_H_SYS_GPR159, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    512. 

  512.   { "h-sys-gpr160", HW_H_SYS_GPR160, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    513. 

  513.   { "h-sys-gpr161", HW_H_SYS_GPR161, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    514. 

  514.   { "h-sys-gpr162", HW_H_SYS_GPR162, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    515. 

  515.   { "h-sys-gpr163", HW_H_SYS_GPR163, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    516. 

  516.   { "h-sys-gpr164", HW_H_SYS_GPR164, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    517. 

  517.   { "h-sys-gpr165", HW_H_SYS_GPR165, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    518. 

  518.   { "h-sys-gpr166", HW_H_SYS_GPR166, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    519. 

  519.   { "h-sys-gpr167", HW_H_SYS_GPR167, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    520. 

  520.   { "h-sys-gpr168", HW_H_SYS_GPR168, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    521. 

  521.   { "h-sys-gpr169", HW_H_SYS_GPR169, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    522. 

  522.   { "h-sys-gpr170", HW_H_SYS_GPR170, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    523. 

  523.   { "h-sys-gpr171", HW_H_SYS_GPR171, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    524. 

  524.   { "h-sys-gpr172", HW_H_SYS_GPR172, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    525. 

  525.   { "h-sys-gpr173", HW_H_SYS_GPR173, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    526. 

  526.   { "h-sys-gpr174", HW_H_SYS_GPR174, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    527. 

  527.   { "h-sys-gpr175", HW_H_SYS_GPR175, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    528. 

  528.   { "h-sys-gpr176", HW_H_SYS_GPR176, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    529. 

  529.   { "h-sys-gpr177", HW_H_SYS_GPR177, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    530. 

  530.   { "h-sys-gpr178", HW_H_SYS_GPR178, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    531. 

  531.   { "h-sys-gpr179", HW_H_SYS_GPR179, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    532. 

  532.   { "h-sys-gpr180", HW_H_SYS_GPR180, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    533. 

  533.   { "h-sys-gpr181", HW_H_SYS_GPR181, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    534. 

  534.   { "h-sys-gpr182", HW_H_SYS_GPR182, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    535. 

  535.   { "h-sys-gpr183", HW_H_SYS_GPR183, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    536. 

  536.   { "h-sys-gpr184", HW_H_SYS_GPR184, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    537. 

  537.   { "h-sys-gpr185", HW_H_SYS_GPR185, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    538. 

  538.   { "h-sys-gpr186", HW_H_SYS_GPR186, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    539. 

  539.   { "h-sys-gpr187", HW_H_SYS_GPR187, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    540. 

  540.   { "h-sys-gpr188", HW_H_SYS_GPR188, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    541. 

  541.   { "h-sys-gpr189", HW_H_SYS_GPR189, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    542. 

  542.   { "h-sys-gpr190", HW_H_SYS_GPR190, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    543. 

  543.   { "h-sys-gpr191", HW_H_SYS_GPR191, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    544. 

  544.   { "h-sys-gpr192", HW_H_SYS_GPR192, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    545. 

  545.   { "h-sys-gpr193", HW_H_SYS_GPR193, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    546. 

  546.   { "h-sys-gpr194", HW_H_SYS_GPR194, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    547. 

  547.   { "h-sys-gpr195", HW_H_SYS_GPR195, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    548. 

  548.   { "h-sys-gpr196", HW_H_SYS_GPR196, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    549. 

  549.   { "h-sys-gpr197", HW_H_SYS_GPR197, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    550. 

  550.   { "h-sys-gpr198", HW_H_SYS_GPR198, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    551. 

  551.   { "h-sys-gpr199", HW_H_SYS_GPR199, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    552. 

  552.   { "h-sys-gpr200", HW_H_SYS_GPR200, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    553. 

  553.   { "h-sys-gpr201", HW_H_SYS_GPR201, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    554. 

  554.   { "h-sys-gpr202", HW_H_SYS_GPR202, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    555. 

  555.   { "h-sys-gpr203", HW_H_SYS_GPR203, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    556. 

  556.   { "h-sys-gpr204", HW_H_SYS_GPR204, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    557. 

  557.   { "h-sys-gpr205", HW_H_SYS_GPR205, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    558. 

  558.   { "h-sys-gpr206", HW_H_SYS_GPR206, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    559. 

  559.   { "h-sys-gpr207", HW_H_SYS_GPR207, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    560. 

  560.   { "h-sys-gpr208", HW_H_SYS_GPR208, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    561. 

  561.   { "h-sys-gpr209", HW_H_SYS_GPR209, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    562. 

  562.   { "h-sys-gpr210", HW_H_SYS_GPR210, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    563. 

  563.   { "h-sys-gpr211", HW_H_SYS_GPR211, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    564. 

  564.   { "h-sys-gpr212", HW_H_SYS_GPR212, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    565. 

  565.   { "h-sys-gpr213", HW_H_SYS_GPR213, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    566. 

  566.   { "h-sys-gpr214", HW_H_SYS_GPR214, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    567. 

  567.   { "h-sys-gpr215", HW_H_SYS_GPR215, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    568. 

  568.   { "h-sys-gpr216", HW_H_SYS_GPR216, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    569. 

  569.   { "h-sys-gpr217", HW_H_SYS_GPR217, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    570. 

  570.   { "h-sys-gpr218", HW_H_SYS_GPR218, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    571. 

  571.   { "h-sys-gpr219", HW_H_SYS_GPR219, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    572. 

  572.   { "h-sys-gpr220", HW_H_SYS_GPR220, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    573. 

  573.   { "h-sys-gpr221", HW_H_SYS_GPR221, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    574. 

  574.   { "h-sys-gpr222", HW_H_SYS_GPR222, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    575. 

  575.   { "h-sys-gpr223", HW_H_SYS_GPR223, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    576. 

  576.   { "h-sys-gpr224", HW_H_SYS_GPR224, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    577. 

  577.   { "h-sys-gpr225", HW_H_SYS_GPR225, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    578. 

  578.   { "h-sys-gpr226", HW_H_SYS_GPR226, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    579. 

  579.   { "h-sys-gpr227", HW_H_SYS_GPR227, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    580. 

  580.   { "h-sys-gpr228", HW_H_SYS_GPR228, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    581. 

  581.   { "h-sys-gpr229", HW_H_SYS_GPR229, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    582. 

  582.   { "h-sys-gpr230", HW_H_SYS_GPR230, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    583. 

  583.   { "h-sys-gpr231", HW_H_SYS_GPR231, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    584. 

  584.   { "h-sys-gpr232", HW_H_SYS_GPR232, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    585. 

  585.   { "h-sys-gpr233", HW_H_SYS_GPR233, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    586. 

  586.   { "h-sys-gpr234", HW_H_SYS_GPR234, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    587. 

  587.   { "h-sys-gpr235", HW_H_SYS_GPR235, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    588. 

  588.   { "h-sys-gpr236", HW_H_SYS_GPR236, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    589. 

  589.   { "h-sys-gpr237", HW_H_SYS_GPR237, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    590. 

  590.   { "h-sys-gpr238", HW_H_SYS_GPR238, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    591. 

  591.   { "h-sys-gpr239", HW_H_SYS_GPR239, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    592. 

  592.   { "h-sys-gpr240", HW_H_SYS_GPR240, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    593. 

  593.   { "h-sys-gpr241", HW_H_SYS_GPR241, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    594. 

  594.   { "h-sys-gpr242", HW_H_SYS_GPR242, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    595. 

  595.   { "h-sys-gpr243", HW_H_SYS_GPR243, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    596. 

  596.   { "h-sys-gpr244", HW_H_SYS_GPR244, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    597. 

  597.   { "h-sys-gpr245", HW_H_SYS_GPR245, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    598. 

  598.   { "h-sys-gpr246", HW_H_SYS_GPR246, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    599. 

  599.   { "h-sys-gpr247", HW_H_SYS_GPR247, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    600. 

  600.   { "h-sys-gpr248", HW_H_SYS_GPR248, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    601. 

  601.   { "h-sys-gpr249", HW_H_SYS_GPR249, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    602. 

  602.   { "h-sys-gpr250", HW_H_SYS_GPR250, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    603. 

  603.   { "h-sys-gpr251", HW_H_SYS_GPR251, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    604. 

  604.   { "h-sys-gpr252", HW_H_SYS_GPR252, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    605. 

  605.   { "h-sys-gpr253", HW_H_SYS_GPR253, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    606. 

  606.   { "h-sys-gpr254", HW_H_SYS_GPR254, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    607. 

  607.   { "h-sys-gpr255", HW_H_SYS_GPR255, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    608. 

  608.   { "h-sys-gpr256", HW_H_SYS_GPR256, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    609. 

  609.   { "h-sys-gpr257", HW_H_SYS_GPR257, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    610. 

  610.   { "h-sys-gpr258", HW_H_SYS_GPR258, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    611. 

  611.   { "h-sys-gpr259", HW_H_SYS_GPR259, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    612. 

  612.   { "h-sys-gpr260", HW_H_SYS_GPR260, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    613. 

  613.   { "h-sys-gpr261", HW_H_SYS_GPR261, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    614. 

  614.   { "h-sys-gpr262", HW_H_SYS_GPR262, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    615. 

  615.   { "h-sys-gpr263", HW_H_SYS_GPR263, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    616. 

  616.   { "h-sys-gpr264", HW_H_SYS_GPR264, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    617. 

  617.   { "h-sys-gpr265", HW_H_SYS_GPR265, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    618. 

  618.   { "h-sys-gpr266", HW_H_SYS_GPR266, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    619. 

  619.   { "h-sys-gpr267", HW_H_SYS_GPR267, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    620. 

  620.   { "h-sys-gpr268", HW_H_SYS_GPR268, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    621. 

  621.   { "h-sys-gpr269", HW_H_SYS_GPR269, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    622. 

  622.   { "h-sys-gpr270", HW_H_SYS_GPR270, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    623. 

  623.   { "h-sys-gpr271", HW_H_SYS_GPR271, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    624. 

  624.   { "h-sys-gpr272", HW_H_SYS_GPR272, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    625. 

  625.   { "h-sys-gpr273", HW_H_SYS_GPR273, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    626. 

  626.   { "h-sys-gpr274", HW_H_SYS_GPR274, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    627. 

  627.   { "h-sys-gpr275", HW_H_SYS_GPR275, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    628. 

  628.   { "h-sys-gpr276", HW_H_SYS_GPR276, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    629. 

  629.   { "h-sys-gpr277", HW_H_SYS_GPR277, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    630. 

  630.   { "h-sys-gpr278", HW_H_SYS_GPR278, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    631. 

  631.   { "h-sys-gpr279", HW_H_SYS_GPR279, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    632. 

  632.   { "h-sys-gpr280", HW_H_SYS_GPR280, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    633. 

  633.   { "h-sys-gpr281", HW_H_SYS_GPR281, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    634. 

  634.   { "h-sys-gpr282", HW_H_SYS_GPR282, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    635. 

  635.   { "h-sys-gpr283", HW_H_SYS_GPR283, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    636. 

  636.   { "h-sys-gpr284", HW_H_SYS_GPR284, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    637. 

  637.   { "h-sys-gpr285", HW_H_SYS_GPR285, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    638. 

  638.   { "h-sys-gpr286", HW_H_SYS_GPR286, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    639. 

  639.   { "h-sys-gpr287", HW_H_SYS_GPR287, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    640. 

  640.   { "h-sys-gpr288", HW_H_SYS_GPR288, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    641. 

  641.   { "h-sys-gpr289", HW_H_SYS_GPR289, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    642. 

  642.   { "h-sys-gpr290", HW_H_SYS_GPR290, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    643. 

  643.   { "h-sys-gpr291", HW_H_SYS_GPR291, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    644. 

  644.   { "h-sys-gpr292", HW_H_SYS_GPR292, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    645. 

  645.   { "h-sys-gpr293", HW_H_SYS_GPR293, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    646. 

  646.   { "h-sys-gpr294", HW_H_SYS_GPR294, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    647. 

  647.   { "h-sys-gpr295", HW_H_SYS_GPR295, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    648. 

  648.   { "h-sys-gpr296", HW_H_SYS_GPR296, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    649. 

  649.   { "h-sys-gpr297", HW_H_SYS_GPR297, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    650. 

  650.   { "h-sys-gpr298", HW_H_SYS_GPR298, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    651. 

  651.   { "h-sys-gpr299", HW_H_SYS_GPR299, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    652. 

  652.   { "h-sys-gpr300", HW_H_SYS_GPR300, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    653. 

  653.   { "h-sys-gpr301", HW_H_SYS_GPR301, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    654. 

  654.   { "h-sys-gpr302", HW_H_SYS_GPR302, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    655. 

  655.   { "h-sys-gpr303", HW_H_SYS_GPR303, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    656. 

  656.   { "h-sys-gpr304", HW_H_SYS_GPR304, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    657. 

  657.   { "h-sys-gpr305", HW_H_SYS_GPR305, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    658. 

  658.   { "h-sys-gpr306", HW_H_SYS_GPR306, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    659. 

  659.   { "h-sys-gpr307", HW_H_SYS_GPR307, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    660. 

  660.   { "h-sys-gpr308", HW_H_SYS_GPR308, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    661. 

  661.   { "h-sys-gpr309", HW_H_SYS_GPR309, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    662. 

  662.   { "h-sys-gpr310", HW_H_SYS_GPR310, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    663. 

  663.   { "h-sys-gpr311", HW_H_SYS_GPR311, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    664. 

  664.   { "h-sys-gpr312", HW_H_SYS_GPR312, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    665. 

  665.   { "h-sys-gpr313", HW_H_SYS_GPR313, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    666. 

  666.   { "h-sys-gpr314", HW_H_SYS_GPR314, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    667. 

  667.   { "h-sys-gpr315", HW_H_SYS_GPR315, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    668. 

  668.   { "h-sys-gpr316", HW_H_SYS_GPR316, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    669. 

  669.   { "h-sys-gpr317", HW_H_SYS_GPR317, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    670. 

  670.   { "h-sys-gpr318", HW_H_SYS_GPR318, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    671. 

  671.   { "h-sys-gpr319", HW_H_SYS_GPR319, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    672. 

  672.   { "h-sys-gpr320", HW_H_SYS_GPR320, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    673. 

  673.   { "h-sys-gpr321", HW_H_SYS_GPR321, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    674. 

  674.   { "h-sys-gpr322", HW_H_SYS_GPR322, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    675. 

  675.   { "h-sys-gpr323", HW_H_SYS_GPR323, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    676. 

  676.   { "h-sys-gpr324", HW_H_SYS_GPR324, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    677. 

  677.   { "h-sys-gpr325", HW_H_SYS_GPR325, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    678. 

  678.   { "h-sys-gpr326", HW_H_SYS_GPR326, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    679. 

  679.   { "h-sys-gpr327", HW_H_SYS_GPR327, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    680. 

  680.   { "h-sys-gpr328", HW_H_SYS_GPR328, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    681. 

  681.   { "h-sys-gpr329", HW_H_SYS_GPR329, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    682. 

  682.   { "h-sys-gpr330", HW_H_SYS_GPR330, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    683. 

  683.   { "h-sys-gpr331", HW_H_SYS_GPR331, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    684. 

  684.   { "h-sys-gpr332", HW_H_SYS_GPR332, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    685. 

  685.   { "h-sys-gpr333", HW_H_SYS_GPR333, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    686. 

  686.   { "h-sys-gpr334", HW_H_SYS_GPR334, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    687. 

  687.   { "h-sys-gpr335", HW_H_SYS_GPR335, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    688. 

  688.   { "h-sys-gpr336", HW_H_SYS_GPR336, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    689. 

  689.   { "h-sys-gpr337", HW_H_SYS_GPR337, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    690. 

  690.   { "h-sys-gpr338", HW_H_SYS_GPR338, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    691. 

  691.   { "h-sys-gpr339", HW_H_SYS_GPR339, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    692. 

  692.   { "h-sys-gpr340", HW_H_SYS_GPR340, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    693. 

  693.   { "h-sys-gpr341", HW_H_SYS_GPR341, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    694. 

  694.   { "h-sys-gpr342", HW_H_SYS_GPR342, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    695. 

  695.   { "h-sys-gpr343", HW_H_SYS_GPR343, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    696. 

  696.   { "h-sys-gpr344", HW_H_SYS_GPR344, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    697. 

  697.   { "h-sys-gpr345", HW_H_SYS_GPR345, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    698. 

  698.   { "h-sys-gpr346", HW_H_SYS_GPR346, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    699. 

  699.   { "h-sys-gpr347", HW_H_SYS_GPR347, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    700. 

  700.   { "h-sys-gpr348", HW_H_SYS_GPR348, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    701. 

  701.   { "h-sys-gpr349", HW_H_SYS_GPR349, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    702. 

  702.   { "h-sys-gpr350", HW_H_SYS_GPR350, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    703. 

  703.   { "h-sys-gpr351", HW_H_SYS_GPR351, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    704. 

  704.   { "h-sys-gpr352", HW_H_SYS_GPR352, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    705. 

  705.   { "h-sys-gpr353", HW_H_SYS_GPR353, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    706. 

  706.   { "h-sys-gpr354", HW_H_SYS_GPR354, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    707. 

  707.   { "h-sys-gpr355", HW_H_SYS_GPR355, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    708. 

  708.   { "h-sys-gpr356", HW_H_SYS_GPR356, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    709. 

  709.   { "h-sys-gpr357", HW_H_SYS_GPR357, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    710. 

  710.   { "h-sys-gpr358", HW_H_SYS_GPR358, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    711. 

  711.   { "h-sys-gpr359", HW_H_SYS_GPR359, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    712. 

  712.   { "h-sys-gpr360", HW_H_SYS_GPR360, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    713. 

  713.   { "h-sys-gpr361", HW_H_SYS_GPR361, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    714. 

  714.   { "h-sys-gpr362", HW_H_SYS_GPR362, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    715. 

  715.   { "h-sys-gpr363", HW_H_SYS_GPR363, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    716. 

  716.   { "h-sys-gpr364", HW_H_SYS_GPR364, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    717. 

  717.   { "h-sys-gpr365", HW_H_SYS_GPR365, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    718. 

  718.   { "h-sys-gpr366", HW_H_SYS_GPR366, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    719. 

  719.   { "h-sys-gpr367", HW_H_SYS_GPR367, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    720. 

  720.   { "h-sys-gpr368", HW_H_SYS_GPR368, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    721. 

  721.   { "h-sys-gpr369", HW_H_SYS_GPR369, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    722. 

  722.   { "h-sys-gpr370", HW_H_SYS_GPR370, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    723. 

  723.   { "h-sys-gpr371", HW_H_SYS_GPR371, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    724. 

  724.   { "h-sys-gpr372", HW_H_SYS_GPR372, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    725. 

  725.   { "h-sys-gpr373", HW_H_SYS_GPR373, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    726. 

  726.   { "h-sys-gpr374", HW_H_SYS_GPR374, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    727. 

  727.   { "h-sys-gpr375", HW_H_SYS_GPR375, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    728. 

  728.   { "h-sys-gpr376", HW_H_SYS_GPR376, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    729. 

  729.   { "h-sys-gpr377", HW_H_SYS_GPR377, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    730. 

  730.   { "h-sys-gpr378", HW_H_SYS_GPR378, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    731. 

  731.   { "h-sys-gpr379", HW_H_SYS_GPR379, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    732. 

  732.   { "h-sys-gpr380", HW_H_SYS_GPR380, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    733. 

  733.   { "h-sys-gpr381", HW_H_SYS_GPR381, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    734. 

  734.   { "h-sys-gpr382", HW_H_SYS_GPR382, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    735. 

  735.   { "h-sys-gpr383", HW_H_SYS_GPR383, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    736. 

  736.   { "h-sys-gpr384", HW_H_SYS_GPR384, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    737. 

  737.   { "h-sys-gpr385", HW_H_SYS_GPR385, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    738. 

  738.   { "h-sys-gpr386", HW_H_SYS_GPR386, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    739. 

  739.   { "h-sys-gpr387", HW_H_SYS_GPR387, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    740. 

  740.   { "h-sys-gpr388", HW_H_SYS_GPR388, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    741. 

  741.   { "h-sys-gpr389", HW_H_SYS_GPR389, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    742. 

  742.   { "h-sys-gpr390", HW_H_SYS_GPR390, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    743. 

  743.   { "h-sys-gpr391", HW_H_SYS_GPR391, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    744. 

  744.   { "h-sys-gpr392", HW_H_SYS_GPR392, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    745. 

  745.   { "h-sys-gpr393", HW_H_SYS_GPR393, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    746. 

  746.   { "h-sys-gpr394", HW_H_SYS_GPR394, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    747. 

  747.   { "h-sys-gpr395", HW_H_SYS_GPR395, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    748. 

  748.   { "h-sys-gpr396", HW_H_SYS_GPR396, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    749. 

  749.   { "h-sys-gpr397", HW_H_SYS_GPR397, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    750. 

  750.   { "h-sys-gpr398", HW_H_SYS_GPR398, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    751. 

  751.   { "h-sys-gpr399", HW_H_SYS_GPR399, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    752. 

  752.   { "h-sys-gpr400", HW_H_SYS_GPR400, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    753. 

  753.   { "h-sys-gpr401", HW_H_SYS_GPR401, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    754. 

  754.   { "h-sys-gpr402", HW_H_SYS_GPR402, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    755. 

  755.   { "h-sys-gpr403", HW_H_SYS_GPR403, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    756. 

  756.   { "h-sys-gpr404", HW_H_SYS_GPR404, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    757. 

  757.   { "h-sys-gpr405", HW_H_SYS_GPR405, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    758. 

  758.   { "h-sys-gpr406", HW_H_SYS_GPR406, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    759. 

  759.   { "h-sys-gpr407", HW_H_SYS_GPR407, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    760. 

  760.   { "h-sys-gpr408", HW_H_SYS_GPR408, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    761. 

  761.   { "h-sys-gpr409", HW_H_SYS_GPR409, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    762. 

  762.   { "h-sys-gpr410", HW_H_SYS_GPR410, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    763. 

  763.   { "h-sys-gpr411", HW_H_SYS_GPR411, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    764. 

  764.   { "h-sys-gpr412", HW_H_SYS_GPR412, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    765. 

  765.   { "h-sys-gpr413", HW_H_SYS_GPR413, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    766. 

  766.   { "h-sys-gpr414", HW_H_SYS_GPR414, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    767. 

  767.   { "h-sys-gpr415", HW_H_SYS_GPR415, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    768. 

  768.   { "h-sys-gpr416", HW_H_SYS_GPR416, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    769. 

  769.   { "h-sys-gpr417", HW_H_SYS_GPR417, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    770. 

  770.   { "h-sys-gpr418", HW_H_SYS_GPR418, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    771. 

  771.   { "h-sys-gpr419", HW_H_SYS_GPR419, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    772. 

  772.   { "h-sys-gpr420", HW_H_SYS_GPR420, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    773. 

  773.   { "h-sys-gpr421", HW_H_SYS_GPR421, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    774. 

  774.   { "h-sys-gpr422", HW_H_SYS_GPR422, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    775. 

  775.   { "h-sys-gpr423", HW_H_SYS_GPR423, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    776. 

  776.   { "h-sys-gpr424", HW_H_SYS_GPR424, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    777. 

  777.   { "h-sys-gpr425", HW_H_SYS_GPR425, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    778. 

  778.   { "h-sys-gpr426", HW_H_SYS_GPR426, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    779. 

  779.   { "h-sys-gpr427", HW_H_SYS_GPR427, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    780. 

  780.   { "h-sys-gpr428", HW_H_SYS_GPR428, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    781. 

  781.   { "h-sys-gpr429", HW_H_SYS_GPR429, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    782. 

  782.   { "h-sys-gpr430", HW_H_SYS_GPR430, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    783. 

  783.   { "h-sys-gpr431", HW_H_SYS_GPR431, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    784. 

  784.   { "h-sys-gpr432", HW_H_SYS_GPR432, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    785. 

  785.   { "h-sys-gpr433", HW_H_SYS_GPR433, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    786. 

  786.   { "h-sys-gpr434", HW_H_SYS_GPR434, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    787. 

  787.   { "h-sys-gpr435", HW_H_SYS_GPR435, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    788. 

  788.   { "h-sys-gpr436", HW_H_SYS_GPR436, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    789. 

  789.   { "h-sys-gpr437", HW_H_SYS_GPR437, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    790. 

  790.   { "h-sys-gpr438", HW_H_SYS_GPR438, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    791. 

  791.   { "h-sys-gpr439", HW_H_SYS_GPR439, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    792. 

  792.   { "h-sys-gpr440", HW_H_SYS_GPR440, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    793. 

  793.   { "h-sys-gpr441", HW_H_SYS_GPR441, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    794. 

  794.   { "h-sys-gpr442", HW_H_SYS_GPR442, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    795. 

  795.   { "h-sys-gpr443", HW_H_SYS_GPR443, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    796. 

  796.   { "h-sys-gpr444", HW_H_SYS_GPR444, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    797. 

  797.   { "h-sys-gpr445", HW_H_SYS_GPR445, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    798. 

  798.   { "h-sys-gpr446", HW_H_SYS_GPR446, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    799. 

  799.   { "h-sys-gpr447", HW_H_SYS_GPR447, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    800. 

  800.   { "h-sys-gpr448", HW_H_SYS_GPR448, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    801. 

  801.   { "h-sys-gpr449", HW_H_SYS_GPR449, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    802. 

  802.   { "h-sys-gpr450", HW_H_SYS_GPR450, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    803. 

  803.   { "h-sys-gpr451", HW_H_SYS_GPR451, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    804. 

  804.   { "h-sys-gpr452", HW_H_SYS_GPR452, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    805. 

  805.   { "h-sys-gpr453", HW_H_SYS_GPR453, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    806. 

  806.   { "h-sys-gpr454", HW_H_SYS_GPR454, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    807. 

  807.   { "h-sys-gpr455", HW_H_SYS_GPR455, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    808. 

  808.   { "h-sys-gpr456", HW_H_SYS_GPR456, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    809. 

  809.   { "h-sys-gpr457", HW_H_SYS_GPR457, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    810. 

  810.   { "h-sys-gpr458", HW_H_SYS_GPR458, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    811. 

  811.   { "h-sys-gpr459", HW_H_SYS_GPR459, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    812. 

  812.   { "h-sys-gpr460", HW_H_SYS_GPR460, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    813. 

  813.   { "h-sys-gpr461", HW_H_SYS_GPR461, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    814. 

  814.   { "h-sys-gpr462", HW_H_SYS_GPR462, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    815. 

  815.   { "h-sys-gpr463", HW_H_SYS_GPR463, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    816. 

  816.   { "h-sys-gpr464", HW_H_SYS_GPR464, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    817. 

  817.   { "h-sys-gpr465", HW_H_SYS_GPR465, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    818. 

  818.   { "h-sys-gpr466", HW_H_SYS_GPR466, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    819. 

  819.   { "h-sys-gpr467", HW_H_SYS_GPR467, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    820. 

  820.   { "h-sys-gpr468", HW_H_SYS_GPR468, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    821. 

  821.   { "h-sys-gpr469", HW_H_SYS_GPR469, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    822. 

  822.   { "h-sys-gpr470", HW_H_SYS_GPR470, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    823. 

  823.   { "h-sys-gpr471", HW_H_SYS_GPR471, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    824. 

  824.   { "h-sys-gpr472", HW_H_SYS_GPR472, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    825. 

  825.   { "h-sys-gpr473", HW_H_SYS_GPR473, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    826. 

  826.   { "h-sys-gpr474", HW_H_SYS_GPR474, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    827. 

  827.   { "h-sys-gpr475", HW_H_SYS_GPR475, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    828. 

  828.   { "h-sys-gpr476", HW_H_SYS_GPR476, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    829. 

  829.   { "h-sys-gpr477", HW_H_SYS_GPR477, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    830. 

  830.   { "h-sys-gpr478", HW_H_SYS_GPR478, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    831. 

  831.   { "h-sys-gpr479", HW_H_SYS_GPR479, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    832. 

  832.   { "h-sys-gpr480", HW_H_SYS_GPR480, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    833. 

  833.   { "h-sys-gpr481", HW_H_SYS_GPR481, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    834. 

  834.   { "h-sys-gpr482", HW_H_SYS_GPR482, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    835. 

  835.   { "h-sys-gpr483", HW_H_SYS_GPR483, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    836. 

  836.   { "h-sys-gpr484", HW_H_SYS_GPR484, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    837. 

  837.   { "h-sys-gpr485", HW_H_SYS_GPR485, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    838. 

  838.   { "h-sys-gpr486", HW_H_SYS_GPR486, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    839. 

  839.   { "h-sys-gpr487", HW_H_SYS_GPR487, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    840. 

  840.   { "h-sys-gpr488", HW_H_SYS_GPR488, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    841. 

  841.   { "h-sys-gpr489", HW_H_SYS_GPR489, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    842. 

  842.   { "h-sys-gpr490", HW_H_SYS_GPR490, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    843. 

  843.   { "h-sys-gpr491", HW_H_SYS_GPR491, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    844. 

  844.   { "h-sys-gpr492", HW_H_SYS_GPR492, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    845. 

  845.   { "h-sys-gpr493", HW_H_SYS_GPR493, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    846. 

  846.   { "h-sys-gpr494", HW_H_SYS_GPR494, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    847. 

  847.   { "h-sys-gpr495", HW_H_SYS_GPR495, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    848. 

  848.   { "h-sys-gpr496", HW_H_SYS_GPR496, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    849. 

  849.   { "h-sys-gpr497", HW_H_SYS_GPR497, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    850. 

  850.   { "h-sys-gpr498", HW_H_SYS_GPR498, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    851. 

  851.   { "h-sys-gpr499", HW_H_SYS_GPR499, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    852. 

  852.   { "h-sys-gpr500", HW_H_SYS_GPR500, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    853. 

  853.   { "h-sys-gpr501", HW_H_SYS_GPR501, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    854. 

  854.   { "h-sys-gpr502", HW_H_SYS_GPR502, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    855. 

  855.   { "h-sys-gpr503", HW_H_SYS_GPR503, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    856. 

  856.   { "h-sys-gpr504", HW_H_SYS_GPR504, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    857. 

  857.   { "h-sys-gpr505", HW_H_SYS_GPR505, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    858. 

  858.   { "h-sys-gpr506", HW_H_SYS_GPR506, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    859. 

  859.   { "h-sys-gpr507", HW_H_SYS_GPR507, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    860. 

  860.   { "h-sys-gpr508", HW_H_SYS_GPR508, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    861. 

  861.   { "h-sys-gpr509", HW_H_SYS_GPR509, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    862. 

  862.   { "h-sys-gpr510", HW_H_SYS_GPR510, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    863. 

  863.   { "h-sys-gpr511", HW_H_SYS_GPR511, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    864. 

  864.   { "h-mac-maclo", HW_H_MAC_MACLO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    865. 

  865.   { "h-mac-machi", HW_H_MAC_MACHI, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    866. 

  866.   { "h-tick-ttmr", HW_H_TICK_TTMR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    867. 

  867.   { "h-sys-vr-rev", HW_H_SYS_VR_REV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    868. 

  868.   { "h-sys-vr-cfg", HW_H_SYS_VR_CFG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    869. 

  869.   { "h-sys-vr-ver", HW_H_SYS_VR_VER, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    870. 

  870.   { "h-sys-upr-up", HW_H_SYS_UPR_UP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    871. 

  871.   { "h-sys-upr-dcp", HW_H_SYS_UPR_DCP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    872. 

  872.   { "h-sys-upr-icp", HW_H_SYS_UPR_ICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    873. 

  873.   { "h-sys-upr-dmp", HW_H_SYS_UPR_DMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    874. 

  874.   { "h-sys-upr-mp", HW_H_SYS_UPR_MP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    875. 

  875.   { "h-sys-upr-imp", HW_H_SYS_UPR_IMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    876. 

  876.   { "h-sys-upr-dup", HW_H_SYS_UPR_DUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    877. 

  877.   { "h-sys-upr-pcup", HW_H_SYS_UPR_PCUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    878. 

  878.   { "h-sys-upr-picp", HW_H_SYS_UPR_PICP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    879. 

  879.   { "h-sys-upr-pmp", HW_H_SYS_UPR_PMP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    880. 

  880.   { "h-sys-upr-ttp", HW_H_SYS_UPR_TTP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    881. 

  881.   { "h-sys-upr-cup", HW_H_SYS_UPR_CUP, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    882. 

  882.   { "h-sys-cpucfgr-nsgr", HW_H_SYS_CPUCFGR_NSGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    883. 

  883.   { "h-sys-cpucfgr-cgf", HW_H_SYS_CPUCFGR_CGF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    884. 

  884.   { "h-sys-cpucfgr-ob32s", HW_H_SYS_CPUCFGR_OB32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    885. 

  885.   { "h-sys-cpucfgr-ob64s", HW_H_SYS_CPUCFGR_OB64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    886. 

  886.   { "h-sys-cpucfgr-of32s", HW_H_SYS_CPUCFGR_OF32S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    887. 

  887.   { "h-sys-cpucfgr-of64s", HW_H_SYS_CPUCFGR_OF64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    888. 

  888.   { "h-sys-cpucfgr-ov64s", HW_H_SYS_CPUCFGR_OV64S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    889. 

  889.   { "h-sys-cpucfgr-nd", HW_H_SYS_CPUCFGR_ND, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    890. 

  890.   { "h-sys-sr-sm", HW_H_SYS_SR_SM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    891. 

  891.   { "h-sys-sr-tee", HW_H_SYS_SR_TEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    892. 

  892.   { "h-sys-sr-iee", HW_H_SYS_SR_IEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    893. 

  893.   { "h-sys-sr-dce", HW_H_SYS_SR_DCE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    894. 

  894.   { "h-sys-sr-ice", HW_H_SYS_SR_ICE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    895. 

  895.   { "h-sys-sr-dme", HW_H_SYS_SR_DME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    896. 

  896.   { "h-sys-sr-ime", HW_H_SYS_SR_IME, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    897. 

  897.   { "h-sys-sr-lee", HW_H_SYS_SR_LEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    898. 

  898.   { "h-sys-sr-ce", HW_H_SYS_SR_CE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    899. 

  899.   { "h-sys-sr-f", HW_H_SYS_SR_F, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    900. 

  900.   { "h-sys-sr-cy", HW_H_SYS_SR_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    901. 

  901.   { "h-sys-sr-ov", HW_H_SYS_SR_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    902. 

  902.   { "h-sys-sr-ove", HW_H_SYS_SR_OVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    903. 

  903.   { "h-sys-sr-dsx", HW_H_SYS_SR_DSX, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    904. 

  904.   { "h-sys-sr-eph", HW_H_SYS_SR_EPH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    905. 

  905.   { "h-sys-sr-fo", HW_H_SYS_SR_FO, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    906. 

  906.   { "h-sys-sr-sumra", HW_H_SYS_SR_SUMRA, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    907. 

  907.   { "h-sys-sr-cid", HW_H_SYS_SR_CID, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    908. 

  908.   { "h-sys-fpcsr-fpee", HW_H_SYS_FPCSR_FPEE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    909. 

  909.   { "h-sys-fpcsr-rm", HW_H_SYS_FPCSR_RM, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    910. 

  910.   { "h-sys-fpcsr-ovf", HW_H_SYS_FPCSR_OVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    911. 

  911.   { "h-sys-fpcsr-unf", HW_H_SYS_FPCSR_UNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    912. 

  912.   { "h-sys-fpcsr-snf", HW_H_SYS_FPCSR_SNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    913. 

  913.   { "h-sys-fpcsr-qnf", HW_H_SYS_FPCSR_QNF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    914. 

  914.   { "h-sys-fpcsr-zf", HW_H_SYS_FPCSR_ZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    915. 

  915.   { "h-sys-fpcsr-ixf", HW_H_SYS_FPCSR_IXF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    916. 

  916.   { "h-sys-fpcsr-ivf", HW_H_SYS_FPCSR_IVF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    917. 

  917.   { "h-sys-fpcsr-inf", HW_H_SYS_FPCSR_INF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    918. 

  918.   { "h-sys-fpcsr-dzf", HW_H_SYS_FPCSR_DZF, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    919. 

  919.   { "h-simm16", HW_H_SIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
    920. 

  920.   { "h-uimm16", HW_H_UIMM16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    921. 

  921.   { "h-uimm6", HW_H_UIMM6, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    922. 

  922.   { "h-atomic-reserve", HW_H_ATOMIC_RESERVE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    923. 

  923.   { "h-atomic-address", HW_H_ATOMIC_ADDRESS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    924. 

  924.   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
    925. 

  925. };
    926. 

  926. 

  927. #undef A
    928. 

  928. 

  929. 

  930. /* The instruction field table.  */
    931. 

  931. 

  932. #define A(a) (1 << CGEN_IFLD_##a)
    933. 

  933. 

  934. const CGEN_IFLD or1k_cgen_ifld_table[] =
    935. 

  935. {
    936. 

  936.   { OR1K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    937. 

  937.   { OR1K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    938. 

  938.   { OR1K_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    939. 

  939.   { OR1K_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    940. 

  940.   { OR1K_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    941. 

  941.   { OR1K_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    942. 

  942.   { OR1K_F_OP_25_2, "f-op-25-2", 0, 32, 25, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    943. 

  943.   { OR1K_F_OP_25_5, "f-op-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    944. 

  944.   { OR1K_F_OP_16_1, "f-op-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    945. 

  945.   { OR1K_F_OP_7_4, "f-op-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    946. 

  946.   { OR1K_F_OP_3_4, "f-op-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    947. 

  947.   { OR1K_F_OP_9_2, "f-op-9-2", 0, 32, 9, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    948. 

  948.   { OR1K_F_OP_9_4, "f-op-9-4", 0, 32, 9, 4, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    949. 

  949.   { OR1K_F_OP_7_8, "f-op-7-8", 0, 32, 7, 8, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    950. 

  950.   { OR1K_F_OP_7_2, "f-op-7-2", 0, 32, 7, 2, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    951. 

  951.   { OR1K_F_RESV_25_26, "f-resv-25-26", 0, 32, 25, 26, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    952. 

  952.   { OR1K_F_RESV_25_10, "f-resv-25-10", 0, 32, 25, 10, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    953. 

  953.   { OR1K_F_RESV_25_5, "f-resv-25-5", 0, 32, 25, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    954. 

  954.   { OR1K_F_RESV_23_8, "f-resv-23-8", 0, 32, 23, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    955. 

  955.   { OR1K_F_RESV_20_21, "f-resv-20-21", 0, 32, 20, 21, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    956. 

  956.   { OR1K_F_RESV_20_5, "f-resv-20-5", 0, 32, 20, 5, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    957. 

  957.   { OR1K_F_RESV_20_4, "f-resv-20-4", 0, 32, 20, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    958. 

  958.   { OR1K_F_RESV_15_8, "f-resv-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    959. 

  959.   { OR1K_F_RESV_15_6, "f-resv-15-6", 0, 32, 15, 6, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    960. 

  960.   { OR1K_F_RESV_10_11, "f-resv-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    961. 

  961.   { OR1K_F_RESV_10_7, "f-resv-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    962. 

  962.   { OR1K_F_RESV_10_3, "f-resv-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    963. 

  963.   { OR1K_F_RESV_10_1, "f-resv-10-1", 0, 32, 10, 1, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    964. 

  964.   { OR1K_F_RESV_7_4, "f-resv-7-4", 0, 32, 7, 4, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    965. 

  965.   { OR1K_F_RESV_5_2, "f-resv-5-2", 0, 32, 5, 2, { 0|A(RESERVED), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    966. 

  966.   { OR1K_F_IMM16_25_5, "f-imm16-25-5", 0, 32, 25, 5, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    967. 

  967.   { OR1K_F_IMM16_10_11, "f-imm16-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    968. 

  968.   { OR1K_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    969. 

  969.   { OR1K_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    970. 

  970.   { OR1K_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    971. 

  971.   { OR1K_F_UIMM6, "f-uimm6", 0, 32, 5, 6, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    972. 

  972.   { OR1K_F_UIMM16_SPLIT, "f-uimm16-split", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    973. 

  973.   { OR1K_F_SIMM16_SPLIT, "f-simm16-split", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    974. 

  974.   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
    975. 

  975. };
    976. 

  976. 

  977. #undef A
    978. 

  978. 

  979. 

  980. 

  981. /* multi ifield declarations */
    982. 

  982. 

  983. const CGEN_MAYBE_MULTI_IFLD OR1K_F_UIMM16_SPLIT_MULTI_IFIELD [];
    984. 

  984. const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [];
    985. 

  985. 

  986. 

  987. /* multi ifield definitions */
    988. 

  988. 

  989. const CGEN_MAYBE_MULTI_IFLD OR1K_F_UIMM16_SPLIT_MULTI_IFIELD [] =
    990. 

  990. {
    991. 

  991.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } },
    992. 

  992.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
    993. 

  993.     { 0, { (const PTR) 0 } }
    994. 

  994. };
    995. 

  995. const CGEN_MAYBE_MULTI_IFLD OR1K_F_SIMM16_SPLIT_MULTI_IFIELD [] =
    996. 

  996. {
    997. 

  997.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_25_5] } },
    998. 

  998.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_IMM16_10_11] } },
    999. 

  999.     { 0, { (const PTR) 0 } }
    1000. 

  1000. };
    1001. 

  1001. 

  1002. /* The operand table.  */
    1003. 

  1003. 

  1004. #define A(a) (1 << CGEN_OPERAND_##a)
    1005. 

  1005. #define OPERAND(op) OR1K_OPERAND_##op
    1006. 

  1006. 

  1007. const CGEN_OPERAND or1k_cgen_operand_table[] =
    1008. 

  1008. {
    1009. 

  1009. /* pc: program counter */
    1010. 

  1010.   { "pc", OR1K_OPERAND_PC, HW_H_PC, 0, 0,
    1011. 

  1011.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_NIL] } },
    1012. 

  1012.     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    1013. 

  1013. /* sys-sr: supervision register */
    1014. 

  1014.   { "sys-sr", OR1K_OPERAND_SYS_SR, HW_H_SYS_SR, 0, 0,
    1015. 

  1015.     { 0, { (const PTR) 0 } },
    1016. 

  1016.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1017. 

  1017. /* sys-esr0: exception supervision register 0 */
    1018. 

  1018.   { "sys-esr0", OR1K_OPERAND_SYS_ESR0, HW_H_SYS_ESR0, 0, 0,
    1019. 

  1019.     { 0, { (const PTR) 0 } },
    1020. 

  1020.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1021. 

  1021. /* sys-epcr0: exception PC register 0 */
    1022. 

  1022.   { "sys-epcr0", OR1K_OPERAND_SYS_EPCR0, HW_H_SYS_EPCR0, 0, 0,
    1023. 

  1023.     { 0, { (const PTR) 0 } },
    1024. 

  1024.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1025. 

  1025. /* sys-sr-lee: SR little endian enable bit */
    1026. 

  1026.   { "sys-sr-lee", OR1K_OPERAND_SYS_SR_LEE, HW_H_SYS_SR_LEE, 0, 0,
    1027. 

  1027.     { 0, { (const PTR) 0 } },
    1028. 

  1028.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1029. 

  1029. /* sys-sr-f: SR flag bit */
    1030. 

  1030.   { "sys-sr-f", OR1K_OPERAND_SYS_SR_F, HW_H_SYS_SR_F, 0, 0,
    1031. 

  1031.     { 0, { (const PTR) 0 } },
    1032. 

  1032.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1033. 

  1033. /* sys-sr-cy: SR carry bit */
    1034. 

  1034.   { "sys-sr-cy", OR1K_OPERAND_SYS_SR_CY, HW_H_SYS_SR_CY, 0, 0,
    1035. 

  1035.     { 0, { (const PTR) 0 } },
    1036. 

  1036.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1037. 

  1037. /* sys-sr-ov: SR overflow bit */
    1038. 

  1038.   { "sys-sr-ov", OR1K_OPERAND_SYS_SR_OV, HW_H_SYS_SR_OV, 0, 0,
    1039. 

  1039.     { 0, { (const PTR) 0 } },
    1040. 

  1040.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1041. 

  1041. /* sys-sr-ove: SR overflow exception enable bit */
    1042. 

  1042.   { "sys-sr-ove", OR1K_OPERAND_SYS_SR_OVE, HW_H_SYS_SR_OVE, 0, 0,
    1043. 

  1043.     { 0, { (const PTR) 0 } },
    1044. 

  1044.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1045. 

  1045. /* sys-cpucfgr-ob64s: CPUCFGR ORBIS64 supported bit */
    1046. 

  1046.   { "sys-cpucfgr-ob64s", OR1K_OPERAND_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OB64S, 0, 0,
    1047. 

  1047.     { 0, { (const PTR) 0 } },
    1048. 

  1048.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1049. 

  1049. /* sys-cpucfgr-nd: CPUCFGR no delay bit */
    1050. 

  1050.   { "sys-cpucfgr-nd", OR1K_OPERAND_SYS_CPUCFGR_ND, HW_H_SYS_CPUCFGR_ND, 0, 0,
    1051. 

  1051.     { 0, { (const PTR) 0 } },
    1052. 

  1052.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1053. 

  1053. /* sys-fpcsr-rm: floating point round mode */
    1054. 

  1054.   { "sys-fpcsr-rm", OR1K_OPERAND_SYS_FPCSR_RM, HW_H_SYS_FPCSR_RM, 0, 0,
    1055. 

  1055.     { 0, { (const PTR) 0 } },
    1056. 

  1056.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1057. 

  1057. /* mac-machi: MAC HI result register */
    1058. 

  1058.   { "mac-machi", OR1K_OPERAND_MAC_MACHI, HW_H_MAC_MACHI, 0, 0,
    1059. 

  1059.     { 0, { (const PTR) 0 } },
    1060. 

  1060.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1061. 

  1061. /* mac-maclo: MAC LO result register */
    1062. 

  1062.   { "mac-maclo", OR1K_OPERAND_MAC_MACLO, HW_H_MAC_MACLO, 0, 0,
    1063. 

  1063.     { 0, { (const PTR) 0 } },
    1064. 

  1064.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1065. 

  1065. /* atomic-reserve: atomic reserve flag */
    1066. 

  1066.   { "atomic-reserve", OR1K_OPERAND_ATOMIC_RESERVE, HW_H_ATOMIC_RESERVE, 0, 0,
    1067. 

  1067.     { 0, { (const PTR) 0 } },
    1068. 

  1068.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1069. 

  1069. /* atomic-address: atomic address */
    1070. 

  1070.   { "atomic-address", OR1K_OPERAND_ATOMIC_ADDRESS, HW_H_ATOMIC_ADDRESS, 0, 0,
    1071. 

  1071.     { 0, { (const PTR) 0 } },
    1072. 

  1072.     { 0|A(SEM_ONLY), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1073. 

  1073. /* uimm6: uimm6 */
    1074. 

  1074.   { "uimm6", OR1K_OPERAND_UIMM6, HW_H_UIMM6, 5, 6,
    1075. 

  1075.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM6] } },
    1076. 

  1076.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1077. 

  1077. /* rD: destination register */
    1078. 

  1078.   { "rD", OR1K_OPERAND_RD, HW_H_GPR, 25, 5,
    1079. 

  1079.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1080. 

  1080.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1081. 

  1081. /* rA: source register A */
    1082. 

  1082.   { "rA", OR1K_OPERAND_RA, HW_H_GPR, 20, 5,
    1083. 

  1083.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
    1084. 

  1084.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1085. 

  1085. /* rB: source register B */
    1086. 

  1086.   { "rB", OR1K_OPERAND_RB, HW_H_GPR, 15, 5,
    1087. 

  1087.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
    1088. 

  1088.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1089. 

  1089. /* disp26: pc-rel 26 bit */
    1090. 

  1090.   { "disp26", OR1K_OPERAND_DISP26, HW_H_IADDR, 25, 26,
    1091. 

  1091.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_DISP26] } },
    1092. 

  1092.     { 0|A(PCREL_ADDR), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1093. 

  1093. /* simm16: 16-bit signed immediate */
    1094. 

  1094.   { "simm16", OR1K_OPERAND_SIMM16, HW_H_SIMM16, 15, 16,
    1095. 

  1095.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_SIMM16] } },
    1096. 

  1096.     { 0|A(SIGN_OPT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1097. 

  1097. /* uimm16: 16-bit unsigned immediate */
    1098. 

  1098.   { "uimm16", OR1K_OPERAND_UIMM16, HW_H_UIMM16, 15, 16,
    1099. 

  1099.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_UIMM16] } },
    1100. 

  1100.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1101. 

  1101. /* simm16-split: split 16-bit signed immediate */
    1102. 

  1102.   { "simm16-split", OR1K_OPERAND_SIMM16_SPLIT, HW_H_SIMM16, 10, 16,
    1103. 

  1103.     { 2, { (const PTR) &OR1K_F_SIMM16_SPLIT_MULTI_IFIELD[0] } },
    1104. 

  1104.     { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1105. 

  1105. /* uimm16-split: split 16-bit unsigned immediate */
    1106. 

  1106.   { "uimm16-split", OR1K_OPERAND_UIMM16_SPLIT, HW_H_UIMM16, 10, 16,
    1107. 

  1107.     { 2, { (const PTR) &OR1K_F_UIMM16_SPLIT_MULTI_IFIELD[0] } },
    1108. 

  1108.     { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1109. 

  1109. /* rDSF: destination register (single floating point mode) */
    1110. 

  1110.   { "rDSF", OR1K_OPERAND_RDSF, HW_H_FSR, 25, 5,
    1111. 

  1111.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1112. 

  1112.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1113. 

  1113. /* rASF: source register A (single floating point mode) */
    1114. 

  1114.   { "rASF", OR1K_OPERAND_RASF, HW_H_FSR, 20, 5,
    1115. 

  1115.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
    1116. 

  1116.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1117. 

  1117. /* rBSF: source register B (single floating point mode) */
    1118. 

  1118.   { "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
    1119. 

  1119.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
    1120. 

  1120.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1121. 

  1121. /* rDDF: destination register (double floating point mode) */
    1122. 

  1122.   { "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5,
    1123. 

  1123.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1124. 

  1124.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1125. 

  1125. /* rADF: source register A (double floating point mode) */
    1126. 

  1126.   { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 25, 5,
    1127. 

  1127.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1128. 

  1128.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1129. 

  1129. /* rBDF: source register B (double floating point mode) */
    1130. 

  1130.   { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 25, 5,
    1131. 

  1131.     { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
    1132. 

  1132.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }  },
    1133. 

  1133. /* sentinel */
    1134. 

  1134.   { 0, 0, 0, 0, 0,
    1135. 

  1135.     { 0, { (const PTR) 0 } },
    1136. 

  1136.     { 0, { { { (1<<MACH_BASE), 0 } } } } }
    1137. 

  1137. };
    1138. 

  1138. 

  1139. #undef A
    1140. 

  1140. 

  1141. 

  1142. /* The instruction table.  */
    1143. 

  1143. 

  1144. #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
    1145. 

  1145. #define A(a) (1 << CGEN_INSN_##a)
    1146. 

  1146. 

  1147. static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
    1148. 

  1148. {
    1149. 

  1149.   /* Special null first entry.
    1150. 

  1150.      A `num' value of zero is thus invalid.
    1151. 

  1151.      Also, the special `invalid' insn resides here.  */
    1152. 

  1152.   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    1153. 

  1153. /* l.j ${disp26} */
    1154. 

  1154.   {
    1155. 

  1155.     OR1K_INSN_L_J, "l-j", "l.j", 32,
    1156. 

  1156.     { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1157. 

  1157.   },
    1158. 

  1158. /* l.jal ${disp26} */
    1159. 

  1159.   {
    1160. 

  1160.     OR1K_INSN_L_JAL, "l-jal", "l.jal", 32,
    1161. 

  1161.     { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1162. 

  1162.   },
    1163. 

  1163. /* l.jr $rB */
    1164. 

  1164.   {
    1165. 

  1165.     OR1K_INSN_L_JR, "l-jr", "l.jr", 32,
    1166. 

  1166.     { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1167. 

  1167.   },
    1168. 

  1168. /* l.jalr $rB */
    1169. 

  1169.   {
    1170. 

  1170.     OR1K_INSN_L_JALR, "l-jalr", "l.jalr", 32,
    1171. 

  1171.     { 0|A(UNCOND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1172. 

  1172.   },
    1173. 

  1173. /* l.bnf ${disp26} */
    1174. 

  1174.   {
    1175. 

  1175.     OR1K_INSN_L_BNF, "l-bnf", "l.bnf", 32,
    1176. 

  1176.     { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1177. 

  1177.   },
    1178. 

  1178. /* l.bf ${disp26} */
    1179. 

  1179.   {
    1180. 

  1180.     OR1K_INSN_L_BF, "l-bf", "l.bf", 32,
    1181. 

  1181.     { 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAYED_CTI)|A(SKIP_CTI)|A(DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1182. 

  1182.   },
    1183. 

  1183. /* l.trap ${uimm16} */
    1184. 

  1184.   {
    1185. 

  1185.     OR1K_INSN_L_TRAP, "l-trap", "l.trap", 32,
    1186. 

  1186.     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1187. 

  1187.   },
    1188. 

  1188. /* l.sys ${uimm16} */
    1189. 

  1189.   {
    1190. 

  1190.     OR1K_INSN_L_SYS, "l-sys", "l.sys", 32,
    1191. 

  1191.     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1192. 

  1192.   },
    1193. 

  1193. /* l.msync */
    1194. 

  1194.   {
    1195. 

  1195.     OR1K_INSN_L_MSYNC, "l-msync", "l.msync", 32,
    1196. 

  1196.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1197. 

  1197.   },
    1198. 

  1198. /* l.psync */
    1199. 

  1199.   {
    1200. 

  1200.     OR1K_INSN_L_PSYNC, "l-psync", "l.psync", 32,
    1201. 

  1201.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1202. 

  1202.   },
    1203. 

  1203. /* l.csync */
    1204. 

  1204.   {
    1205. 

  1205.     OR1K_INSN_L_CSYNC, "l-csync", "l.csync", 32,
    1206. 

  1206.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1207. 

  1207.   },
    1208. 

  1208. /* l.rfe */
    1209. 

  1209.   {
    1210. 

  1210.     OR1K_INSN_L_RFE, "l-rfe", "l.rfe", 32,
    1211. 

  1211.     { 0|A(FORCED_CTI)|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1212. 

  1212.   },
    1213. 

  1213. /* l.nop ${uimm16} */
    1214. 

  1214.   {
    1215. 

  1215.     OR1K_INSN_L_NOP_IMM, "l-nop-imm", "l.nop", 32,
    1216. 

  1216.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1217. 

  1217.   },
    1218. 

  1218. /* l.nop */
    1219. 

  1219.   {
    1220. 

  1220.     OR1K_INSN_L_NOP, "l-nop", "l.nop", 32,
    1221. 

  1221.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1222. 

  1222.   },
    1223. 

  1223. /* l.movhi $rD,$uimm16 */
    1224. 

  1224.   {
    1225. 

  1225.     OR1K_INSN_L_MOVHI, "l-movhi", "l.movhi", 32,
    1226. 

  1226.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1227. 

  1227.   },
    1228. 

  1228. /* l.macrc $rD */
    1229. 

  1229.   {
    1230. 

  1230.     OR1K_INSN_L_MACRC, "l-macrc", "l.macrc", 32,
    1231. 

  1231.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1232. 

  1232.   },
    1233. 

  1233. /* l.mfspr $rD,$rA,${uimm16} */
    1234. 

  1234.   {
    1235. 

  1235.     OR1K_INSN_L_MFSPR, "l-mfspr", "l.mfspr", 32,
    1236. 

  1236.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1237. 

  1237.   },
    1238. 

  1238. /* l.mtspr $rA,$rB,${uimm16-split} */
    1239. 

  1239.   {
    1240. 

  1240.     OR1K_INSN_L_MTSPR, "l-mtspr", "l.mtspr", 32,
    1241. 

  1241.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1242. 

  1242.   },
    1243. 

  1243. /* l.lwz $rD,${simm16}($rA) */
    1244. 

  1244.   {
    1245. 

  1245.     OR1K_INSN_L_LWZ, "l-lwz", "l.lwz", 32,
    1246. 

  1246.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1247. 

  1247.   },
    1248. 

  1248. /* l.lws $rD,${simm16}($rA) */
    1249. 

  1249.   {
    1250. 

  1250.     OR1K_INSN_L_LWS, "l-lws", "l.lws", 32,
    1251. 

  1251.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1252. 

  1252.   },
    1253. 

  1253. /* l.lwa $rD,${simm16}($rA) */
    1254. 

  1254.   {
    1255. 

  1255.     OR1K_INSN_L_LWA, "l-lwa", "l.lwa", 32,
    1256. 

  1256.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1257. 

  1257.   },
    1258. 

  1258. /* l.lbz $rD,${simm16}($rA) */
    1259. 

  1259.   {
    1260. 

  1260.     OR1K_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
    1261. 

  1261.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1262. 

  1262.   },
    1263. 

  1263. /* l.lbs $rD,${simm16}($rA) */
    1264. 

  1264.   {
    1265. 

  1265.     OR1K_INSN_L_LBS, "l-lbs", "l.lbs", 32,
    1266. 

  1266.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1267. 

  1267.   },
    1268. 

  1268. /* l.lhz $rD,${simm16}($rA) */
    1269. 

  1269.   {
    1270. 

  1270.     OR1K_INSN_L_LHZ, "l-lhz", "l.lhz", 32,
    1271. 

  1271.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1272. 

  1272.   },
    1273. 

  1273. /* l.lhs $rD,${simm16}($rA) */
    1274. 

  1274.   {
    1275. 

  1275.     OR1K_INSN_L_LHS, "l-lhs", "l.lhs", 32,
    1276. 

  1276.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1277. 

  1277.   },
    1278. 

  1278. /* l.sw ${simm16-split}($rA),$rB */
    1279. 

  1279.   {
    1280. 

  1280.     OR1K_INSN_L_SW, "l-sw", "l.sw", 32,
    1281. 

  1281.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1282. 

  1282.   },
    1283. 

  1283. /* l.sb ${simm16-split}($rA),$rB */
    1284. 

  1284.   {
    1285. 

  1285.     OR1K_INSN_L_SB, "l-sb", "l.sb", 32,
    1286. 

  1286.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1287. 

  1287.   },
    1288. 

  1288. /* l.sh ${simm16-split}($rA),$rB */
    1289. 

  1289.   {
    1290. 

  1290.     OR1K_INSN_L_SH, "l-sh", "l.sh", 32,
    1291. 

  1291.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1292. 

  1292.   },
    1293. 

  1293. /* l.swa ${simm16-split}($rA),$rB */
    1294. 

  1294.   {
    1295. 

  1295.     OR1K_INSN_L_SWA, "l-swa", "l.swa", 32,
    1296. 

  1296.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1297. 

  1297.   },
    1298. 

  1298. /* l.sll $rD,$rA,$rB */
    1299. 

  1299.   {
    1300. 

  1300.     OR1K_INSN_L_SLL, "l-sll", "l.sll", 32,
    1301. 

  1301.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1302. 

  1302.   },
    1303. 

  1303. /* l.slli $rD,$rA,${uimm6} */
    1304. 

  1304.   {
    1305. 

  1305.     OR1K_INSN_L_SLLI, "l-slli", "l.slli", 32,
    1306. 

  1306.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1307. 

  1307.   },
    1308. 

  1308. /* l.srl $rD,$rA,$rB */
    1309. 

  1309.   {
    1310. 

  1310.     OR1K_INSN_L_SRL, "l-srl", "l.srl", 32,
    1311. 

  1311.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1312. 

  1312.   },
    1313. 

  1313. /* l.srli $rD,$rA,${uimm6} */
    1314. 

  1314.   {
    1315. 

  1315.     OR1K_INSN_L_SRLI, "l-srli", "l.srli", 32,
    1316. 

  1316.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1317. 

  1317.   },
    1318. 

  1318. /* l.sra $rD,$rA,$rB */
    1319. 

  1319.   {
    1320. 

  1320.     OR1K_INSN_L_SRA, "l-sra", "l.sra", 32,
    1321. 

  1321.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1322. 

  1322.   },
    1323. 

  1323. /* l.srai $rD,$rA,${uimm6} */
    1324. 

  1324.   {
    1325. 

  1325.     OR1K_INSN_L_SRAI, "l-srai", "l.srai", 32,
    1326. 

  1326.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1327. 

  1327.   },
    1328. 

  1328. /* l.ror $rD,$rA,$rB */
    1329. 

  1329.   {
    1330. 

  1330.     OR1K_INSN_L_ROR, "l-ror", "l.ror", 32,
    1331. 

  1331.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1332. 

  1332.   },
    1333. 

  1333. /* l.rori $rD,$rA,${uimm6} */
    1334. 

  1334.   {
    1335. 

  1335.     OR1K_INSN_L_RORI, "l-rori", "l.rori", 32,
    1336. 

  1336.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1337. 

  1337.   },
    1338. 

  1338. /* l.and $rD,$rA,$rB */
    1339. 

  1339.   {
    1340. 

  1340.     OR1K_INSN_L_AND, "l-and", "l.and", 32,
    1341. 

  1341.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1342. 

  1342.   },
    1343. 

  1343. /* l.or $rD,$rA,$rB */
    1344. 

  1344.   {
    1345. 

  1345.     OR1K_INSN_L_OR, "l-or", "l.or", 32,
    1346. 

  1346.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1347. 

  1347.   },
    1348. 

  1348. /* l.xor $rD,$rA,$rB */
    1349. 

  1349.   {
    1350. 

  1350.     OR1K_INSN_L_XOR, "l-xor", "l.xor", 32,
    1351. 

  1351.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1352. 

  1352.   },
    1353. 

  1353. /* l.add $rD,$rA,$rB */
    1354. 

  1354.   {
    1355. 

  1355.     OR1K_INSN_L_ADD, "l-add", "l.add", 32,
    1356. 

  1356.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1357. 

  1357.   },
    1358. 

  1358. /* l.sub $rD,$rA,$rB */
    1359. 

  1359.   {
    1360. 

  1360.     OR1K_INSN_L_SUB, "l-sub", "l.sub", 32,
    1361. 

  1361.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1362. 

  1362.   },
    1363. 

  1363. /* l.addc $rD,$rA,$rB */
    1364. 

  1364.   {
    1365. 

  1365.     OR1K_INSN_L_ADDC, "l-addc", "l.addc", 32,
    1366. 

  1366.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1367. 

  1367.   },
    1368. 

  1368. /* l.mul $rD,$rA,$rB */
    1369. 

  1369.   {
    1370. 

  1370.     OR1K_INSN_L_MUL, "l-mul", "l.mul", 32,
    1371. 

  1371.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1372. 

  1372.   },
    1373. 

  1373. /* l.mulu $rD,$rA,$rB */
    1374. 

  1374.   {
    1375. 

  1375.     OR1K_INSN_L_MULU, "l-mulu", "l.mulu", 32,
    1376. 

  1376.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1377. 

  1377.   },
    1378. 

  1378. /* l.div $rD,$rA,$rB */
    1379. 

  1379.   {
    1380. 

  1380.     OR1K_INSN_L_DIV, "l-div", "l.div", 32,
    1381. 

  1381.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1382. 

  1382.   },
    1383. 

  1383. /* l.divu $rD,$rA,$rB */
    1384. 

  1384.   {
    1385. 

  1385.     OR1K_INSN_L_DIVU, "l-divu", "l.divu", 32,
    1386. 

  1386.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1387. 

  1387.   },
    1388. 

  1388. /* l.ff1 $rD,$rA */
    1389. 

  1389.   {
    1390. 

  1390.     OR1K_INSN_L_FF1, "l-ff1", "l.ff1", 32,
    1391. 

  1391.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1392. 

  1392.   },
    1393. 

  1393. /* l.fl1 $rD,$rA */
    1394. 

  1394.   {
    1395. 

  1395.     OR1K_INSN_L_FL1, "l-fl1", "l.fl1", 32,
    1396. 

  1396.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1397. 

  1397.   },
    1398. 

  1398. /* l.andi $rD,$rA,$uimm16 */
    1399. 

  1399.   {
    1400. 

  1400.     OR1K_INSN_L_ANDI, "l-andi", "l.andi", 32,
    1401. 

  1401.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1402. 

  1402.   },
    1403. 

  1403. /* l.ori $rD,$rA,$uimm16 */
    1404. 

  1404.   {
    1405. 

  1405.     OR1K_INSN_L_ORI, "l-ori", "l.ori", 32,
    1406. 

  1406.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1407. 

  1407.   },
    1408. 

  1408. /* l.xori $rD,$rA,$simm16 */
    1409. 

  1409.   {
    1410. 

  1410.     OR1K_INSN_L_XORI, "l-xori", "l.xori", 32,
    1411. 

  1411.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1412. 

  1412.   },
    1413. 

  1413. /* l.addi $rD,$rA,$simm16 */
    1414. 

  1414.   {
    1415. 

  1415.     OR1K_INSN_L_ADDI, "l-addi", "l.addi", 32,
    1416. 

  1416.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1417. 

  1417.   },
    1418. 

  1418. /* l.addic $rD,$rA,$simm16 */
    1419. 

  1419.   {
    1420. 

  1420.     OR1K_INSN_L_ADDIC, "l-addic", "l.addic", 32,
    1421. 

  1421.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1422. 

  1422.   },
    1423. 

  1423. /* l.muli $rD,$rA,$simm16 */
    1424. 

  1424.   {
    1425. 

  1425.     OR1K_INSN_L_MULI, "l-muli", "l.muli", 32,
    1426. 

  1426.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1427. 

  1427.   },
    1428. 

  1428. /* l.exths $rD,$rA */
    1429. 

  1429.   {
    1430. 

  1430.     OR1K_INSN_L_EXTHS, "l-exths", "l.exths", 32,
    1431. 

  1431.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1432. 

  1432.   },
    1433. 

  1433. /* l.extbs $rD,$rA */
    1434. 

  1434.   {
    1435. 

  1435.     OR1K_INSN_L_EXTBS, "l-extbs", "l.extbs", 32,
    1436. 

  1436.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1437. 

  1437.   },
    1438. 

  1438. /* l.exthz $rD,$rA */
    1439. 

  1439.   {
    1440. 

  1440.     OR1K_INSN_L_EXTHZ, "l-exthz", "l.exthz", 32,
    1441. 

  1441.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1442. 

  1442.   },
    1443. 

  1443. /* l.extbz $rD,$rA */
    1444. 

  1444.   {
    1445. 

  1445.     OR1K_INSN_L_EXTBZ, "l-extbz", "l.extbz", 32,
    1446. 

  1446.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1447. 

  1447.   },
    1448. 

  1448. /* l.extws $rD,$rA */
    1449. 

  1449.   {
    1450. 

  1450.     OR1K_INSN_L_EXTWS, "l-extws", "l.extws", 32,
    1451. 

  1451.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1452. 

  1452.   },
    1453. 

  1453. /* l.extwz $rD,$rA */
    1454. 

  1454.   {
    1455. 

  1455.     OR1K_INSN_L_EXTWZ, "l-extwz", "l.extwz", 32,
    1456. 

  1456.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1457. 

  1457.   },
    1458. 

  1458. /* l.cmov $rD,$rA,$rB */
    1459. 

  1459.   {
    1460. 

  1460.     OR1K_INSN_L_CMOV, "l-cmov", "l.cmov", 32,
    1461. 

  1461.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1462. 

  1462.   },
    1463. 

  1463. /* l.sfgts $rA,$rB */
    1464. 

  1464.   {
    1465. 

  1465.     OR1K_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32,
    1466. 

  1466.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1467. 

  1467.   },
    1468. 

  1468. /* l.sfgtsi $rA,$simm16 */
    1469. 

  1469.   {
    1470. 

  1470.     OR1K_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32,
    1471. 

  1471.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1472. 

  1472.   },
    1473. 

  1473. /* l.sfgtu $rA,$rB */
    1474. 

  1474.   {
    1475. 

  1475.     OR1K_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32,
    1476. 

  1476.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1477. 

  1477.   },
    1478. 

  1478. /* l.sfgtui $rA,$simm16 */
    1479. 

  1479.   {
    1480. 

  1480.     OR1K_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32,
    1481. 

  1481.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1482. 

  1482.   },
    1483. 

  1483. /* l.sfges $rA,$rB */
    1484. 

  1484.   {
    1485. 

  1485.     OR1K_INSN_L_SFGES, "l-sfges", "l.sfges", 32,
    1486. 

  1486.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1487. 

  1487.   },
    1488. 

  1488. /* l.sfgesi $rA,$simm16 */
    1489. 

  1489.   {
    1490. 

  1490.     OR1K_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32,
    1491. 

  1491.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1492. 

  1492.   },
    1493. 

  1493. /* l.sfgeu $rA,$rB */
    1494. 

  1494.   {
    1495. 

  1495.     OR1K_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32,
    1496. 

  1496.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1497. 

  1497.   },
    1498. 

  1498. /* l.sfgeui $rA,$simm16 */
    1499. 

  1499.   {
    1500. 

  1500.     OR1K_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32,
    1501. 

  1501.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1502. 

  1502.   },
    1503. 

  1503. /* l.sflts $rA,$rB */
    1504. 

  1504.   {
    1505. 

  1505.     OR1K_INSN_L_SFLTS, "l-sflts", "l.sflts", 32,
    1506. 

  1506.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1507. 

  1507.   },
    1508. 

  1508. /* l.sfltsi $rA,$simm16 */
    1509. 

  1509.   {
    1510. 

  1510.     OR1K_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32,
    1511. 

  1511.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1512. 

  1512.   },
    1513. 

  1513. /* l.sfltu $rA,$rB */
    1514. 

  1514.   {
    1515. 

  1515.     OR1K_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32,
    1516. 

  1516.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1517. 

  1517.   },
    1518. 

  1518. /* l.sfltui $rA,$simm16 */
    1519. 

  1519.   {
    1520. 

  1520.     OR1K_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32,
    1521. 

  1521.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1522. 

  1522.   },
    1523. 

  1523. /* l.sfles $rA,$rB */
    1524. 

  1524.   {
    1525. 

  1525.     OR1K_INSN_L_SFLES, "l-sfles", "l.sfles", 32,
    1526. 

  1526.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1527. 

  1527.   },
    1528. 

  1528. /* l.sflesi $rA,$simm16 */
    1529. 

  1529.   {
    1530. 

  1530.     OR1K_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32,
    1531. 

  1531.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1532. 

  1532.   },
    1533. 

  1533. /* l.sfleu $rA,$rB */
    1534. 

  1534.   {
    1535. 

  1535.     OR1K_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32,
    1536. 

  1536.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1537. 

  1537.   },
    1538. 

  1538. /* l.sfleui $rA,$simm16 */
    1539. 

  1539.   {
    1540. 

  1540.     OR1K_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32,
    1541. 

  1541.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1542. 

  1542.   },
    1543. 

  1543. /* l.sfeq $rA,$rB */
    1544. 

  1544.   {
    1545. 

  1545.     OR1K_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32,
    1546. 

  1546.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1547. 

  1547.   },
    1548. 

  1548. /* l.sfeqi $rA,$simm16 */
    1549. 

  1549.   {
    1550. 

  1550.     OR1K_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32,
    1551. 

  1551.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1552. 

  1552.   },
    1553. 

  1553. /* l.sfne $rA,$rB */
    1554. 

  1554.   {
    1555. 

  1555.     OR1K_INSN_L_SFNE, "l-sfne", "l.sfne", 32,
    1556. 

  1556.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1557. 

  1557.   },
    1558. 

  1558. /* l.sfnei $rA,$simm16 */
    1559. 

  1559.   {
    1560. 

  1560.     OR1K_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32,
    1561. 

  1561.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1562. 

  1562.   },
    1563. 

  1563. /* l.mac $rA,$rB */
    1564. 

  1564.   {
    1565. 

  1565.     OR1K_INSN_L_MAC, "l-mac", "l.mac", 32,
    1566. 

  1566.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1567. 

  1567.   },
    1568. 

  1568. /* l.msb $rA,$rB */
    1569. 

  1569.   {
    1570. 

  1570.     OR1K_INSN_L_MSB, "l-msb", "l.msb", 32,
    1571. 

  1571.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1572. 

  1572.   },
    1573. 

  1573. /* l.maci $rA,${simm16} */
    1574. 

  1574.   {
    1575. 

  1575.     OR1K_INSN_L_MACI, "l-maci", "l.maci", 32,
    1576. 

  1576.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1577. 

  1577.   },
    1578. 

  1578. /* l.cust1 */
    1579. 

  1579.   {
    1580. 

  1580.     OR1K_INSN_L_CUST1, "l-cust1", "l.cust1", 32,
    1581. 

  1581.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1582. 

  1582.   },
    1583. 

  1583. /* l.cust2 */
    1584. 

  1584.   {
    1585. 

  1585.     OR1K_INSN_L_CUST2, "l-cust2", "l.cust2", 32,
    1586. 

  1586.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1587. 

  1587.   },
    1588. 

  1588. /* l.cust3 */
    1589. 

  1589.   {
    1590. 

  1590.     OR1K_INSN_L_CUST3, "l-cust3", "l.cust3", 32,
    1591. 

  1591.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1592. 

  1592.   },
    1593. 

  1593. /* l.cust4 */
    1594. 

  1594.   {
    1595. 

  1595.     OR1K_INSN_L_CUST4, "l-cust4", "l.cust4", 32,
    1596. 

  1596.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1597. 

  1597.   },
    1598. 

  1598. /* l.cust5 */
    1599. 

  1599.   {
    1600. 

  1600.     OR1K_INSN_L_CUST5, "l-cust5", "l.cust5", 32,
    1601. 

  1601.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1602. 

  1602.   },
    1603. 

  1603. /* l.cust6 */
    1604. 

  1604.   {
    1605. 

  1605.     OR1K_INSN_L_CUST6, "l-cust6", "l.cust6", 32,
    1606. 

  1606.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1607. 

  1607.   },
    1608. 

  1608. /* l.cust7 */
    1609. 

  1609.   {
    1610. 

  1610.     OR1K_INSN_L_CUST7, "l-cust7", "l.cust7", 32,
    1611. 

  1611.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1612. 

  1612.   },
    1613. 

  1613. /* l.cust8 */
    1614. 

  1614.   {
    1615. 

  1615.     OR1K_INSN_L_CUST8, "l-cust8", "l.cust8", 32,
    1616. 

  1616.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1617. 

  1617.   },
    1618. 

  1618. /* lf.add.s $rDSF,$rASF,$rBSF */
    1619. 

  1619.   {
    1620. 

  1620.     OR1K_INSN_LF_ADD_S, "lf-add-s", "lf.add.s", 32,
    1621. 

  1621.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1622. 

  1622.   },
    1623. 

  1623. /* lf.add.d $rDDF,$rADF,$rBDF */
    1624. 

  1624.   {
    1625. 

  1625.     OR1K_INSN_LF_ADD_D, "lf-add-d", "lf.add.d", 32,
    1626. 

  1626.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1627. 

  1627.   },
    1628. 

  1628. /* lf.sub.s $rDSF,$rASF,$rBSF */
    1629. 

  1629.   {
    1630. 

  1630.     OR1K_INSN_LF_SUB_S, "lf-sub-s", "lf.sub.s", 32,
    1631. 

  1631.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1632. 

  1632.   },
    1633. 

  1633. /* lf.sub.d $rDDF,$rADF,$rBDF */
    1634. 

  1634.   {
    1635. 

  1635.     OR1K_INSN_LF_SUB_D, "lf-sub-d", "lf.sub.d", 32,
    1636. 

  1636.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1637. 

  1637.   },
    1638. 

  1638. /* lf.mul.s $rDSF,$rASF,$rBSF */
    1639. 

  1639.   {
    1640. 

  1640.     OR1K_INSN_LF_MUL_S, "lf-mul-s", "lf.mul.s", 32,
    1641. 

  1641.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1642. 

  1642.   },
    1643. 

  1643. /* lf.mul.d $rDDF,$rADF,$rBDF */
    1644. 

  1644.   {
    1645. 

  1645.     OR1K_INSN_LF_MUL_D, "lf-mul-d", "lf.mul.d", 32,
    1646. 

  1646.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1647. 

  1647.   },
    1648. 

  1648. /* lf.div.s $rDSF,$rASF,$rBSF */
    1649. 

  1649.   {
    1650. 

  1650.     OR1K_INSN_LF_DIV_S, "lf-div-s", "lf.div.s", 32,
    1651. 

  1651.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1652. 

  1652.   },
    1653. 

  1653. /* lf.div.d $rDDF,$rADF,$rBDF */
    1654. 

  1654.   {
    1655. 

  1655.     OR1K_INSN_LF_DIV_D, "lf-div-d", "lf.div.d", 32,
    1656. 

  1656.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1657. 

  1657.   },
    1658. 

  1658. /* lf.rem.s $rDSF,$rASF,$rBSF */
    1659. 

  1659.   {
    1660. 

  1660.     OR1K_INSN_LF_REM_S, "lf-rem-s", "lf.rem.s", 32,
    1661. 

  1661.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1662. 

  1662.   },
    1663. 

  1663. /* lf.rem.d $rDDF,$rADF,$rBDF */
    1664. 

  1664.   {
    1665. 

  1665.     OR1K_INSN_LF_REM_D, "lf-rem-d", "lf.rem.d", 32,
    1666. 

  1666.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1667. 

  1667.   },
    1668. 

  1668. /* lf.itof.s $rDSF,$rA */
    1669. 

  1669.   {
    1670. 

  1670.     OR1K_INSN_LF_ITOF_S, "lf-itof-s", "lf.itof.s", 32,
    1671. 

  1671.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1672. 

  1672.   },
    1673. 

  1673. /* lf.itof.d $rDSF,$rA */
    1674. 

  1674.   {
    1675. 

  1675.     OR1K_INSN_LF_ITOF_D, "lf-itof-d", "lf.itof.d", 32,
    1676. 

  1676.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1677. 

  1677.   },
    1678. 

  1678. /* lf.ftoi.s $rD,$rASF */
    1679. 

  1679.   {
    1680. 

  1680.     OR1K_INSN_LF_FTOI_S, "lf-ftoi-s", "lf.ftoi.s", 32,
    1681. 

  1681.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1682. 

  1682.   },
    1683. 

  1683. /* lf.ftoi.d $rD,$rADF */
    1684. 

  1684.   {
    1685. 

  1685.     OR1K_INSN_LF_FTOI_D, "lf-ftoi-d", "lf.ftoi.d", 32,
    1686. 

  1686.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1687. 

  1687.   },
    1688. 

  1688. /* lf.sfeq.s $rASF,$rBSF */
    1689. 

  1689.   {
    1690. 

  1690.     OR1K_INSN_LF_EQ_S, "lf-eq-s", "lf.sfeq.s", 32,
    1691. 

  1691.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1692. 

  1692.   },
    1693. 

  1693. /* lf.sfeq.d $rASF,$rBSF */
    1694. 

  1694.   {
    1695. 

  1695.     OR1K_INSN_LF_EQ_D, "lf-eq-d", "lf.sfeq.d", 32,
    1696. 

  1696.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1697. 

  1697.   },
    1698. 

  1698. /* lf.sfne.s $rASF,$rBSF */
    1699. 

  1699.   {
    1700. 

  1700.     OR1K_INSN_LF_NE_S, "lf-ne-s", "lf.sfne.s", 32,
    1701. 

  1701.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1702. 

  1702.   },
    1703. 

  1703. /* lf.sfne.d $rASF,$rBSF */
    1704. 

  1704.   {
    1705. 

  1705.     OR1K_INSN_LF_NE_D, "lf-ne-d", "lf.sfne.d", 32,
    1706. 

  1706.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1707. 

  1707.   },
    1708. 

  1708. /* lf.sfge.s $rASF,$rBSF */
    1709. 

  1709.   {
    1710. 

  1710.     OR1K_INSN_LF_GE_S, "lf-ge-s", "lf.sfge.s", 32,
    1711. 

  1711.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1712. 

  1712.   },
    1713. 

  1713. /* lf.sfge.d $rASF,$rBSF */
    1714. 

  1714.   {
    1715. 

  1715.     OR1K_INSN_LF_GE_D, "lf-ge-d", "lf.sfge.d", 32,
    1716. 

  1716.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1717. 

  1717.   },
    1718. 

  1718. /* lf.sfgt.s $rASF,$rBSF */
    1719. 

  1719.   {
    1720. 

  1720.     OR1K_INSN_LF_GT_S, "lf-gt-s", "lf.sfgt.s", 32,
    1721. 

  1721.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1722. 

  1722.   },
    1723. 

  1723. /* lf.sfgt.d $rASF,$rBSF */
    1724. 

  1724.   {
    1725. 

  1725.     OR1K_INSN_LF_GT_D, "lf-gt-d", "lf.sfgt.d", 32,
    1726. 

  1726.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1727. 

  1727.   },
    1728. 

  1728. /* lf.sflt.s $rASF,$rBSF */
    1729. 

  1729.   {
    1730. 

  1730.     OR1K_INSN_LF_LT_S, "lf-lt-s", "lf.sflt.s", 32,
    1731. 

  1731.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1732. 

  1732.   },
    1733. 

  1733. /* lf.sflt.d $rASF,$rBSF */
    1734. 

  1734.   {
    1735. 

  1735.     OR1K_INSN_LF_LT_D, "lf-lt-d", "lf.sflt.d", 32,
    1736. 

  1736.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1737. 

  1737.   },
    1738. 

  1738. /* lf.sfle.s $rASF,$rBSF */
    1739. 

  1739.   {
    1740. 

  1740.     OR1K_INSN_LF_LE_S, "lf-le-s", "lf.sfle.s", 32,
    1741. 

  1741.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1742. 

  1742.   },
    1743. 

  1743. /* lf.sfle.d $rASF,$rBSF */
    1744. 

  1744.   {
    1745. 

  1745.     OR1K_INSN_LF_LE_D, "lf-le-d", "lf.sfle.d", 32,
    1746. 

  1746.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1747. 

  1747.   },
    1748. 

  1748. /* lf.madd.s $rDSF,$rASF,$rBSF */
    1749. 

  1749.   {
    1750. 

  1750.     OR1K_INSN_LF_MADD_S, "lf-madd-s", "lf.madd.s", 32,
    1751. 

  1751.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1752. 

  1752.   },
    1753. 

  1753. /* lf.madd.d $rDDF,$rADF,$rBDF */
    1754. 

  1754.   {
    1755. 

  1755.     OR1K_INSN_LF_MADD_D, "lf-madd-d", "lf.madd.d", 32,
    1756. 

  1756.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1757. 

  1757.   },
    1758. 

  1758. /* lf.cust1.s $rASF,$rBSF */
    1759. 

  1759.   {
    1760. 

  1760.     OR1K_INSN_LF_CUST1_S, "lf-cust1-s", "lf.cust1.s", 32,
    1761. 

  1761.     { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1762. 

  1762.   },
    1763. 

  1763. /* lf.cust1.d */
    1764. 

  1764.   {
    1765. 

  1765.     OR1K_INSN_LF_CUST1_D, "lf-cust1-d", "lf.cust1.d", 32,
    1766. 

  1766.     { 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
    1767. 

  1767.   },
    1768. 

  1768. };
    1769. 

  1769. 

  1770. #undef OP
    1771. 

  1771. #undef A
    1772. 

  1772. 

  1773. /* Initialize anything needed to be done once, before any cpu_open call.  */
    1774. 

  1774. 

  1775. static void
    1776. 

  1776. init_tables (void)
    1777. 

  1777. {
    1778. 

  1778. }
    1779. 

  1779. 

  1780. static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
    1781. 

  1781. static void build_hw_table      (CGEN_CPU_TABLE *);
    1782. 

  1782. static void build_ifield_table  (CGEN_CPU_TABLE *);
    1783. 

  1783. static void build_operand_table (CGEN_CPU_TABLE *);
    1784. 

  1784. static void build_insn_table    (CGEN_CPU_TABLE *);
    1785. 

  1785. static void or1k_cgen_rebuild_tables (CGEN_CPU_TABLE *);
    1786. 

  1786. 

  1787. /* Subroutine of or1k_cgen_cpu_open to look up a mach via its bfd name.  */
    1788. 

  1788. 

  1789. static const CGEN_MACH *
    1790. 

  1790. lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
    1791. 

  1791. {
    1792. 

  1792.   while (table->name)
    1793. 

  1793.     {
    1794. 

  1794.       if (strcmp (name, table->bfd_name) == 0)
    1795. 

  1795. 	return table;
    1796. 

  1796.       ++table;
    1797. 

  1797.     }
    1798. 

  1798.   abort ();
    1799. 

  1799. }
    1800. 

  1800. 

  1801. /* Subroutine of or1k_cgen_cpu_open to build the hardware table.  */
    1802. 

  1802. 

  1803. static void
    1804. 

  1804. build_hw_table (CGEN_CPU_TABLE *cd)
    1805. 

  1805. {
    1806. 

  1806.   int i;
    1807. 

  1807.   int machs = cd->machs;
    1808. 

  1808.   const CGEN_HW_ENTRY *init = & or1k_cgen_hw_table[0];
    1809. 

  1809.   /* MAX_HW is only an upper bound on the number of selected entries.
    1810. 

  1810.      However each entry is indexed by it's enum so there can be holes in
    1811. 

  1811.      the table.  */
    1812. 

  1812.   const CGEN_HW_ENTRY **selected =
    1813. 

  1813.     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
    1814. 

  1814. 

  1815.   cd->hw_table.init_entries = init;
    1816. 

  1816.   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
    1817. 

  1817.   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
    1818. 

  1818.   /* ??? For now we just use machs to determine which ones we want.  */
    1819. 

  1819.   for (i = 0; init[i].name != NULL; ++i)
    1820. 

  1820.     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
    1821. 

  1821. 	& machs)
    1822. 

  1822.       selected[init[i].type] = &init[i];
    1823. 

  1823.   cd->hw_table.entries = selected;
    1824. 

  1824.   cd->hw_table.num_entries = MAX_HW;
    1825. 

  1825. }
    1826. 

  1826. 

  1827. /* Subroutine of or1k_cgen_cpu_open to build the hardware table.  */
    1828. 

  1828. 

  1829. static void
    1830. 

  1830. build_ifield_table (CGEN_CPU_TABLE *cd)
    1831. 

  1831. {
    1832. 

  1832.   cd->ifld_table = & or1k_cgen_ifld_table[0];
    1833. 

  1833. }
    1834. 

  1834. 

  1835. /* Subroutine of or1k_cgen_cpu_open to build the hardware table.  */
    1836. 

  1836. 

  1837. static void
    1838. 

  1838. build_operand_table (CGEN_CPU_TABLE *cd)
    1839. 

  1839. {
    1840. 

  1840.   int i;
    1841. 

  1841.   int machs = cd->machs;
    1842. 

  1842.   const CGEN_OPERAND *init = & or1k_cgen_operand_table[0];
    1843. 

  1843.   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
    1844. 

  1844.      However each entry is indexed by it's enum so there can be holes in
    1845. 

  1845.      the table.  */
    1846. 

  1846.   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
    1847. 

  1847. 

  1848.   cd->operand_table.init_entries = init;
    1849. 

  1849.   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
    1850. 

  1850.   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
    1851. 

  1851.   /* ??? For now we just use mach to determine which ones we want.  */
    1852. 

  1852.   for (i = 0; init[i].name != NULL; ++i)
    1853. 

  1853.     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
    1854. 

  1854. 	& machs)
    1855. 

  1855.       selected[init[i].type] = &init[i];
    1856. 

  1856.   cd->operand_table.entries = selected;
    1857. 

  1857.   cd->operand_table.num_entries = MAX_OPERANDS;
    1858. 

  1858. }
    1859. 

  1859. 

  1860. /* Subroutine of or1k_cgen_cpu_open to build the hardware table.
    1861. 

  1861.    ??? This could leave out insns not supported by the specified mach/isa,
    1862. 

  1862.    but that would cause errors like "foo only supported by bar" to become
    1863. 

  1863.    "unknown insn", so for now we include all insns and require the app to
    1864. 

  1864.    do the checking later.
    1865. 

  1865.    ??? On the other hand, parsing of such insns may require their hardware or
    1866. 

  1866.    operand elements to be in the table [which they mightn't be].  */
    1867. 

  1867. 

  1868. static void
    1869. 

  1869. build_insn_table (CGEN_CPU_TABLE *cd)
    1870. 

  1870. {
    1871. 

  1871.   int i;
    1872. 

  1872.   const CGEN_IBASE *ib = & or1k_cgen_insn_table[0];
    1873. 

  1873.   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
    1874. 

  1874. 

  1875.   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
    1876. 

  1876.   for (i = 0; i < MAX_INSNS; ++i)
    1877. 

  1877.     insns[i].base = &ib[i];
    1878. 

  1878.   cd->insn_table.init_entries = insns;
    1879. 

  1879.   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
    1880. 

  1880.   cd->insn_table.num_init_entries = MAX_INSNS;
    1881. 

  1881. }
    1882. 

  1882. 

  1883. /* Subroutine of or1k_cgen_cpu_open to rebuild the tables.  */
    1884. 

  1884. 

  1885. static void
    1886. 

  1886. or1k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
    1887. 

  1887. {
    1888. 

  1888.   int i;
    1889. 

  1889.   CGEN_BITSET *isas = cd->isas;
    1890. 

  1890.   unsigned int machs = cd->machs;
    1891. 

  1891. 

  1892.   cd->int_insn_p = CGEN_INT_INSN_P;
    1893. 

  1893. 

  1894.   /* Data derived from the isa spec.  */
    1895. 

  1895. #define UNSET (CGEN_SIZE_UNKNOWN + 1)
    1896. 

  1896.   cd->default_insn_bitsize = UNSET;
    1897. 

  1897.   cd->base_insn_bitsize = UNSET;
    1898. 

  1898.   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
    1899. 

  1899.   cd->max_insn_bitsize = 0;
    1900. 

  1900.   for (i = 0; i < MAX_ISAS; ++i)
    1901. 

  1901.     if (cgen_bitset_contains (isas, i))
    1902. 

  1902.       {
    1903. 

  1903. 	const CGEN_ISA *isa = & or1k_cgen_isa_table[i];
    1904. 

  1904. 

  1905. 	/* Default insn sizes of all selected isas must be
    1906. 

  1906. 	   equal or we set the result to 0, meaning "unknown".  */
    1907. 

  1907. 	if (cd->default_insn_bitsize == UNSET)
    1908. 

  1908. 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
    1909. 

  1909. 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
    1910. 

  1910. 	  ; /* This is ok.  */
    1911. 

  1911. 	else
    1912. 

  1912. 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
    1913. 

  1913. 

  1914. 	/* Base insn sizes of all selected isas must be equal
    1915. 

  1915. 	   or we set the result to 0, meaning "unknown".  */
    1916. 

  1916. 	if (cd->base_insn_bitsize == UNSET)
    1917. 

  1917. 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
    1918. 

  1918. 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
    1919. 

  1919. 	  ; /* This is ok.  */
    1920. 

  1920. 	else
    1921. 

  1921. 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
    1922. 

  1922. 

  1923. 	/* Set min,max insn sizes.  */
    1924. 

  1924. 	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
    1925. 

  1925. 	  cd->min_insn_bitsize = isa->min_insn_bitsize;
    1926. 

  1926. 	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
    1927. 

  1927. 	  cd->max_insn_bitsize = isa->max_insn_bitsize;
    1928. 

  1928.       }
    1929. 

  1929. 

  1930.   /* Data derived from the mach spec.  */
    1931. 

  1931.   for (i = 0; i < MAX_MACHS; ++i)
    1932. 

  1932.     if (((1 << i) & machs) != 0)
    1933. 

  1933.       {
    1934. 

  1934. 	const CGEN_MACH *mach = & or1k_cgen_mach_table[i];
    1935. 

  1935. 

  1936. 	if (mach->insn_chunk_bitsize != 0)
    1937. 

  1937. 	{
    1938. 

  1938. 	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
    1939. 

  1939. 	    {
    1940. 

  1940. 	      fprintf (stderr, "or1k_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
    1941. 

  1941. 		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
    1942. 

  1942. 	      abort ();
    1943. 

  1943. 	    }
    1944. 

  1944. 

  1945.  	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
    1946. 

  1946. 	}
    1947. 

  1947.       }
    1948. 

  1948. 

  1949.   /* Determine which hw elements are used by MACH.  */
    1950. 

  1950.   build_hw_table (cd);
    1951. 

  1951. 

  1952.   /* Build the ifield table.  */
    1953. 

  1953.   build_ifield_table (cd);
    1954. 

  1954. 

  1955.   /* Determine which operands are used by MACH/ISA.  */
    1956. 

  1956.   build_operand_table (cd);
    1957. 

  1957. 

  1958.   /* Build the instruction table.  */
    1959. 

  1959.   build_insn_table (cd);
    1960. 

  1960. }
    1961. 

  1961. 

  1962. /* Initialize a cpu table and return a descriptor.
    1963. 

  1963.    It's much like opening a file, and must be the first function called.
    1964. 

  1964.    The arguments are a set of (type/value) pairs, terminated with
    1965. 

  1965.    CGEN_CPU_OPEN_END.
    1966. 

  1966. 

  1967.    Currently supported values:
    1968. 

  1968.    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
    1969. 

  1969.    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
    1970. 

  1970.    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
    1971. 

  1971.    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
    1972. 

  1972.    CGEN_CPU_OPEN_END:     terminates arguments
    1973. 

  1973. 

  1974.    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
    1975. 

  1975.    precluded.  */
    1976. 

  1976. 

  1977. CGEN_CPU_DESC
    1978. 

  1978. or1k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
    1979. 

  1979. {
    1980. 

  1980.   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
    1981. 

  1981.   static int init_p;
    1982. 

  1982.   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
    1983. 

  1983.   unsigned int machs = 0; /* 0 = "unspecified" */
    1984. 

  1984.   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
    1985. 

  1985.   va_list ap;
    1986. 

  1986. 

  1987.   if (! init_p)
    1988. 

  1988.     {
    1989. 

  1989.       init_tables ();
    1990. 

  1990.       init_p = 1;
    1991. 

  1991.     }
    1992. 

  1992. 

  1993.   memset (cd, 0, sizeof (*cd));
    1994. 

  1994. 

  1995.   va_start (ap, arg_type);
    1996. 

  1996.   while (arg_type != CGEN_CPU_OPEN_END)
    1997. 

  1997.     {
    1998. 

  1998.       switch (arg_type)
    1999. 

  1999. 	{
    2000. 

  2000. 	case CGEN_CPU_OPEN_ISAS :
    2001. 

  2001. 	  isas = va_arg (ap, CGEN_BITSET *);
    2002. 

  2002. 	  break;
    2003. 

  2003. 	case CGEN_CPU_OPEN_MACHS :
    2004. 

  2004. 	  machs = va_arg (ap, unsigned int);
    2005. 

  2005. 	  break;
    2006. 

  2006. 	case CGEN_CPU_OPEN_BFDMACH :
    2007. 

  2007. 	  {
    2008. 

  2008. 	    const char *name = va_arg (ap, const char *);
    2009. 

  2009. 	    const CGEN_MACH *mach =
    2010. 

  2010. 	      lookup_mach_via_bfd_name (or1k_cgen_mach_table, name);
    2011. 

  2011. 

  2012. 	    machs |= 1 << mach->num;
    2013. 

  2013. 	    break;
    2014. 

  2014. 	  }
    2015. 

  2015. 	case CGEN_CPU_OPEN_ENDIAN :
    2016. 

  2016. 	  endian = va_arg (ap, enum cgen_endian);
    2017. 

  2017. 	  break;
    2018. 

  2018. 	default :
    2019. 

  2019. 	  fprintf (stderr, "or1k_cgen_cpu_open: unsupported argument `%d'\n",
    2020. 

  2020. 		   arg_type);
    2021. 

  2021. 	  abort (); /* ??? return NULL? */
    2022. 

  2022. 	}
    2023. 

  2023.       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
    2024. 

  2024.     }
    2025. 

  2025.   va_end (ap);
    2026. 

  2026. 

  2027.   /* Mach unspecified means "all".  */
    2028. 

  2028.   if (machs == 0)
    2029. 

  2029.     machs = (1 << MAX_MACHS) - 1;
    2030. 

  2030.   /* Base mach is always selected.  */
    2031. 

  2031.   machs |= 1;
    2032. 

  2032.   if (endian == CGEN_ENDIAN_UNKNOWN)
    2033. 

  2033.     {
    2034. 

  2034.       /* ??? If target has only one, could have a default.  */
    2035. 

  2035.       fprintf (stderr, "or1k_cgen_cpu_open: no endianness specified\n");
    2036. 

  2036.       abort ();
    2037. 

  2037.     }
    2038. 

  2038. 

  2039.   cd->isas = cgen_bitset_copy (isas);
    2040. 

  2040.   cd->machs = machs;
    2041. 

  2041.   cd->endian = endian;
    2042. 

  2042.   /* FIXME: for the sparc case we can determine insn-endianness statically.
    2043. 

  2043.      The worry here is where both data and insn endian can be independently
    2044. 

  2044.      chosen, in which case this function will need another argument.
    2045. 

  2045.      Actually, will want to allow for more arguments in the future anyway.  */
    2046. 

  2046.   cd->insn_endian = endian;
    2047. 

  2047. 

  2048.   /* Table (re)builder.  */
    2049. 

  2049.   cd->rebuild_tables = or1k_cgen_rebuild_tables;
    2050. 

  2050.   or1k_cgen_rebuild_tables (cd);
    2051. 

  2051. 

  2052.   /* Default to not allowing signed overflow.  */
    2053. 

  2053.   cd->signed_overflow_ok_p = 0;
    2054. 

  2054. 

  2055.   return (CGEN_CPU_DESC) cd;
    2056. 

  2056. }
    2057. 

  2057. 

  2058. /* Cover fn to or1k_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
    2059. 

  2059.    MACH_NAME is the bfd name of the mach.  */
    2060. 

  2060. 

  2061. CGEN_CPU_DESC
    2062. 

  2062. or1k_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
    2063. 

  2063. {
    2064. 

  2064.   return or1k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
    2065. 

  2065. 			       CGEN_CPU_OPEN_ENDIAN, endian,
    2066. 

  2066. 			       CGEN_CPU_OPEN_END);
    2067. 

  2067. }
    2068. 

  2068. 

  2069. /* Close a cpu table.
    2070. 

  2070.    ??? This can live in a machine independent file, but there's currently
    2071. 

  2071.    no place to put this file (there's no libcgen).  libopcodes is the wrong
    2072. 

  2072.    place as some simulator ports use this but they don't use libopcodes.  */
    2073. 

  2073. 

  2074. void
    2075. 

  2075. or1k_cgen_cpu_close (CGEN_CPU_DESC cd)
    2076. 

  2076. {
    2077. 

  2077.   unsigned int i;
    2078. 

  2078.   const CGEN_INSN *insns;
    2079. 

  2079. 

  2080.   if (cd->macro_insn_table.init_entries)
    2081. 

  2081.     {
    2082. 

  2082.       insns = cd->macro_insn_table.init_entries;
    2083. 

  2083.       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
    2084. 

  2084. 	if (CGEN_INSN_RX ((insns)))
    2085. 

  2085. 	  regfree (CGEN_INSN_RX (insns));
    2086. 

  2086.     }
    2087. 

  2087. 

  2088.   if (cd->insn_table.init_entries)
    2089. 

  2089.     {
    2090. 

  2090.       insns = cd->insn_table.init_entries;
    2091. 

  2091.       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
    2092. 

  2092. 	if (CGEN_INSN_RX (insns))
    2093. 

  2093. 	  regfree (CGEN_INSN_RX (insns));
    2094. 

  2094.     }
    2095. 

  2095. 

  2096.   if (cd->macro_insn_table.init_entries)
    2097. 

  2097.     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
    2098. 

  2098. 

  2099.   if (cd->insn_table.init_entries)
    2100. 

  2100.     free ((CGEN_INSN *) cd->insn_table.init_entries);
    2101. 

  2101. 

  2102.   if (cd->hw_table.entries)
    2103. 

  2103.     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
    2104. 

  2104. 

  2105.   if (cd->operand_table.entries)
    2106. 

  2106.     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
    2107. 

  2107. 

  2108.   free (cd);
    2109. 

  2109. }
    2110. 

  2110. 

  2111.