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m68hc11-opc.c

m68hc11-opc.c 118 KB
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
  1. /* m68hc11-opc.c -- Motorola 68HC11, 68HC12, 9S12X and XGATE opcode list
    2. 

  2.    Copyright (C) 1999-2015 Free Software Foundation, Inc.
    3. 

  3.    Written by Stephane Carrez (stcarrez@nerim.fr)
    4. 

  4.    XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk)
    5. 

  5.    Note: min/max cycles not updated for S12X opcodes.
    6. 

  6. 

  7.    This file is part of the GNU opcodes library.
    8. 

  8. 

  9.    This library is free software; you can redistribute it and/or modify
    10. 

  10.    it under the terms of the GNU General Public License as published by
    11. 

  11.    the Free Software Foundation; either version 3, or (at your option)
    12. 

  12.    any later version.
    13. 

  13. 

  14.    It is distributed in the hope that it will be useful, but WITHOUT
    15. 

  15.    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
    16. 

  16.    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
    17. 

  17.    License for more details.
    18. 

  18. 

  19.    You should have received a copy of the GNU General Public License
    20. 

  20.    along with this file; see the file COPYING.  If not, write to the
    21. 

  21.    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
    22. 

  22.    MA 02110-1301, USA.  */
    23. 

  23. 

  24. #include <stdio.h>
    25. 

  25. #include "ansidecl.h"
    26. 

  26. #include "opcode/m68hc11.h"
    27. 

  27. 

  28. #define TABLE_SIZE(X)       (sizeof(X) / sizeof(X[0]))
    29. 

  29. 

  30. /* Combination of CCR flags.  */
    31. 

  31. #define M6811_ZC_BIT    M6811_Z_BIT|M6811_C_BIT
    32. 

  32. #define M6811_NZ_BIT    M6811_N_BIT|M6811_Z_BIT
    33. 

  33. #define M6811_NZV_BIT   M6811_N_BIT|M6811_Z_BIT|M6811_V_BIT
    34. 

  34. #define M6811_NZC_BIT   M6811_N_BIT|M6811_Z_BIT|M6811_C_BIT
    35. 

  35. #define M6811_NVC_BIT   M6811_N_BIT|M6811_V_BIT|M6811_C_BIT
    36. 

  36. #define M6811_ZVC_BIT   M6811_Z_BIT|M6811_V_BIT|M6811_C_BIT
    37. 

  37. #define M6811_NZVC_BIT  M6811_ZVC_BIT|M6811_N_BIT
    38. 

  38. #define M6811_HNZVC_BIT M6811_NZVC_BIT|M6811_H_BIT
    39. 

  39. #define M6811_HNVC_BIT  M6811_NVC_BIT|M6811_H_BIT
    40. 

  40. #define M6811_VC_BIT    M6811_V_BIT|M6811_C_BIT
    41. 

  41. 

  42. /* Flags when the insn only changes some CCR flags.  */
    43. 

  43. #define CHG_NONE        0,0,0
    44. 

  44. #define CHG_Z           0,0,M6811_Z_BIT
    45. 

  45. #define CHG_C           0,0,M6811_C_BIT
    46. 

  46. #define CHG_ZVC         0,0,M6811_ZVC_BIT
    47. 

  47. #define CHG_NZC         0,0,M6811_NZC_BIT
    48. 

  48. #define CHG_NZV         0,0,M6811_NZV_BIT
    49. 

  49. #define CHG_NZVC        0,0,M6811_NZVC_BIT
    50. 

  50. #define CHG_HNZVC       0,0,M6811_HNZVC_BIT
    51. 

  51. #define CHG_ALL         0,0,0xff
    52. 

  52. 

  53. /* The insn clears and changes some flags.  */
    54. 

  54. #define CLR_I           0,M6811_I_BIT,0
    55. 

  55. #define CLR_C           0,M6811_C_BIT,0
    56. 

  56. #define CLR_V           0,M6811_V_BIT,0
    57. 

  57. #define CLR_V_CHG_ZC    0,M6811_V_BIT,M6811_ZC_BIT
    58. 

  58. #define CLR_V_CHG_NZ    0,M6811_V_BIT,M6811_NZ_BIT
    59. 

  59. #define CLR_V_CHG_ZVC   0,M6811_V_BIT,M6811_ZVC_BIT
    60. 

  60. #define CLR_N_CHG_ZVC   0,M6811_N_BIT,M6811_ZVC_BIT /* Used by lsr */
    61. 

  61. #define CLR_VC_CHG_NZ   0,M6811_VC_BIT,M6811_NZ_BIT
    62. 

  62. 

  63. /* The insn sets some flags.  */
    64. 

  64. #define SET_I           M6811_I_BIT,0,0
    65. 

  65. #define SET_C           M6811_C_BIT,0,0
    66. 

  66. #define SET_V           M6811_V_BIT,0,0
    67. 

  67. #define SET_Z_CLR_NVC   M6811_Z_BIT,M6811_NVC_BIT,0
    68. 

  68. #define SET_C_CLR_V_CHG_NZ M6811_C_BIT,M6811_V_BIT,M6811_NZ_BIT
    69. 

  69. #define SET_Z_CHG_HNVC  M6811_Z_BIT,0,M6811_HNVC_BIT
    70. 

  70. 

  71. #define _M 0xff
    72. 

  72. #define OP_NONE         M6811_OP_NONE
    73. 

  73. #define OP_PAGE2        M6811_OP_PAGE2
    74. 

  74. #define OP_PAGE3        M6811_OP_PAGE3
    75. 

  75. #define OP_PAGE4        M6811_OP_PAGE4
    76. 

  76. #define OP_IMM8         M6811_OP_IMM8
    77. 

  77. #define OP_IMM16        M6811_OP_IMM16
    78. 

  78. #define OP_IX           M6811_OP_IX
    79. 

  79. #define OP_IY           M6811_OP_IY
    80. 

  80. #define OP_IND16        M6811_OP_IND16
    81. 

  81. #define OP_PAGE         M6812_OP_PAGE
    82. 

  82. #define OP_IDX          M6812_OP_IDX
    83. 

  83. #define OP_IDX_1        M6812_OP_IDX_1
    84. 

  84. #define OP_IDX_2        M6812_OP_IDX_2
    85. 

  85. #define OP_D_IDX        M6812_OP_D_IDX
    86. 

  86. #define OP_D_IDX_2      M6812_OP_D_IDX_2
    87. 

  87. #define OP_DIRECT       M6811_OP_DIRECT
    88. 

  88. #define OP_BITMASK      M6811_OP_BITMASK
    89. 

  89. #define OP_BRANCH       M6811_OP_BRANCH
    90. 

  90. #define OP_JUMP_REL     (M6811_OP_JUMP_REL|OP_BRANCH)
    91. 

  91. #define OP_JUMP_REL16   (M6812_OP_JUMP_REL16|OP_BRANCH)
    92. 

  92. #define OP_REG          M6812_OP_REG
    93. 

  93. #define OP_REG_1        M6812_OP_REG
    94. 

  94. #define OP_REG_2        M6812_OP_REG_2
    95. 

  95. #define OP_IDX_p2       M6812_OP_IDX_P2
    96. 

  96. #define OP_IND16_p2     M6812_OP_IND16_P2
    97. 

  97. #define OP_TRAP_ID      M6812_OP_TRAP_ID
    98. 

  98. #define OP_EXG_MARKER   M6812_OP_EXG_MARKER
    99. 

  99. #define OP_TFR_MARKER   M6812_OP_TFR_MARKER
    100. 

  100. #define OP_DBEQ_MARKER  (M6812_OP_DBCC_MARKER|M6812_OP_EQ_MARKER)
    101. 

  101. #define OP_DBNE_MARKER  (M6812_OP_DBCC_MARKER)
    102. 

  102. #define OP_TBEQ_MARKER  (M6812_OP_TBCC_MARKER|M6812_OP_EQ_MARKER)
    103. 

  103. #define OP_TBNE_MARKER  (M6812_OP_TBCC_MARKER)
    104. 

  104. #define OP_IBEQ_MARKER  (M6812_OP_IBCC_MARKER|M6812_OP_EQ_MARKER)
    105. 

  105. #define OP_IBNE_MARKER  (M6812_OP_IBCC_MARKER)
    106. 

  106. 

  107. /*
    108. 

  108.    { "test", OP_NONE,          1, 0x00,  5, _M,  CHG_NONE,  cpu6811, 0 },
    109. 

  109.                                                             +-- cpu  +-- XGATE opcode mask
    110. 

  110.   Name -+                                        +------- Insn CCR changes
    111. 

  111.   Format  ------+                            +----------- Max # cycles
    112. 

  112.   Size     --------------------+         +--------------- Min # cycles
    113. 

  113.                                    +--------------------- Opcode
    114. 

  114. */
    115. 

  115. const struct m68hc11_opcode m68hc11_opcodes[] = {
    116. 

  116.   { "aba",  OP_NONE,           1, 0x1b,  2,  2,  CHG_HNZVC, cpu6811, 0 },
    117. 

  117.   { "aba",  OP_NONE | OP_PAGE2,2, 0x06,  2,  2,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    118. 

  118.   { "abx",  OP_NONE,           1, 0x3a,  3,  3,  CHG_NONE,  cpu6811, 0 },
    119. 

  119.   { "aby",  OP_NONE | OP_PAGE2,2, 0x3a,  4,  4,  CHG_NONE,  cpu6811, 0 },
    120. 

  120. 

  121.   { "adca", OP_IMM8,           2, 0x89,  1,  1,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    122. 

  122.   { "adca", OP_DIRECT,         2, 0x99,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    123. 

  123.   { "adca", OP_IND16,          3, 0xb9,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    124. 

  124.   { "adca", OP_IX,             2, 0xa9,  4,  4,  CHG_HNZVC, cpu6811, 0 },
    125. 

  125.   { "adca", OP_IY | OP_PAGE2,  3, 0xa9,  5,  5,  CHG_HNZVC, cpu6811, 0 },
    126. 

  126.   { "adca", OP_IDX,            2, 0xa9,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    127. 

  127.   { "adca", OP_IDX_1,          3, 0xa9,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    128. 

  128.   { "adca", OP_IDX_2,          4, 0xa9,  4,  4,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    129. 

  129.   { "adca", OP_D_IDX,          2, 0xa9,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    130. 

  130.   { "adca", OP_D_IDX_2,        4, 0xa9,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    131. 

  131. 

  132.   { "adcb", OP_IMM8,           2, 0xc9,  1,  1,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    133. 

  133.   { "adcb", OP_DIRECT,         2, 0xd9,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    134. 

  134.   { "adcb", OP_IND16,          3, 0xf9,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    135. 

  135.   { "adcb", OP_IX,             2, 0xe9,  4,  4,  CHG_HNZVC, cpu6811, 0 },
    136. 

  136.   { "adcb", OP_IY | OP_PAGE2,  3, 0xe9,  5,  5,  CHG_HNZVC, cpu6811, 0 },
    137. 

  137.   { "adcb", OP_IDX,            2, 0xe9,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    138. 

  138.   { "adcb", OP_IDX_1,          3, 0xe9,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    139. 

  139.   { "adcb", OP_IDX_2,          4, 0xe9,  4,  4,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    140. 

  140.   { "adcb", OP_D_IDX,          2, 0xe9,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    141. 

  141.   { "adcb", OP_D_IDX_2,        4, 0xe9,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    142. 

  142. 

  143.   { "adda", OP_IMM8,           2, 0x8b,  1,  1,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    144. 

  144.   { "adda", OP_DIRECT,         2, 0x9b,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    145. 

  145.   { "adda", OP_IND16,          3, 0xbb,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    146. 

  146.   { "adda", OP_IX,             2, 0xab,  4,  4,  CHG_HNZVC, cpu6811, 0 },
    147. 

  147.   { "adda", OP_IY | OP_PAGE2,  3, 0xab,  5,  5,  CHG_HNZVC, cpu6811, 0 },
    148. 

  148.   { "adda", OP_IDX,            2, 0xab,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    149. 

  149.   { "adda", OP_IDX_1,          3, 0xab,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    150. 

  150.   { "adda", OP_IDX_2,          4, 0xab,  4,  4,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    151. 

  151.   { "adda", OP_D_IDX,          2, 0xab,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    152. 

  152.   { "adda", OP_D_IDX_2,        4, 0xab,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    153. 

  153. 

  154.   { "addb", OP_IMM8,           2, 0xcb,  1,  1,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    155. 

  155.   { "addb", OP_DIRECT,         2, 0xdb,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    156. 

  156.   { "addb", OP_IND16,          3, 0xfb,  3,  3,  CHG_HNZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    157. 

  157.   { "addb", OP_IX,             2, 0xeb,  4,  4,  CHG_HNZVC, cpu6811, 0 },
    158. 

  158.   { "addb", OP_IY | OP_PAGE2,  3, 0xeb,  5,  5,  CHG_HNZVC, cpu6811, 0 },
    159. 

  159.   { "addb", OP_IDX,            2, 0xeb,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    160. 

  160.   { "addb", OP_IDX_1,          3, 0xeb,  3,  3,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    161. 

  161.   { "addb", OP_IDX_2,          4, 0xeb,  4,  4,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    162. 

  162.   { "addb", OP_D_IDX,          2, 0xeb,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    163. 

  163.   { "addb", OP_D_IDX_2,        4, 0xeb,  6,  6,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    164. 

  164. 

  165.   { "addd", OP_IMM16,          3, 0xc3,  2,  2,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    166. 

  166.   { "addd", OP_DIRECT,         2, 0xd3,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    167. 

  167.   { "addd", OP_IND16,          3, 0xf3,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    168. 

  168.   { "addd", OP_IX,             2, 0xe3,  6,  6,  CHG_NZVC, cpu6811, 0 },
    169. 

  169.   { "addd", OP_IY | OP_PAGE2,  3, 0xe3,  7,  7,  CHG_NZVC, cpu6811, 0 },
    170. 

  170.   { "addd", OP_IDX,            2, 0xe3,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    171. 

  171.   { "addd", OP_IDX_1,          3, 0xe3,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    172. 

  172.   { "addd", OP_IDX_2,          4, 0xe3,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    173. 

  173.   { "addd", OP_D_IDX,          2, 0xe3,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    174. 

  174.   { "addd", OP_D_IDX_2,        4, 0xe3,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    175. 

  175. 

  176.   { "addx", OP_IMM16 | OP_PAGE2,          3, 0x8b,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    177. 

  177.   { "addx", OP_DIRECT | OP_PAGE2,         2, 0x9b,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    178. 

  178.   { "addx", OP_IND16 | OP_PAGE2,          3, 0xbb,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    179. 

  179.   { "addx", OP_IDX | OP_PAGE2,            2, 0xab,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    180. 

  180.   { "addx", OP_IDX_1 | OP_PAGE2,          3, 0xab,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    181. 

  181.   { "addx", OP_IDX_2 | OP_PAGE2,          4, 0xab,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    182. 

  182.   { "addx", OP_D_IDX | OP_PAGE2,          2, 0xab,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    183. 

  183.   { "addx", OP_D_IDX_2 | OP_PAGE2,        4, 0xab,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    184. 

  184. 

  185.   { "addy", OP_IMM16 | OP_PAGE2,          3, 0xcb,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    186. 

  186.   { "addy", OP_DIRECT | OP_PAGE2,         2, 0xdb,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    187. 

  187.   { "addy", OP_IND16 | OP_PAGE2,          3, 0xfb,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    188. 

  188.   { "addy", OP_IDX | OP_PAGE2,            2, 0xeb,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    189. 

  189.   { "addy", OP_IDX_1 | OP_PAGE2,          3, 0xeb,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    190. 

  190.   { "addy", OP_IDX_2 | OP_PAGE2,          4, 0xeb,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    191. 

  191.   { "addy", OP_D_IDX | OP_PAGE2,          2, 0xeb,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    192. 

  192.   { "addy", OP_D_IDX_2 | OP_PAGE2,        4, 0xeb,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    193. 

  193. 

  194.   { "aded", OP_IMM16 | OP_PAGE2,          3, 0xc3,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    195. 

  195.   { "aded", OP_DIRECT | OP_PAGE2,         2, 0xd3,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    196. 

  196.   { "aded", OP_IND16 | OP_PAGE2,          3, 0xf3,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    197. 

  197.   { "aded", OP_IDX | OP_PAGE2,            2, 0xe3,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    198. 

  198.   { "aded", OP_IDX_1 | OP_PAGE2,          3, 0xe3,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    199. 

  199.   { "aded", OP_IDX_2 | OP_PAGE2,          4, 0xe3,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    200. 

  200.   { "aded", OP_D_IDX | OP_PAGE2,          2, 0xe3,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    201. 

  201.   { "aded", OP_D_IDX_2 | OP_PAGE2,        4, 0xe3,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    202. 

  202. 

  203.   { "adex", OP_IMM16 | OP_PAGE2,          3, 0x89,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    204. 

  204.   { "adex", OP_DIRECT | OP_PAGE2,         2, 0x99,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    205. 

  205.   { "adex", OP_IND16 | OP_PAGE2,          3, 0xb9,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    206. 

  206.   { "adex", OP_IDX | OP_PAGE2,            2, 0xa9,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    207. 

  207.   { "adex", OP_IDX_1 | OP_PAGE2,          3, 0xa9,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    208. 

  208.   { "adex", OP_IDX_2 | OP_PAGE2,          4, 0xa9,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    209. 

  209.   { "adex", OP_D_IDX | OP_PAGE2,          2, 0xa9,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    210. 

  210.   { "adex", OP_D_IDX_2 | OP_PAGE2,        4, 0xa9,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    211. 

  211. 

  212.   { "adey", OP_IMM16 | OP_PAGE2,          3, 0xc9,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    213. 

  213.   { "adey", OP_DIRECT | OP_PAGE2,         2, 0xd9,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    214. 

  214.   { "adey", OP_IND16 | OP_PAGE2,          3, 0xf9,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    215. 

  215.   { "adey", OP_IDX | OP_PAGE2,            2, 0xe9,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    216. 

  216.   { "adey", OP_IDX_1 | OP_PAGE2,          3, 0xe9,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    217. 

  217.   { "adey", OP_IDX_2 | OP_PAGE2,          4, 0xe9,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    218. 

  218.   { "adey", OP_D_IDX | OP_PAGE2,          2, 0xe9,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    219. 

  219.   { "adey", OP_D_IDX_2 | OP_PAGE2,        4, 0xe9,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    220. 

  220. 

  221.   { "anda", OP_IMM8,         2, 0x84,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    222. 

  222.   { "anda", OP_DIRECT,       2, 0x94,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    223. 

  223.   { "anda", OP_IND16,        3, 0xb4,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    224. 

  224.   { "anda", OP_IX,             2, 0xa4,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    225. 

  225.   { "anda", OP_IY | OP_PAGE2,  3, 0xa4,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    226. 

  226.   { "anda", OP_IDX,            2, 0xa4,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    227. 

  227.   { "anda", OP_IDX_1,          3, 0xa4,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    228. 

  228.   { "anda", OP_IDX_2,          4, 0xa4,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    229. 

  229.   { "anda", OP_D_IDX,          2, 0xa4,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    230. 

  230.   { "anda", OP_D_IDX_2,        4, 0xa4,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    231. 

  231. 

  232.   { "andb", OP_IMM8,         2, 0xc4,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    233. 

  233.   { "andb", OP_DIRECT,       2, 0xd4,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    234. 

  234.   { "andb", OP_IND16,        3, 0xf4,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    235. 

  235.   { "andb", OP_IX,             2, 0xe4,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    236. 

  236.   { "andb", OP_IY | OP_PAGE2,  3, 0xe4,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    237. 

  237.   { "andb", OP_IDX,            2, 0xe4,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    238. 

  238.   { "andb", OP_IDX_1,          3, 0xe4,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    239. 

  239.   { "andb", OP_IDX_2,          4, 0xe4,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    240. 

  240.   { "andb", OP_D_IDX,          2, 0xe4,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    241. 

  241.   { "andb", OP_D_IDX_2,        4, 0xe4,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    242. 

  242. 

  243.   { "andcc", OP_IMM8,          2, 0x10,  1,  1,  CHG_ALL,  cpu6812|cpu9s12x, 0 },
    244. 

  244. 

  245.   { "andx", OP_IMM16 | OP_PAGE2,         2, 0x84,  1,  1,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    246. 

  246.   { "andx", OP_DIRECT | OP_PAGE2,       2, 0x94,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    247. 

  247.   { "andx", OP_IND16 | OP_PAGE2,        3, 0xb4,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    248. 

  248.   { "andx", OP_IDX | OP_PAGE2,            2, 0xa4,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    249. 

  249.   { "andx", OP_IDX_1 | OP_PAGE2,          3, 0xa4,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    250. 

  250.   { "andx", OP_IDX_2 | OP_PAGE2,          4, 0xa4,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    251. 

  251.   { "andx", OP_D_IDX | OP_PAGE2,          2, 0xa4,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    252. 

  252.   { "andx", OP_D_IDX_2 | OP_PAGE2,        4, 0xa4,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    253. 

  253. 

  254.   { "andy", OP_IMM16 | OP_PAGE2,         2, 0xc4,  1,  1,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    255. 

  255.   { "andy", OP_DIRECT | OP_PAGE2,       2, 0xd4,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    256. 

  256.   { "andy", OP_IND16 | OP_PAGE2,        3, 0xf4,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    257. 

  257.   { "andy", OP_IDX | OP_PAGE2,            2, 0xe4,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    258. 

  258.   { "andy", OP_IDX_1 | OP_PAGE2,          3, 0xe4,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    259. 

  259.   { "andy", OP_IDX_2 | OP_PAGE2,          4, 0xe4,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    260. 

  260.   { "andy", OP_D_IDX | OP_PAGE2,          2, 0xe4,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    261. 

  261.   { "andy", OP_D_IDX_2 | OP_PAGE2,        4, 0xe4,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    262. 

  262. 

  263.   { "asl",  OP_IND16,          3, 0x78,  4,  4,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    264. 

  264.   { "asl",  OP_IX,             2, 0x68,  6,  6,  CHG_NZVC, cpu6811, 0 },
    265. 

  265.   { "asl",  OP_IY | OP_PAGE2,  3, 0x68,  7,  7,  CHG_NZVC, cpu6811, 0 },
    266. 

  266.   { "asl",  OP_IDX,            2, 0x68,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    267. 

  267.   { "asl",  OP_IDX_1,          3, 0x68,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    268. 

  268.   { "asl",  OP_IDX_2,          4, 0x68,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    269. 

  269.   { "asl",  OP_D_IDX,          2, 0x68,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    270. 

  270.   { "asl",  OP_D_IDX_2,        4, 0x68,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    271. 

  271. 

  272.   { "asla", OP_NONE,           1, 0x48,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    273. 

  273.   { "aslb", OP_NONE,           1, 0x58,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    274. 

  274.   { "asld", OP_NONE,           1, 0x05,  3,  3,  CHG_NZVC, cpu6811, 0 },
    275. 

  275.   { "asld", OP_NONE,           1, 0x59,  1,  1,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    276. 

  276. 

  277.   { "aslw",  OP_IND16 | OP_PAGE2,          3, 0x78,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    278. 

  278.   { "aslw",  OP_IDX | OP_PAGE2,            2, 0x68,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    279. 

  279.   { "aslw",  OP_IDX_1 | OP_PAGE2,          3, 0x68,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    280. 

  280.   { "aslw",  OP_IDX_2 | OP_PAGE2,          4, 0x68,  5,  5,  CHG_NZVC, cpu9s12x, 0 },
    281. 

  281.   { "aslw",  OP_D_IDX | OP_PAGE2,          2, 0x68,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    282. 

  282.   { "aslw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x68,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    283. 

  283. 

  284.   { "aslx", OP_NONE | OP_PAGE2,           1, 0x48,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    285. 

  285. 

  286.   { "asly", OP_NONE | OP_PAGE2,           1, 0x58,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    287. 

  287. 

  288.   { "asr",  OP_IND16,          3, 0x77,  4,  4,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    289. 

  289.   { "asr",  OP_IX,             2, 0x67,  6,  6,  CHG_NZVC, cpu6811, 0 },
    290. 

  290.   { "asr",  OP_IY | OP_PAGE2,  3, 0x67,  7,  7,  CHG_NZVC, cpu6811, 0 },
    291. 

  291.   { "asr",  OP_IDX,            2, 0x67,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    292. 

  292.   { "asr",  OP_IDX_1,          3, 0x67,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    293. 

  293.   { "asr",  OP_IDX_2,          4, 0x67,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    294. 

  294.   { "asr",  OP_D_IDX,          2, 0x67,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    295. 

  295.   { "asr",  OP_D_IDX_2,        4, 0x67,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    296. 

  296. 

  297.   { "asra", OP_NONE,           1, 0x47,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    298. 

  298.   { "asrb", OP_NONE,           1, 0x57,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    299. 

  299. 

  300.   { "asrw",  OP_IND16 | OP_PAGE2,          3, 0x77,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    301. 

  301.   { "asrw",  OP_IDX | OP_PAGE2,            2, 0x67,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    302. 

  302.   { "asrw",  OP_IDX_1 | OP_PAGE2,          3, 0x67,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    303. 

  303.   { "asrw",  OP_IDX_2 | OP_PAGE2,          4, 0x67,  5,  5,  CHG_NZVC, cpu9s12x, 0 },
    304. 

  304.   { "asrw",  OP_D_IDX | OP_PAGE2,          2, 0x67,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    305. 

  305.   { "asrw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x67,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    306. 

  306. 

  307.   { "asrx", OP_NONE | OP_PAGE2,           1, 0x47,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    308. 

  308. 

  309.   { "asry", OP_NONE | OP_PAGE2,           1, 0x57,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    310. 

  310. 

  311.   { "bcc", OP_JUMP_REL,        2, 0x24,  1,  3,  CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    312. 

  312. 

  313.   { "bclr", OP_BITMASK|OP_DIRECT,  3, 0x15,  6,  6,  CLR_V_CHG_NZ, cpu6811, 0 },
    314. 

  314.   { "bclr", OP_BITMASK|OP_IX,       3, 0x1d,  7,  7,  CLR_V_CHG_NZ, cpu6811, 0 },
    315. 

  315.   { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 },
    316. 

  316.   { "bclr", OP_BITMASK|OP_DIRECT,   3, 0x4d,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    317. 

  317.   { "bclr", OP_BITMASK|OP_IND16,    4, 0x1d,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    318. 

  318.   { "bclr", OP_BITMASK|OP_IDX,      3, 0x0d,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    319. 

  319.   { "bclr", OP_BITMASK|OP_IDX_1,    4, 0x0d,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    320. 

  320.   { "bclr", OP_BITMASK|OP_IDX_2,    5, 0x0d,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    321. 

  321. 

  322.   { "bcs", OP_JUMP_REL,        2, 0x25,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    323. 

  323.   { "beq", OP_JUMP_REL,        2, 0x27,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    324. 

  324.   { "bge", OP_JUMP_REL,        2, 0x2c,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    325. 

  325. 

  326.   { "bgnd", OP_NONE,           1, 0x00,  5,  5, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    327. 

  327. 

  328.   { "bgt", OP_JUMP_REL,        2, 0x2e,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    329. 

  329.   { "bhi", OP_JUMP_REL,        2, 0x22,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    330. 

  330.   { "bhs", OP_JUMP_REL,        2, 0x24,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    331. 

  331. 

  332.   { "bita", OP_IMM8,          2, 0x85,  1,  1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    333. 

  333.   { "bita", OP_DIRECT,        2, 0x95,  3,  3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    334. 

  334.   { "bita", OP_IND16,         3, 0xb5,  3,  3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    335. 

  335.   { "bita", OP_IX,             2, 0xa5,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    336. 

  336.   { "bita", OP_IY | OP_PAGE2,  3, 0xa5,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    337. 

  337.   { "bita", OP_IDX,            2, 0xa5,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    338. 

  338.   { "bita", OP_IDX_1,          3, 0xa5,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    339. 

  339.   { "bita", OP_IDX_2,          4, 0xa5,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    340. 

  340.   { "bita", OP_D_IDX,          2, 0xa5,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    341. 

  341.   { "bita", OP_D_IDX_2,        4, 0xa5,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    342. 

  342. 

  343.   { "bitb", OP_IMM8,          2, 0xc5,  1,  1, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    344. 

  344.   { "bitb", OP_DIRECT,        2, 0xd5,  3,  3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    345. 

  345.   { "bitb", OP_IND16,         3, 0xf5,  3,  3, CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    346. 

  346.   { "bitb", OP_IX,             2, 0xe5,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    347. 

  347.   { "bitb", OP_IY | OP_PAGE2,  3, 0xe5,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    348. 

  348.   { "bitb", OP_IDX,            2, 0xe5,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    349. 

  349.   { "bitb", OP_IDX_1,          3, 0xe5,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    350. 

  350.   { "bitb", OP_IDX_2,          4, 0xe5,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    351. 

  351.   { "bitb", OP_D_IDX,          2, 0xe5,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    352. 

  352.   { "bitb", OP_D_IDX_2,        4, 0xe5,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    353. 

  353. 

  354.   { "bitx", OP_IMM16 | OP_PAGE2,          2, 0x85,  1,  1, CLR_V_CHG_NZ, cpu9s12x, 0 },
    355. 

  355.   { "bitx", OP_DIRECT | OP_PAGE2,        2, 0x95,  3,  3, CLR_V_CHG_NZ, cpu9s12x, 0 },
    356. 

  356.   { "bitx", OP_IND16 | OP_PAGE2,         3, 0xb5,  3,  3, CLR_V_CHG_NZ, cpu9s12x, 0 },
    357. 

  357.   { "bitx", OP_IDX | OP_PAGE2,            2, 0xa5,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    358. 

  358.   { "bitx", OP_IDX_1 | OP_PAGE2,          3, 0xa5,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    359. 

  359.   { "bitx", OP_IDX_2 | OP_PAGE2,          4, 0xa5,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    360. 

  360.   { "bitx", OP_D_IDX | OP_PAGE2,          2, 0xa5,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    361. 

  361.   { "bitx", OP_D_IDX_2 | OP_PAGE2,        4, 0xa5,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    362. 

  362. 

  363.   { "bity", OP_IMM16 | OP_PAGE2,          2, 0xc5,  1,  1, CLR_V_CHG_NZ, cpu9s12x, 0 },
    364. 

  364.   { "bity", OP_DIRECT | OP_PAGE2,        2, 0xd5,  3,  3, CLR_V_CHG_NZ, cpu9s12x, 0 },
    365. 

  365.   { "bity", OP_IND16 | OP_PAGE2,         3, 0xf5,  3,  3, CLR_V_CHG_NZ, cpu9s12x, 0 },
    366. 

  366.   { "bity", OP_IDX | OP_PAGE2,            2, 0xe5,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    367. 

  367.   { "bity", OP_IDX_1 | OP_PAGE2,          3, 0xe5,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    368. 

  368.   { "bity", OP_IDX_2 | OP_PAGE2,          4, 0xe5,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    369. 

  369.   { "bity", OP_D_IDX | OP_PAGE2,          2, 0xe5,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    370. 

  370.   { "bity", OP_D_IDX_2 | OP_PAGE2,        4, 0xe5,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    371. 

  371. 

  372.   { "ble", OP_JUMP_REL,        2, 0x2f,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    373. 

  373.   { "blo", OP_JUMP_REL,        2, 0x25,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    374. 

  374.   { "bls", OP_JUMP_REL,        2, 0x23,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    375. 

  375.   { "blt", OP_JUMP_REL,        2, 0x2d,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    376. 

  376.   { "bmi", OP_JUMP_REL,        2, 0x2b,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    377. 

  377.   { "bne", OP_JUMP_REL,        2, 0x26,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    378. 

  378.   { "bpl", OP_JUMP_REL,        2, 0x2a,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    379. 

  379.   { "bra", OP_JUMP_REL,        2, 0x20,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    380. 

  380. 

  381.   { "brclr", OP_BITMASK | OP_JUMP_REL
    382. 

  382.            | OP_DIRECT,         4, 0x13,  6,  6, CHG_NONE, cpu6811, 0 },
    383. 

  383.   { "brclr", OP_BITMASK | OP_JUMP_REL
    384. 

  384.            | OP_IX,             4, 0x1f,  7,  7, CHG_NONE, cpu6811, 0 },
    385. 

  385.   { "brclr", OP_BITMASK | OP_JUMP_REL
    386. 

  386.            | OP_IY | OP_PAGE2,  5, 0x1f,  8,  8, CHG_NONE, cpu6811, 0 },
    387. 

  387.   { "brclr", OP_BITMASK | OP_JUMP_REL
    388. 

  388.            | OP_DIRECT,         4, 0x4f,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    389. 

  389.   { "brclr", OP_BITMASK | OP_JUMP_REL
    390. 

  390.            | OP_IND16,          5, 0x1f,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    391. 

  391.   { "brclr", OP_BITMASK | OP_JUMP_REL
    392. 

  392.            | OP_IDX,            4, 0x0f,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    393. 

  393.   { "brclr", OP_BITMASK | OP_JUMP_REL
    394. 

  394.            | OP_IDX_1,          5, 0x0f,  6,  6,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    395. 

  395.   { "brclr", OP_BITMASK
    396. 

  396.            | OP_JUMP_REL
    397. 

  397.            | OP_IDX_2,          6, 0x0f,  8,  8,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    398. 

  398. 

  399.   { "brn", OP_JUMP_REL,         2, 0x21,  1,  3,  CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    400. 

  400. 

  401.   { "brset", OP_BITMASK | OP_JUMP_REL
    402. 

  402.            | OP_DIRECT,         4, 0x12,  6,  6,  CHG_NONE, cpu6811, 0 },
    403. 

  403.   { "brset", OP_BITMASK
    404. 

  404.            | OP_JUMP_REL
    405. 

  405.            | OP_IX,             4, 0x1e,  7,  7,  CHG_NONE, cpu6811, 0 },
    406. 

  406.   { "brset", OP_BITMASK | OP_JUMP_REL
    407. 

  407.            | OP_IY | OP_PAGE2,  5, 0x1e,  8,  8,  CHG_NONE, cpu6811, 0 },
    408. 

  408.   { "brset", OP_BITMASK | OP_JUMP_REL
    409. 

  409.            | OP_DIRECT,   4, 0x4e,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    410. 

  410.   { "brset", OP_BITMASK | OP_JUMP_REL
    411. 

  411.            | OP_IND16,    5, 0x1e,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    412. 

  412.   { "brset", OP_BITMASK | OP_JUMP_REL
    413. 

  413.            | OP_IDX,            4, 0x0e,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    414. 

  414.   { "brset", OP_BITMASK | OP_JUMP_REL
    415. 

  415.            | OP_IDX_1,          5, 0x0e,  6,  6,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    416. 

  416.   { "brset", OP_BITMASK | OP_JUMP_REL
    417. 

  417.            | OP_IDX_2,          6, 0x0e,  8,  8,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    418. 

  418. 

  419. 

  420.   { "bset", OP_BITMASK | OP_DIRECT,   3, 0x14,  6,  6, CLR_V_CHG_NZ, cpu6811, 0 },
    421. 

  421.   { "bset", OP_BITMASK | OP_IX,       3, 0x1c,  7,  7, CLR_V_CHG_NZ, cpu6811, 0 },
    422. 

  422.   { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 },
    423. 

  423.   { "bset", OP_BITMASK|OP_DIRECT,   3, 0x4c,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    424. 

  424.   { "bset", OP_BITMASK|OP_IND16,    4, 0x1c,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    425. 

  425.   { "bset", OP_BITMASK|OP_IDX,      3, 0x0c,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    426. 

  426.   { "bset", OP_BITMASK|OP_IDX_1,    4, 0x0c,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    427. 

  427.   { "bset", OP_BITMASK|OP_IDX_2,    5, 0x0c,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    428. 

  428. 

  429.   { "bsr",  OP_JUMP_REL,       2, 0x8d,  6,  6, CHG_NONE, cpu6811, 0 },
    430. 

  430.   { "bsr",  OP_JUMP_REL,       2, 0x07,  4,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    431. 

  431. 

  432.   { "btas", OP_BITMASK|OP_DIRECT | OP_PAGE2,   3, 0x35,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    433. 

  433.   { "btas", OP_BITMASK|OP_IND16 | OP_PAGE2,    4, 0x36,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    434. 

  434.   { "btas", OP_BITMASK|OP_IDX | OP_PAGE2,      3, 0x37,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    435. 

  435.   { "btas", OP_BITMASK|OP_IDX_1 | OP_PAGE2,    4, 0x37,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    436. 

  436.   { "btas", OP_BITMASK|OP_IDX_2 | OP_PAGE2,    5, 0x37,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    437. 

  437. 

  438.   { "bvc",  OP_JUMP_REL,       2, 0x28,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    439. 

  439.   { "bvs",  OP_JUMP_REL,       2, 0x29,  1,  3, CHG_NONE, cpu6811 | cpu6812|cpu9s12x, 0 },
    440. 

  440. 

  441.   { "call", OP_IND16 | OP_PAGE
    442. 

  442.           | OP_BRANCH,         4, 0x4a,  8,  8,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    443. 

  443.   { "call", OP_IDX | OP_PAGE
    444. 

  444.           | OP_BRANCH,         3, 0x4b,  8,  8,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    445. 

  445.   { "call", OP_IDX_1 | OP_PAGE
    446. 

  446.           | OP_BRANCH,         4, 0x4b,  8,  8,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    447. 

  447.   { "call", OP_IDX_2 | OP_PAGE
    448. 

  448.           | OP_BRANCH,         5, 0x4b,  9,  9,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    449. 

  449.   { "call", OP_D_IDX
    450. 

  450.           | OP_BRANCH,         2, 0x4b, 10, 10,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    451. 

  451.   { "call", OP_D_IDX_2
    452. 

  452.           | OP_BRANCH,         4, 0x4b, 10, 10,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    453. 

  453. 

  454.   { "cba",  OP_NONE,           1, 0x11,  2,  2,  CHG_NZVC, cpu6811, 0 },
    455. 

  455.   { "cba",  OP_NONE | OP_PAGE2,2, 0x17,  2,  2,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    456. 

  456. 

  457.   { "clc",  OP_NONE,           1, 0x0c,  2,  2,  CLR_C, cpu6811, 0 },
    458. 

  458.   { "cli",  OP_NONE,           1, 0x0e,  2,  2,  CLR_I, cpu6811, 0 },
    459. 

  459. 

  460.   { "clr", OP_IND16,           3, 0x7f,  6,  6,  SET_Z_CLR_NVC, cpu6811, 0 },
    461. 

  461.   { "clr", OP_IX,              2, 0x6f,  6,  6,  SET_Z_CLR_NVC, cpu6811, 0 },
    462. 

  462.   { "clr", OP_IY | OP_PAGE2,   3, 0x6f,  7,  7,  SET_Z_CLR_NVC, cpu6811, 0 },
    463. 

  463.   { "clr", OP_IND16,           3, 0x79,  3,  3,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    464. 

  464.   { "clr", OP_IDX,             2, 0x69,  2,  2,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    465. 

  465.   { "clr", OP_IDX_1,           3, 0x69,  3,  3,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    466. 

  466.   { "clr", OP_IDX_2,           4, 0x69,  4,  4,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    467. 

  467.   { "clr", OP_D_IDX,           2, 0x69,  5,  5,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    468. 

  468.   { "clr", OP_D_IDX_2,         4, 0x69,  5,  5,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    469. 

  469. 

  470.   { "clra", OP_NONE,           1, 0x4f,  2,  2,  SET_Z_CLR_NVC, cpu6811, 0 },
    471. 

  471.   { "clrb", OP_NONE,           1, 0x5f,  2,  2,  SET_Z_CLR_NVC, cpu6811, 0 },
    472. 

  472.   { "clra", OP_NONE,           1, 0x87,  1,  1,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    473. 

  473.   { "clrb", OP_NONE,           1, 0xc7,  1,  1,  SET_Z_CLR_NVC, cpu6812|cpu9s12x, 0 },
    474. 

  474. 

  475.   { "clrw",  OP_IND16 | OP_PAGE2,          3, 0x79,  4,  4,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    476. 

  476.   { "clrw",  OP_IDX | OP_PAGE2,            2, 0x69,  3,  3,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    477. 

  477.   { "clrw",  OP_IDX_1 | OP_PAGE2,          3, 0x69,  4,  4,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    478. 

  478.   { "clrw",  OP_IDX_2 | OP_PAGE2,          4, 0x69,  5,  5,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    479. 

  479.   { "clrw",  OP_D_IDX | OP_PAGE2,          2, 0x69,  6,  6,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    480. 

  480.   { "clrw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x69,  6,  6,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    481. 

  481. 

  482.   { "clrx",  OP_NONE | OP_PAGE2,          3, 0x87,  4,  4,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    483. 

  483. 

  484.   { "clry",  OP_NONE | OP_PAGE2,          3, 0xc7,  4,  4,  SET_Z_CLR_NVC, cpu9s12x, 0 },
    485. 

  485. 

  486.   { "clv",  OP_NONE,           1, 0x0a,  2,  2,  CLR_V, cpu6811, 0 },
    487. 

  487. 

  488.   { "cmpa", OP_IMM8,           2, 0x81,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    489. 

  489.   { "cmpa", OP_DIRECT,         2, 0x91,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    490. 

  490.   { "cmpa", OP_IND16,          3, 0xb1,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    491. 

  491.   { "cmpa", OP_IX,             2, 0xa1,  4,  4,  CHG_NZVC, cpu6811, 0 },
    492. 

  492.   { "cmpa", OP_IY | OP_PAGE2,  3, 0xa1,  5,  5,  CHG_NZVC, cpu6811, 0 },
    493. 

  493.   { "cmpa", OP_IDX,            2, 0xa1,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    494. 

  494.   { "cmpa", OP_IDX_1,          3, 0xa1,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    495. 

  495.   { "cmpa", OP_IDX_2,          4, 0xa1,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    496. 

  496.   { "cmpa", OP_D_IDX,          2, 0xa1,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    497. 

  497.   { "cmpa", OP_D_IDX_2,        4, 0xa1,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    498. 

  498. 

  499.   { "cmpb", OP_IMM8,           2, 0xc1,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    500. 

  500.   { "cmpb", OP_DIRECT,         2, 0xd1,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    501. 

  501.   { "cmpb", OP_IND16,          3, 0xf1,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    502. 

  502.   { "cmpb", OP_IX,             2, 0xe1,  4,  4,  CHG_NZVC, cpu6811, 0 },
    503. 

  503.   { "cmpb", OP_IY | OP_PAGE2,  3, 0xe1,  5,  5,  CHG_NZVC, cpu6811, 0 },
    504. 

  504.   { "cmpb", OP_IDX,            2, 0xe1,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    505. 

  505.   { "cmpb", OP_IDX_1,          3, 0xe1,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    506. 

  506.   { "cmpb", OP_IDX_2,          4, 0xe1,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    507. 

  507.   { "cmpb", OP_D_IDX,          2, 0xe1,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    508. 

  508.   { "cmpb", OP_D_IDX_2,        4, 0xe1,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    509. 

  509. 

  510.   { "com", OP_IND16,           3, 0x73,  6,  6,  SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
    511. 

  511.   { "com", OP_IX,              2, 0x63,  6,  6,  SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
    512. 

  512.   { "com", OP_IY | OP_PAGE2,   3, 0x63,  7,  7,  SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
    513. 

  513.   { "com", OP_IND16,           3, 0x71,  4,  4,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    514. 

  514.   { "com", OP_IDX,             2, 0x61,  3,  3,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    515. 

  515.   { "com", OP_IDX_1,           3, 0x61,  4,  4,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    516. 

  516.   { "com", OP_IDX_2,           4, 0x61,  5,  5,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    517. 

  517.   { "com", OP_D_IDX,           2, 0x61,  6,  6,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    518. 

  518.   { "com", OP_D_IDX_2,         4, 0x61,  6,  6,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    519. 

  519. 

  520.   { "coma", OP_NONE,           1, 0x43,  2,  2,  SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
    521. 

  521.   { "coma", OP_NONE,           1, 0x41,  1,  1,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    522. 

  522.   { "comb", OP_NONE,           1, 0x53,  2,  2,  SET_C_CLR_V_CHG_NZ, cpu6811, 0 },
    523. 

  523.   { "comb", OP_NONE,           1, 0x51,  1,  1,  SET_C_CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    524. 

  524. 

  525.   { "comw",  OP_IND16 | OP_PAGE2,          3, 0x71,  4,  4,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    526. 

  526.   { "comw",  OP_IDX | OP_PAGE2,            2, 0x61,  3,  3,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    527. 

  527.   { "comw",  OP_IDX_1 | OP_PAGE2,          3, 0x61,  4,  4,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    528. 

  528.   { "comw",  OP_IDX_2 | OP_PAGE2,          4, 0x61,  5,  5,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    529. 

  529.   { "comw",  OP_D_IDX | OP_PAGE2,          2, 0x61,  6,  6,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    530. 

  530.   { "comw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x61,  6,  6,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    531. 

  531. 

  532.   { "comx", OP_NONE | OP_PAGE2,           1, 0x41,  2,  2,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    533. 

  533. 

  534.   { "comy", OP_NONE | OP_PAGE2,           1, 0x51,  2,  2,  SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },
    535. 

  535. 

  536.   { "cpd", OP_IMM16 | OP_PAGE3,  4, 0x83,  5,  5,  CHG_NZVC, cpu6811, 0 },
    537. 

  537.   { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93,  6,  6,  CHG_NZVC, cpu6811, 0 },
    538. 

  538.   { "cpd", OP_IND16 | OP_PAGE3,  4, 0xb3,  7,  7,  CHG_NZVC, cpu6811, 0 },
    539. 

  539.   { "cpd", OP_IX | OP_PAGE3,     3, 0xa3,  7,  7,  CHG_NZVC, cpu6811, 0 },
    540. 

  540.   { "cpd", OP_IY | OP_PAGE4,     3, 0xa3,  7,  7,  CHG_NZVC, cpu6811, 0 },
    541. 

  541.   { "cpd", OP_IMM16,             3, 0x8c,  2,  2,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    542. 

  542.   { "cpd", OP_DIRECT,            2, 0x9c,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    543. 

  543.   { "cpd", OP_IND16,             3, 0xbc,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    544. 

  544.   { "cpd", OP_IDX,               2, 0xac,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    545. 

  545.   { "cpd", OP_IDX_1,             3, 0xac,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    546. 

  546.   { "cpd", OP_IDX_2,             4, 0xac,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    547. 

  547.   { "cpd", OP_D_IDX,             2, 0xac,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    548. 

  548.   { "cpd", OP_D_IDX_2,           4, 0xac,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    549. 

  549. 

  550.   { "cped", OP_IMM16 | OP_PAGE2,             3, 0x8c,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    551. 

  551.   { "cped", OP_DIRECT | OP_PAGE2,            2, 0x9c,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    552. 

  552.   { "cped", OP_IND16 | OP_PAGE2,             3, 0xbc,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    553. 

  553.   { "cped", OP_IDX | OP_PAGE2,               2, 0xac,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    554. 

  554.   { "cped", OP_IDX_1 | OP_PAGE2,             3, 0xac,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    555. 

  555.   { "cped", OP_IDX_2 | OP_PAGE2,             4, 0xac,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    556. 

  556.   { "cped", OP_D_IDX | OP_PAGE2,             2, 0xac,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    557. 

  557.   { "cped", OP_D_IDX_2 | OP_PAGE2,           4, 0xac,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    558. 

  558. 

  559.   { "cpes", OP_IMM16 | OP_PAGE2,             3, 0x8f,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    560. 

  560.   { "cpes", OP_DIRECT | OP_PAGE2,            2, 0x9f,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    561. 

  561.   { "cpes", OP_IND16 | OP_PAGE2,             3, 0xbf,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    562. 

  562.   { "cpes", OP_IDX | OP_PAGE2,               2, 0xaf,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    563. 

  563.   { "cpes", OP_IDX_1 | OP_PAGE2,             3, 0xaf,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    564. 

  564.   { "cpes", OP_IDX_2 | OP_PAGE2,             4, 0xaf,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    565. 

  565.   { "cpes", OP_D_IDX | OP_PAGE2,             2, 0xaf,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    566. 

  566.   { "cpes", OP_D_IDX_2 | OP_PAGE2,           4, 0xaf,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    567. 

  567. 

  568.   { "cpex", OP_IMM16 | OP_PAGE2,             3, 0x8e,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    569. 

  569.   { "cpex", OP_DIRECT | OP_PAGE2,            2, 0x9e,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    570. 

  570.   { "cpex", OP_IND16 | OP_PAGE2,             3, 0xbe,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    571. 

  571.   { "cpex", OP_IDX | OP_PAGE2,               2, 0xae,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    572. 

  572.   { "cpex", OP_IDX_1 | OP_PAGE2,             3, 0xae,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    573. 

  573.   { "cpex", OP_IDX_2 | OP_PAGE2,             4, 0xae,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    574. 

  574.   { "cpex", OP_D_IDX | OP_PAGE2,             2, 0xae,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    575. 

  575.   { "cpex", OP_D_IDX_2 | OP_PAGE2,           4, 0xae,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    576. 

  576. 

  577.   { "cpey", OP_IMM16 | OP_PAGE2,             3, 0x8d,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    578. 

  578.   { "cpey", OP_DIRECT | OP_PAGE2,            2, 0x9d,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    579. 

  579.   { "cpey", OP_IND16 | OP_PAGE2,             3, 0xbd,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    580. 

  580.   { "cpey", OP_IDX | OP_PAGE2,               2, 0xad,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    581. 

  581.   { "cpey", OP_IDX_1 | OP_PAGE2,             3, 0xad,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    582. 

  582.   { "cpey", OP_IDX_2 | OP_PAGE2,             4, 0xad,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    583. 

  583.   { "cpey", OP_D_IDX | OP_PAGE2,             2, 0xad,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    584. 

  584.   { "cpey", OP_D_IDX_2 | OP_PAGE2,           4, 0xad,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    585. 

  585. 

  586.   { "cps", OP_IMM16,             3, 0x8f,  2,  2,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    587. 

  587.   { "cps", OP_DIRECT,            2, 0x9f,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    588. 

  588.   { "cps", OP_IND16,             3, 0xbf,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    589. 

  589.   { "cps", OP_IDX,               2, 0xaf,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    590. 

  590.   { "cps", OP_IDX_1,             3, 0xaf,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    591. 

  591.   { "cps", OP_IDX_2,             4, 0xaf,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    592. 

  592.   { "cps", OP_D_IDX,             2, 0xaf,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    593. 

  593.   { "cps", OP_D_IDX_2,           4, 0xaf,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    594. 

  594. 

  595.   { "cpx", OP_IMM16,             3, 0x8c,  4,  4,  CHG_NZVC, cpu6811, 0 },
    596. 

  596.   { "cpx", OP_DIRECT,            2, 0x9c,  5,  5,  CHG_NZVC, cpu6811, 0 },
    597. 

  597.   { "cpx", OP_IND16,             3, 0xbc,  5,  5,  CHG_NZVC, cpu6811, 0 },
    598. 

  598.   { "cpx", OP_IX,                2, 0xac,  6,  6,  CHG_NZVC, cpu6811, 0 },
    599. 

  599.   { "cpx", OP_IY | OP_PAGE4,     3, 0xac,  7,  7,  CHG_NZVC, cpu6811, 0 },
    600. 

  600.   { "cpx", OP_IMM16,             3, 0x8e,  2,  2,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    601. 

  601.   { "cpx", OP_DIRECT,            2, 0x9e,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    602. 

  602.   { "cpx", OP_IND16,             3, 0xbe,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    603. 

  603.   { "cpx", OP_IDX,               2, 0xae,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    604. 

  604.   { "cpx", OP_IDX_1,             3, 0xae,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    605. 

  605.   { "cpx", OP_IDX_2,             4, 0xae,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    606. 

  606.   { "cpx", OP_D_IDX,             2, 0xae,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    607. 

  607.   { "cpx", OP_D_IDX_2,           4, 0xae,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    608. 

  608. 

  609.   { "cpy", OP_PAGE2 | OP_IMM16,  4, 0x8c,  5,  5,  CHG_NZVC, cpu6811, 0 },
    610. 

  610.   { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c,  6,  6,  CHG_NZVC, cpu6811, 0 },
    611. 

  611.   { "cpy", OP_PAGE2 | OP_IY,     3, 0xac,  7,  7,  CHG_NZVC, cpu6811, 0 },
    612. 

  612.   { "cpy", OP_PAGE2 | OP_IND16,  4, 0xbc,  7,  7,  CHG_NZVC, cpu6811, 0 },
    613. 

  613.   { "cpy", OP_PAGE3 | OP_IX,     3, 0xac,  7,  7,  CHG_NZVC, cpu6811, 0 },
    614. 

  614.   { "cpy", OP_IMM16,             3, 0x8d,  2,  2,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    615. 

  615.   { "cpy", OP_DIRECT,            2, 0x9d,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    616. 

  616.   { "cpy", OP_IND16,             3, 0xbd,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    617. 

  617.   { "cpy", OP_IDX,               2, 0xad,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    618. 

  618.   { "cpy", OP_IDX_1,             3, 0xad,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    619. 

  619.   { "cpy", OP_IDX_2,             4, 0xad,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    620. 

  620.   { "cpy", OP_D_IDX,             2, 0xad,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    621. 

  621.   { "cpy", OP_D_IDX_2,           4, 0xad,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    622. 

  622. 

  623.   /* After 'daa', the Z flag is undefined. Mark it as changed.  */
    624. 

  624.   { "daa", OP_NONE,              1, 0x19,  2,  2,  CHG_NZVC, cpu6811, 0 },
    625. 

  625.   { "daa", OP_NONE | OP_PAGE2,  2, 0x07,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    626. 

  626. 

  627.   { "dbeq", OP_DBEQ_MARKER
    628. 

  628.           | OP_REG | OP_JUMP_REL,3, 0x04,  3,  3, CHG_NONE, cpu6812|cpu9s12x, 0 },
    629. 

  629.   { "dbne", OP_DBNE_MARKER
    630. 

  630.           | OP_REG | OP_JUMP_REL,3, 0x04,  3,  3, CHG_NONE, cpu6812|cpu9s12x, 0 },
    631. 

  631. 

  632.   { "dec", OP_IX,                2, 0x6a,  6,  6,  CHG_NZV, cpu6811, 0 },
    633. 

  633.   { "dec", OP_IND16,             3, 0x7a,  6,  6,  CHG_NZV, cpu6811, 0 },
    634. 

  634.   { "dec", OP_IY | OP_PAGE2,     3, 0x6a,  7,  7,  CHG_NZV, cpu6811, 0 },
    635. 

  635.   { "dec", OP_IND16,             3, 0x73,  4,  4,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    636. 

  636.   { "dec", OP_IDX,               2, 0x63,  3,  3,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    637. 

  637.   { "dec", OP_IDX_1,             3, 0x63,  4,  4,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    638. 

  638.   { "dec", OP_IDX_2,             4, 0x63,  5,  5,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    639. 

  639.   { "dec", OP_D_IDX,             2, 0x63,  6,  6,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    640. 

  640.   { "dec", OP_D_IDX_2,           4, 0x63,  6,  6,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    641. 

  641. 

  642.   { "des",  OP_NONE,             1, 0x34,  3,  3,  CHG_NONE, cpu6811, 0 },
    643. 

  643. 

  644.   { "deca", OP_NONE,             1, 0x4a,  2,  2,  CHG_NZV, cpu6811, 0 },
    645. 

  645.   { "deca", OP_NONE,             1, 0x43,  1,  1,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    646. 

  646.   { "decb", OP_NONE,             1, 0x5a,  2,  2,  CHG_NZV, cpu6811, 0 },
    647. 

  647.   { "decb", OP_NONE,             1, 0x53,  1,  1,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    648. 

  648. 

  649.   { "decw",  OP_IND16 | OP_PAGE2,          3, 0x73,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    650. 

  650.   { "decw",  OP_IDX | OP_PAGE2,            2, 0x63,  3,  3,  CHG_NZV, cpu9s12x, 0 },
    651. 

  651.   { "decw",  OP_IDX_1 | OP_PAGE2,          3, 0x63,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    652. 

  652.   { "decw",  OP_IDX_2 | OP_PAGE2,          4, 0x63,  5,  5,  CHG_NZV, cpu9s12x, 0 },
    653. 

  653.   { "decw",  OP_D_IDX | OP_PAGE2,          2, 0x63,  6,  6,  CHG_NZV, cpu9s12x, 0 },
    654. 

  654.   { "decw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x63,  6,  6,  CHG_NZV, cpu9s12x, 0 },
    655. 

  655. 

  656.   { "decx",  OP_NONE | OP_PAGE2,          3, 0x43,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    657. 

  657. 

  658.   { "decy",  OP_NONE | OP_PAGE2,          3, 0x53,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    659. 

  659. 

  660.   { "dex",  OP_NONE,             1, 0x09,  1,  1,  CHG_Z, cpu6812|cpu9s12x|cpu6811, 0 },
    661. 

  661.   { "dey",  OP_NONE | OP_PAGE2,  2, 0x09,  4,  4,  CHG_Z, cpu6811, 0 },
    662. 

  662.   { "dey",  OP_NONE,             1, 0x03,  1,  1,  CHG_Z, cpu6812|cpu9s12x, 0 },
    663. 

  663. 

  664.   { "ediv", OP_NONE,             1, 0x11,  11,  11,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    665. 

  665.   { "edivs", OP_NONE | OP_PAGE2, 2, 0x14,  12,  12,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    666. 

  666.   { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12,  13,  13,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    667. 

  667. 

  668.   { "emaxd", OP_IDX | OP_PAGE2,     3, 0x1a,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    669. 

  669.   { "emaxd", OP_IDX_1 | OP_PAGE2,   4, 0x1a,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    670. 

  670.   { "emaxd", OP_IDX_2 | OP_PAGE2,   5, 0x1a,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    671. 

  671.   { "emaxd", OP_D_IDX | OP_PAGE2,   3, 0x1a,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    672. 

  672.   { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    673. 

  673. 

  674.   { "emaxm", OP_IDX | OP_PAGE2,     3, 0x1e,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    675. 

  675.   { "emaxm", OP_IDX_1 | OP_PAGE2,   4, 0x1e,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    676. 

  676.   { "emaxm", OP_IDX_2 | OP_PAGE2,   5, 0x1e,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    677. 

  677.   { "emaxm", OP_D_IDX | OP_PAGE2,   3, 0x1e,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    678. 

  678.   { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    679. 

  679. 

  680.   { "emind", OP_IDX | OP_PAGE2,     3, 0x1b,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    681. 

  681.   { "emind", OP_IDX_1 | OP_PAGE2,   4, 0x1b,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    682. 

  682.   { "emind", OP_IDX_2 | OP_PAGE2,   5, 0x1b,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    683. 

  683.   { "emind", OP_D_IDX | OP_PAGE2,   3, 0x1b,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    684. 

  684.   { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    685. 

  685. 

  686.   { "eminm", OP_IDX | OP_PAGE2,     3, 0x1f,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    687. 

  687.   { "eminm", OP_IDX_1 | OP_PAGE2,   4, 0x1f,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    688. 

  688.   { "eminm", OP_IDX_2 | OP_PAGE2,   5, 0x1f,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    689. 

  689.   { "eminm", OP_D_IDX | OP_PAGE2,   3, 0x1f,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    690. 

  690.   { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    691. 

  691. 

  692.   { "emul",  OP_NONE,               1, 0x13,  3,  3,  CHG_NZC, cpu6812|cpu9s12x, 0 },
    693. 

  693.   { "emuls", OP_NONE | OP_PAGE2,    2, 0x13,  3,  3,  CHG_NZC, cpu6812|cpu9s12x, 0 },
    694. 

  694. 

  695.   { "eora", OP_IMM8,         2, 0x88,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    696. 

  696.   { "eora", OP_DIRECT,       2, 0x98,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    697. 

  697.   { "eora", OP_IND16,        3, 0xb8,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    698. 

  698.   { "eora", OP_IX,             2, 0xa8,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    699. 

  699.   { "eora", OP_IY | OP_PAGE2,  3, 0xa8,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    700. 

  700.   { "eora", OP_IDX,            2, 0xa8,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    701. 

  701.   { "eora", OP_IDX_1,          3, 0xa8,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    702. 

  702.   { "eora", OP_IDX_2,          4, 0xa8,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    703. 

  703.   { "eora", OP_D_IDX,          2, 0xa8,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    704. 

  704.   { "eora", OP_D_IDX_2,        4, 0xa8,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    705. 

  705. 

  706.   { "eorb", OP_IMM8,         2, 0xc8,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    707. 

  707.   { "eorb", OP_DIRECT,       2, 0xd8,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    708. 

  708.   { "eorb", OP_IND16,        3, 0xf8,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    709. 

  709.   { "eorb", OP_IX,             2, 0xe8,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    710. 

  710.   { "eorb", OP_IY | OP_PAGE2,  3, 0xe8,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    711. 

  711.   { "eorb", OP_IDX,            2, 0xe8,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    712. 

  712.   { "eorb", OP_IDX_1,          3, 0xe8,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    713. 

  713.   { "eorb", OP_IDX_2,          4, 0xe8,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    714. 

  714.   { "eorb", OP_D_IDX,          2, 0xe8,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    715. 

  715.   { "eorb", OP_D_IDX_2,        4, 0xe8,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    716. 

  716. 

  717.   { "eorx", OP_IMM16 | OP_PAGE2,         2, 0x88,  1,  1,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    718. 

  718.   { "eorx", OP_DIRECT | OP_PAGE2,       2, 0x98,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    719. 

  719.   { "eorx", OP_IND16 | OP_PAGE2,        3, 0xb8,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    720. 

  720.   { "eorx", OP_IDX | OP_PAGE2,            2, 0xa8,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    721. 

  721.   { "eorx", OP_IDX_1 | OP_PAGE2,          3, 0xa8,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    722. 

  722.   { "eorx", OP_IDX_2 | OP_PAGE2,          4, 0xa8,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    723. 

  723.   { "eorx", OP_D_IDX | OP_PAGE2,          2, 0xa8,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    724. 

  724.   { "eorx", OP_D_IDX_2 | OP_PAGE2,        4, 0xa8,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    725. 

  725. 

  726.   { "eory", OP_IMM16 | OP_PAGE2,         2, 0xc8,  1,  1,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    727. 

  727.   { "eory", OP_DIRECT | OP_PAGE2,       2, 0xd8,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    728. 

  728.   { "eory", OP_IND16 | OP_PAGE2,        3, 0xf8,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    729. 

  729.   { "eory", OP_IDX | OP_PAGE2,            2, 0xe8,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    730. 

  730.   { "eory", OP_IDX_1 | OP_PAGE2,          3, 0xe8,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    731. 

  731.   { "eory", OP_IDX_2 | OP_PAGE2,          4, 0xe8,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    732. 

  732.   { "eory", OP_D_IDX | OP_PAGE2,          2, 0xe8,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    733. 

  733.   { "eory", OP_D_IDX_2 | OP_PAGE2,        4, 0xe8,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    734. 

  734. 

  735.   { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10,  CHG_NZC, cpu6812|cpu9s12x, 0 },
    736. 

  736. 

  737. /* S12X has more exg variants, most are pointless so not supported */
    738. 

  738.   { "exg",  OP_EXG_MARKER
    739. 

  739.           | OP_REG | OP_REG_2, 2, 0xb7, 1, 1,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    740. 

  740. 

  741.   { "fdiv", OP_NONE,             1, 0x03,  3, 41, CHG_ZVC, cpu6811, 0 },
    742. 

  742.   { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812|cpu9s12x, 0 },
    743. 

  743. 

  744.   { "gldaa", OP_DIRECT | OP_PAGE2,       2, 0x96,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    745. 

  745.   { "gldaa", OP_IND16 | OP_PAGE2,        3, 0xb6,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    746. 

  746.   { "gldaa", OP_IDX | OP_PAGE2,            2, 0xa6,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    747. 

  747.   { "gldaa", OP_IDX_1 | OP_PAGE2,          3, 0xa6,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    748. 

  748.   { "gldaa", OP_IDX_2 | OP_PAGE2,          4, 0xa6,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    749. 

  749.   { "gldaa", OP_D_IDX | OP_PAGE2,          2, 0xa6,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    750. 

  750.   { "gldaa", OP_D_IDX_2 | OP_PAGE2,        4, 0xa6,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    751. 

  751. 

  752.   { "gldab", OP_DIRECT | OP_PAGE2,       2, 0xd6,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    753. 

  753.   { "gldab", OP_IND16 | OP_PAGE2,        3, 0xf6,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    754. 

  754.   { "gldab", OP_IDX | OP_PAGE2,            2, 0xe6,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    755. 

  755.   { "gldab", OP_IDX_1 | OP_PAGE2,          3, 0xe6,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    756. 

  756.   { "gldab", OP_IDX_2 | OP_PAGE2,          4, 0xe6,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    757. 

  757.   { "gldab", OP_D_IDX | OP_PAGE2,          2, 0xe6,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    758. 

  758.   { "gldab", OP_D_IDX_2 | OP_PAGE2,        4, 0xe6,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    759. 

  759. 

  760.   { "gldd", OP_DIRECT | OP_PAGE2,       2, 0xdc,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    761. 

  761.   { "gldd", OP_IND16 | OP_PAGE2,        3, 0xfc,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    762. 

  762.   { "gldd", OP_IDX | OP_PAGE2,            2, 0xec,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    763. 

  763.   { "gldd", OP_IDX_1 | OP_PAGE2,          3, 0xec,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    764. 

  764.   { "gldd", OP_IDX_2 | OP_PAGE2,          4, 0xec,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    765. 

  765.   { "gldd", OP_D_IDX | OP_PAGE2,          2, 0xec,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    766. 

  766.   { "gldd", OP_D_IDX_2 | OP_PAGE2,        4, 0xec,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    767. 

  767. 

  768.   { "glds", OP_DIRECT | OP_PAGE2,       2, 0xdf,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    769. 

  769.   { "glds", OP_IND16 | OP_PAGE2,        3, 0xff,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    770. 

  770.   { "glds", OP_IDX | OP_PAGE2,            2, 0xef,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    771. 

  771.   { "glds", OP_IDX_1 | OP_PAGE2,          3, 0xef,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    772. 

  772.   { "glds", OP_IDX_2 | OP_PAGE2,          4, 0xef,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    773. 

  773.   { "glds", OP_D_IDX | OP_PAGE2,          2, 0xef,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    774. 

  774.   { "glds", OP_D_IDX_2 | OP_PAGE2,        4, 0xef,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    775. 

  775. 

  776.   { "gldx", OP_DIRECT | OP_PAGE2,       2, 0xde,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    777. 

  777.   { "gldx", OP_IND16 | OP_PAGE2,        3, 0xfe,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    778. 

  778.   { "gldx", OP_IDX | OP_PAGE2,            2, 0xee,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    779. 

  779.   { "gldx", OP_IDX_1 | OP_PAGE2,          3, 0xee,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    780. 

  780.   { "gldx", OP_IDX_2 | OP_PAGE2,          4, 0xee,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    781. 

  781.   { "gldx", OP_D_IDX | OP_PAGE2,          2, 0xee,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    782. 

  782.   { "gldx", OP_D_IDX_2 | OP_PAGE2,        4, 0xee,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    783. 

  783. 

  784.   { "gldy", OP_DIRECT | OP_PAGE2,       2, 0xdd,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    785. 

  785.   { "gldy", OP_IND16 | OP_PAGE2,        3, 0xfd,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    786. 

  786.   { "gldy", OP_IDX | OP_PAGE2,            2, 0xed,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    787. 

  787.   { "gldy", OP_IDX_1 | OP_PAGE2,          3, 0xed,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    788. 

  788.   { "gldy", OP_IDX_2 | OP_PAGE2,          4, 0xed,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    789. 

  789.   { "gldy", OP_D_IDX | OP_PAGE2,          2, 0xed,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    790. 

  790.   { "gldy", OP_D_IDX_2 | OP_PAGE2,        4, 0xed,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    791. 

  791. 

  792.   { "gstaa", OP_DIRECT | OP_PAGE2,       2, 0x5a,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    793. 

  793.   { "gstaa", OP_IND16 | OP_PAGE2,        3, 0x7a,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    794. 

  794.   { "gstaa", OP_IDX | OP_PAGE2,            2, 0x6a,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    795. 

  795.   { "gstaa", OP_IDX_1 | OP_PAGE2,          3, 0x6a,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    796. 

  796.   { "gstaa", OP_IDX_2 | OP_PAGE2,          4, 0x6a,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    797. 

  797.   { "gstaa", OP_D_IDX | OP_PAGE2,          2, 0x6a,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    798. 

  798.   { "gstaa", OP_D_IDX_2 | OP_PAGE2,        4, 0x6a,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    799. 

  799. 

  800.   { "gstab", OP_DIRECT | OP_PAGE2,       2, 0x5b,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    801. 

  801.   { "gstab", OP_IND16 | OP_PAGE2,        3, 0x7b,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    802. 

  802.   { "gstab", OP_IDX | OP_PAGE2,            2, 0x6b,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    803. 

  803.   { "gstab", OP_IDX_1 | OP_PAGE2,          3, 0x6b,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    804. 

  804.   { "gstab", OP_IDX_2 | OP_PAGE2,          4, 0x6b,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    805. 

  805.   { "gstab", OP_D_IDX | OP_PAGE2,          2, 0x6b,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    806. 

  806.   { "gstab", OP_D_IDX_2 | OP_PAGE2,        4, 0x6b,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    807. 

  807. 

  808.   { "gstd", OP_DIRECT | OP_PAGE2,       2, 0x5c,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    809. 

  809.   { "gstd", OP_IND16 | OP_PAGE2,        3, 0x7c,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    810. 

  810.   { "gstd", OP_IDX | OP_PAGE2,            2, 0x6c,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    811. 

  811.   { "gstd", OP_IDX_1 | OP_PAGE2,          3, 0x6c,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    812. 

  812.   { "gstd", OP_IDX_2 | OP_PAGE2,          4, 0x6c,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    813. 

  813.   { "gstd", OP_D_IDX | OP_PAGE2,          2, 0x6c,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    814. 

  814.   { "gstd", OP_D_IDX_2 | OP_PAGE2,        4, 0x6c,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    815. 

  815. 

  816.   { "gsts", OP_DIRECT | OP_PAGE2,       2, 0x5f,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    817. 

  817.   { "gsts", OP_IND16 | OP_PAGE2,        3, 0x6f,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    818. 

  818.   { "gsts", OP_IDX | OP_PAGE2,            2, 0x6f,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    819. 

  819.   { "gsts", OP_IDX_1 | OP_PAGE2,          3, 0x6f,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    820. 

  820.   { "gsts", OP_IDX_2 | OP_PAGE2,          4, 0x6f,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    821. 

  821.   { "gsts", OP_D_IDX | OP_PAGE2,          2, 0x6f,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    822. 

  822.   { "gsts", OP_D_IDX_2 | OP_PAGE2,        4, 0x6f,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    823. 

  823. 

  824.   { "gstx", OP_DIRECT | OP_PAGE2,       2, 0x5e,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    825. 

  825.   { "gstx", OP_IND16 | OP_PAGE2,        3, 0x7e,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    826. 

  826.   { "gstx", OP_IDX | OP_PAGE2,            2, 0x6e,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    827. 

  827.   { "gstx", OP_IDX_1 | OP_PAGE2,          3, 0x6e,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    828. 

  828.   { "gstx", OP_IDX_2 | OP_PAGE2,          4, 0x6e,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    829. 

  829.   { "gstx", OP_D_IDX | OP_PAGE2,          2, 0x6e,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    830. 

  830.   { "gstx", OP_D_IDX_2 | OP_PAGE2,        4, 0x6e,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    831. 

  831. 

  832.   { "gsty", OP_DIRECT | OP_PAGE2,       2, 0x5d,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    833. 

  833.   { "gsty", OP_IND16 | OP_PAGE2,        3, 0x7d,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    834. 

  834.   { "gsty", OP_IDX | OP_PAGE2,            2, 0x6d,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    835. 

  835.   { "gsty", OP_IDX_1 | OP_PAGE2,          3, 0x6d,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    836. 

  836.   { "gsty", OP_IDX_2 | OP_PAGE2,          4, 0x6d,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    837. 

  837.   { "gsty", OP_D_IDX | OP_PAGE2,          2, 0x6d,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    838. 

  838.   { "gsty", OP_D_IDX_2 | OP_PAGE2,        4, 0x6d,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    839. 

  839. 

  840.   { "ibeq", OP_IBEQ_MARKER
    841. 

  841.           | OP_REG | OP_JUMP_REL,  3, 0x04,  3,  3, CHG_NONE, cpu6812|cpu9s12x, 0 },
    842. 

  842.   { "ibne", OP_IBNE_MARKER
    843. 

  843.           | OP_REG | OP_JUMP_REL,  3, 0x04,  3,  3, CHG_NONE, cpu6812|cpu9s12x, 0 },
    844. 

  844. 

  845.   { "idiv",  OP_NONE,              1, 0x02,  3, 41, CLR_V_CHG_ZC, cpu6811, 0 },
    846. 

  846.   { "idiv",  OP_NONE | OP_PAGE2,  2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812|cpu9s12x, 0 },
    847. 

  847.   { "idivs", OP_NONE | OP_PAGE2,  2, 0x15, 12, 12, CHG_NZVC, cpu6812|cpu9s12x, 0 },
    848. 

  848. 

  849.   { "inc", OP_IX,                  2, 0x6c,  6,  6,  CHG_NZV, cpu6811, 0 },
    850. 

  850.   { "inc", OP_IND16,               3, 0x7c,  6,  6,  CHG_NZV, cpu6811, 0 },
    851. 

  851.   { "inc", OP_IY | OP_PAGE2,       3, 0x6c,  7,  7,  CHG_NZV, cpu6811, 0 },
    852. 

  852.   { "inc", OP_IND16,               3, 0x72,  4,  4,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    853. 

  853.   { "inc", OP_IDX,                 2, 0x62,  3,  3,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    854. 

  854.   { "inc", OP_IDX_1,               3, 0x62,  4,  4,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    855. 

  855.   { "inc", OP_IDX_2,               4, 0x62,  5,  5,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    856. 

  856.   { "inc", OP_D_IDX,               2, 0x62,  6,  6,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    857. 

  857.   { "inc", OP_D_IDX_2,             4, 0x62,  6,  6,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    858. 

  858. 

  859.   { "inca", OP_NONE,               1, 0x4c,  2,  2,  CHG_NZV, cpu6811, 0 },
    860. 

  860.   { "inca", OP_NONE,               1, 0x42,  1,  1,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    861. 

  861.   { "incb", OP_NONE,               1, 0x5c,  2,  2,  CHG_NZV, cpu6811, 0 },
    862. 

  862.   { "incb", OP_NONE,               1, 0x52,  1,  1,  CHG_NZV, cpu6812|cpu9s12x, 0 },
    863. 

  863. 

  864.   { "incw",  OP_IND16 | OP_PAGE2,          3, 0x72,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    865. 

  865.   { "incw",  OP_IDX | OP_PAGE2,            2, 0x62,  3,  3,  CHG_NZV, cpu9s12x, 0 },
    866. 

  866.   { "incw",  OP_IDX_1 | OP_PAGE2,          3, 0x62,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    867. 

  867.   { "incw",  OP_IDX_2 | OP_PAGE2,          4, 0x62,  5,  5,  CHG_NZV, cpu9s12x, 0 },
    868. 

  868.   { "incw",  OP_D_IDX | OP_PAGE2,          2, 0x62,  6,  6,  CHG_NZV, cpu9s12x, 0 },
    869. 

  869.   { "incw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x62,  6,  6,  CHG_NZV, cpu9s12x, 0 },
    870. 

  870. 

  871.   { "incx",  OP_NONE | OP_PAGE2,          3, 0x42,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    872. 

  872. 

  873.   { "incy",  OP_NONE | OP_PAGE2,          3, 0x52,  4,  4,  CHG_NZV, cpu9s12x, 0 },
    874. 

  874. 

  875.   { "ins",  OP_NONE,               1, 0x31,  3,  3,  CHG_NONE, cpu6811, 0 },
    876. 

  876. 

  877.   { "inx",  OP_NONE,               1, 0x08,  1,  1,  CHG_Z, cpu6811|cpu6812|cpu9s12x, 0 },
    878. 

  878.   { "iny",  OP_NONE |OP_PAGE2,     2, 0x08,  4,  4,  CHG_Z, cpu6811, 0 },
    879. 

  879.   { "iny",  OP_NONE,               1, 0x02,  1,  1,  CHG_Z, cpu6812|cpu9s12x, 0 },
    880. 

  880. 

  881.   { "jmp",  OP_IND16 | OP_BRANCH,  3, 0x7e,  3,  3,  CHG_NONE, cpu6811, 0 },
    882. 

  882.   { "jmp",  OP_IX,                 2, 0x6e,  3,  3,  CHG_NONE, cpu6811, 0 },
    883. 

  883.   { "jmp",  OP_IY | OP_PAGE2,      3, 0x6e,  4,  4,  CHG_NONE, cpu6811, 0 },
    884. 

  884.   { "jmp",  OP_IND16 | OP_BRANCH,  3, 0x06,  3,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    885. 

  885.   { "jmp",  OP_IDX,                2, 0x05,  3,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    886. 

  886.   { "jmp",  OP_IDX_1,              3, 0x05,  3,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    887. 

  887.   { "jmp",  OP_IDX_2,              4, 0x05,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    888. 

  888.   { "jmp",  OP_D_IDX,              2, 0x05,  6,  6,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    889. 

  889.   { "jmp",  OP_D_IDX_2,            4, 0x05,  6,  6,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    890. 

  890. 

  891.   { "jsr",  OP_DIRECT | OP_BRANCH, 2, 0x9d,  5,  5,  CHG_NONE, cpu6811, 0 },
    892. 

  892.   { "jsr",  OP_IND16 | OP_BRANCH,  3, 0xbd,  6,  6,  CHG_NONE, cpu6811, 0 },
    893. 

  893.   { "jsr",  OP_IX,                 2, 0xad,  6,  6,  CHG_NONE, cpu6811, 0 },
    894. 

  894.   { "jsr",  OP_IY | OP_PAGE2,      3, 0xad,  6,  6,  CHG_NONE, cpu6811, 0 },
    895. 

  895.   { "jsr",  OP_DIRECT | OP_BRANCH, 2, 0x17,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    896. 

  896.   { "jsr",  OP_IND16 | OP_BRANCH,  3, 0x16,  4,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    897. 

  897.   { "jsr",  OP_IDX,                2, 0x15,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    898. 

  898.   { "jsr",  OP_IDX_1,              3, 0x15,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    899. 

  899.   { "jsr",  OP_IDX_2,              4, 0x15,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    900. 

  900.   { "jsr",  OP_D_IDX,              2, 0x15,  7,  7,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    901. 

  901.   { "jsr",  OP_D_IDX_2,            4, 0x15,  7,  7,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    902. 

  902. 

  903.   { "lbcc", OP_JUMP_REL16 | OP_PAGE2,  4, 0x24,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    904. 

  904.   { "lbcs", OP_JUMP_REL16 | OP_PAGE2,  4, 0x25,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    905. 

  905.   { "lbeq", OP_JUMP_REL16 | OP_PAGE2,  4, 0x27,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    906. 

  906.   { "lbge", OP_JUMP_REL16 | OP_PAGE2,  4, 0x2c,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    907. 

  907.   { "lbgt", OP_JUMP_REL16 | OP_PAGE2,  4, 0x2e,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    908. 

  908.   { "lbhi", OP_JUMP_REL16 | OP_PAGE2,  4, 0x22,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    909. 

  909.   { "lbhs", OP_JUMP_REL16 | OP_PAGE2,  4, 0x24,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    910. 

  910.   { "lble", OP_JUMP_REL16 | OP_PAGE2,  4, 0x2f,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    911. 

  911.   { "lblo", OP_JUMP_REL16 | OP_PAGE2,  4, 0x25,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    912. 

  912.   { "lbls", OP_JUMP_REL16 | OP_PAGE2,  4, 0x23,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    913. 

  913.   { "lblt", OP_JUMP_REL16 | OP_PAGE2,  4, 0x2d,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    914. 

  914.   { "lbmi", OP_JUMP_REL16 | OP_PAGE2,  4, 0x2b,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    915. 

  915.   { "lbne", OP_JUMP_REL16 | OP_PAGE2,  4, 0x26,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    916. 

  916.   { "lbpl", OP_JUMP_REL16 | OP_PAGE2,  4, 0x2a,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    917. 

  917.   { "lbra", OP_JUMP_REL16 | OP_PAGE2,  4, 0x20,  4,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    918. 

  918.   { "lbrn", OP_JUMP_REL16 | OP_PAGE2,  4, 0x21,  3,  3, CHG_NONE, cpu6812|cpu9s12x, 0 },
    919. 

  919.   { "lbvc", OP_JUMP_REL16 | OP_PAGE2,  4, 0x28,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    920. 

  920.   { "lbvs", OP_JUMP_REL16 | OP_PAGE2,  4, 0x29,  3,  4, CHG_NONE, cpu6812|cpu9s12x, 0 },
    921. 

  921. 

  922.   { "ldaa", OP_IMM8,         2, 0x86,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    923. 

  923.   { "ldaa", OP_DIRECT,       2, 0x96,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    924. 

  924.   { "ldaa", OP_IND16,        3, 0xb6,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    925. 

  925.   { "ldaa", OP_IX,             2, 0xa6,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    926. 

  926.   { "ldaa", OP_IY | OP_PAGE2,  3, 0xa6,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    927. 

  927.   { "ldaa", OP_IDX,            2, 0xa6,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    928. 

  928.   { "ldaa", OP_IDX_1,          3, 0xa6,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    929. 

  929.   { "ldaa", OP_IDX_2,          4, 0xa6,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    930. 

  930.   { "ldaa", OP_D_IDX,          2, 0xa6,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    931. 

  931.   { "ldaa", OP_D_IDX_2,        4, 0xa6,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    932. 

  932. 

  933.   { "ldab", OP_IMM8,         2, 0xc6,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    934. 

  934.   { "ldab", OP_DIRECT,       2, 0xd6,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    935. 

  935.   { "ldab", OP_IND16,        3, 0xf6,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    936. 

  936.   { "ldab", OP_IX,             2, 0xe6,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    937. 

  937.   { "ldab", OP_IY | OP_PAGE2,  3, 0xe6,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    938. 

  938.   { "ldab", OP_IDX,            2, 0xe6,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    939. 

  939.   { "ldab", OP_IDX_1,          3, 0xe6,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    940. 

  940.   { "ldab", OP_IDX_2,          4, 0xe6,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    941. 

  941.   { "ldab", OP_D_IDX,          2, 0xe6,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    942. 

  942.   { "ldab", OP_D_IDX_2,        4, 0xe6,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    943. 

  943. 

  944.   { "ldd", OP_IMM16,         3, 0xcc,  2,  2,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    945. 

  945.   { "ldd", OP_DIRECT,        2, 0xdc,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    946. 

  946.   { "ldd", OP_IND16,         3, 0xfc,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    947. 

  947.   { "ldd", OP_IX,              2, 0xec,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    948. 

  948.   { "ldd", OP_IY | OP_PAGE2,   3, 0xec,  6,  6,  CLR_V_CHG_NZ, cpu6811, 0 },
    949. 

  949.   { "ldd", OP_IDX,             2, 0xec,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    950. 

  950.   { "ldd", OP_IDX_1,           3, 0xec,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    951. 

  951.   { "ldd", OP_IDX_2,           4, 0xec,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    952. 

  952.   { "ldd", OP_D_IDX,           2, 0xec,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    953. 

  953.   { "ldd", OP_D_IDX_2,         4, 0xec,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    954. 

  954. 

  955.   { "lds",  OP_IMM16,          3, 0x8e,  3,  3,  CLR_V_CHG_NZ, cpu6811, 0 },
    956. 

  956.   { "lds",  OP_DIRECT,         2, 0x9e,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    957. 

  957.   { "lds",  OP_IND16,          3, 0xbe,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    958. 

  958.   { "lds",  OP_IX,             2, 0xae,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    959. 

  959.   { "lds",  OP_IY | OP_PAGE2,  3, 0xae,  6,  6,  CLR_V_CHG_NZ, cpu6811, 0 },
    960. 

  960.   { "lds",  OP_IMM16,          3, 0xcf,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    961. 

  961.   { "lds",  OP_DIRECT,         2, 0xdf,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    962. 

  962.   { "lds",  OP_IND16,          3, 0xff,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    963. 

  963.   { "lds",  OP_IDX,            2, 0xef,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    964. 

  964.   { "lds",  OP_IDX_1,          3, 0xef,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    965. 

  965.   { "lds",  OP_IDX_2,          4, 0xef,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    966. 

  966.   { "lds",  OP_D_IDX,          2, 0xef,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    967. 

  967.   { "lds",  OP_D_IDX_2,        4, 0xef,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    968. 

  968. 

  969.   { "ldx",  OP_IMM16,        3, 0xce,  2,  2,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    970. 

  970.   { "ldx",  OP_DIRECT,       2, 0xde,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    971. 

  971.   { "ldx",  OP_IND16,        3, 0xfe,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    972. 

  972.   { "ldx",  OP_IX,             2, 0xee,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    973. 

  973.   { "ldx",  OP_IY | OP_PAGE4,  3, 0xee,  6,  6,  CLR_V_CHG_NZ, cpu6811, 0 },
    974. 

  974.   { "ldx",  OP_IDX,            2, 0xee,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    975. 

  975.   { "ldx",  OP_IDX_1,          3, 0xee,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    976. 

  976.   { "ldx",  OP_IDX_2,          4, 0xee,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    977. 

  977.   { "ldx",  OP_D_IDX,          2, 0xee,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    978. 

  978.   { "ldx",  OP_D_IDX_2,        4, 0xee,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    979. 

  979. 

  980.   { "ldy",  OP_IMM16 | OP_PAGE2,  4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },
    981. 

  981.   { "ldy",  OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
    982. 

  982.   { "ldy",  OP_IND16 | OP_PAGE2,  4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
    983. 

  983.   { "ldy",  OP_IX | OP_PAGE3,     3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
    984. 

  984.   { "ldy",  OP_IY | OP_PAGE2,     3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
    985. 

  985.   { "ldy",  OP_IMM16,          3, 0xcd,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    986. 

  986.   { "ldy",  OP_DIRECT,         2, 0xdd,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    987. 

  987.   { "ldy",  OP_IND16,          3, 0xfd,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    988. 

  988.   { "ldy",  OP_IDX,            2, 0xed,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    989. 

  989.   { "ldy",  OP_IDX_1,          3, 0xed,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    990. 

  990.   { "ldy",  OP_IDX_2,          4, 0xed,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    991. 

  991.   { "ldy",  OP_D_IDX,          2, 0xed,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    992. 

  992.   { "ldy",  OP_D_IDX_2,        4, 0xed,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    993. 

  993. 

  994.   { "leas", OP_IDX,            2, 0x1b,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    995. 

  995.   { "leas", OP_IDX_1,          3, 0x1b,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    996. 

  996.   { "leas", OP_IDX_2,          4, 0x1b,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    997. 

  997. 

  998.   { "leax", OP_IDX,            2, 0x1a,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    999. 

  999.   { "leax", OP_IDX_1,          3, 0x1a,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1000. 

  1000.   { "leax", OP_IDX_2,          4, 0x1a,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1001. 

  1001. 

  1002.   { "leay", OP_IDX,            2, 0x19,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1003. 

  1003.   { "leay", OP_IDX_1,          3, 0x19,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1004. 

  1004.   { "leay", OP_IDX_2,          4, 0x19,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1005. 

  1005. 

  1006.   { "lsl",  OP_IND16,          3, 0x78,  4,  4,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1007. 

  1007.   { "lsl",  OP_IX,             2, 0x68,  6,  6,  CHG_NZVC, cpu6811, 0 },
    1008. 

  1008.   { "lsl",  OP_IY | OP_PAGE2,  3, 0x68,  7,  7,  CHG_NZVC, cpu6811, 0 },
    1009. 

  1009.   { "lsl",  OP_IDX,            2, 0x68,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1010. 

  1010.   { "lsl",  OP_IDX_1,          3, 0x68,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1011. 

  1011.   { "lsl",  OP_IDX_2,          4, 0x68,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1012. 

  1012.   { "lsl",  OP_D_IDX,          2, 0x68,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1013. 

  1013.   { "lsl",  OP_D_IDX_2,        4, 0x68,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1014. 

  1014. 

  1015.   { "lsla", OP_NONE,           1, 0x48,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1016. 

  1016.   { "lslb", OP_NONE,           1, 0x58,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1017. 

  1017.   { "lsld", OP_NONE,           1, 0x05,  3,  3,  CHG_NZVC, cpu6811, 0 },
    1018. 

  1018.   { "lsld", OP_NONE,           1, 0x59,  1,  1,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1019. 

  1019. /* lslw is the same as aslw. */
    1020. 

  1020.   { "lslw",  OP_IND16 | OP_PAGE2,          3, 0x78,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1021. 

  1021.   { "lslw",  OP_IDX | OP_PAGE2,            2, 0x68,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1022. 

  1022.   { "lslw",  OP_IDX_1 | OP_PAGE2,          3, 0x68,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1023. 

  1023.   { "lslw",  OP_IDX_2 | OP_PAGE2,          4, 0x68,  5,  5,  CHG_NZVC, cpu9s12x, 0 },
    1024. 

  1024.   { "lslw",  OP_D_IDX | OP_PAGE2,          2, 0x68,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1025. 

  1025.   { "lslw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x68,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1026. 

  1026. /* lslx is same as aslx. */
    1027. 

  1027.   { "lslx", OP_NONE | OP_PAGE2,           1, 0x48,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1028. 

  1028. /* lsly is the same as asly. */
    1029. 

  1029.   { "lsly", OP_NONE | OP_PAGE2,           1, 0x58,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1030. 

  1030. 

  1031.   { "lsr",  OP_IND16,        3, 0x74,  4,  4,  CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1032. 

  1032.   { "lsr",  OP_IX,             2, 0x64,  6,  6,  CLR_N_CHG_ZVC, cpu6811, 0 },
    1033. 

  1033.   { "lsr",  OP_IY | OP_PAGE2,  3, 0x64,  7,  7,  CLR_V_CHG_ZVC, cpu6811, 0 },
    1034. 

  1034.   { "lsr",  OP_IDX,            2, 0x64,  3,  3,  CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
    1035. 

  1035.   { "lsr",  OP_IDX_1,          3, 0x64,  4,  4,  CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
    1036. 

  1036.   { "lsr",  OP_IDX_2,          4, 0x64,  5,  5,  CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
    1037. 

  1037.   { "lsr",  OP_D_IDX,          2, 0x64,  6,  6,  CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
    1038. 

  1038.   { "lsr",  OP_D_IDX_2,        4, 0x64,  6,  6,  CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
    1039. 

  1039. 

  1040.   { "lsra", OP_NONE,         1, 0x44,  1,  1,  CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1041. 

  1041.   { "lsrb", OP_NONE,         1, 0x54,  1,  1,  CLR_N_CHG_ZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1042. 

  1042.   { "lsrd", OP_NONE,           1, 0x04,  3,  3,  CLR_N_CHG_ZVC, cpu6811, 0 },
    1043. 

  1043.   { "lsrd", OP_NONE,           1, 0x49,  1,  1,  CLR_N_CHG_ZVC, cpu6812|cpu9s12x, 0 },
    1044. 

  1044. 

  1045.   { "lsrw",  OP_IND16 | OP_PAGE2,          3, 0x74,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1046. 

  1046.   { "lsrw",  OP_IDX | OP_PAGE2,            2, 0x64,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1047. 

  1047.   { "lsrw",  OP_IDX_1 | OP_PAGE2,          3, 0x64,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1048. 

  1048.   { "lsrw",  OP_IDX_2 | OP_PAGE2,          4, 0x64,  5,  5,  CHG_NZVC, cpu9s12x, 0 },
    1049. 

  1049.   { "lsrw",  OP_D_IDX | OP_PAGE2,          2, 0x64,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1050. 

  1050.   { "lsrw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x64,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1051. 

  1051. 

  1052.   { "lsrx", OP_NONE | OP_PAGE2,           1, 0x44,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1053. 

  1053. 

  1054.   { "lsry", OP_NONE | OP_PAGE2,           1, 0x54,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1055. 

  1055. 

  1056.   { "maxa", OP_IDX | OP_PAGE2,     3, 0x18,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1057. 

  1057.   { "maxa", OP_IDX_1 | OP_PAGE2,   4, 0x18,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1058. 

  1058.   { "maxa", OP_IDX_2 | OP_PAGE2,   5, 0x18,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1059. 

  1059.   { "maxa", OP_D_IDX | OP_PAGE2,   3, 0x18,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1060. 

  1060.   { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1061. 

  1061. 

  1062.   { "maxm", OP_IDX | OP_PAGE2,     3, 0x1c,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1063. 

  1063.   { "maxm", OP_IDX_1 | OP_PAGE2,   4, 0x1c,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1064. 

  1064.   { "maxm", OP_IDX_2 | OP_PAGE2,   5, 0x1c,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1065. 

  1065.   { "maxm", OP_D_IDX | OP_PAGE2,   3, 0x1c,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1066. 

  1066.   { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1067. 

  1067. 

  1068.   { "mem",  OP_NONE,                1, 0x01,  5,  5,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    1069. 

  1069. 

  1070.   { "mina", OP_IDX | OP_PAGE2,     3, 0x19,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1071. 

  1071.   { "mina", OP_IDX_1 | OP_PAGE2,   4, 0x19,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1072. 

  1072.   { "mina", OP_IDX_2 | OP_PAGE2,   5, 0x19,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1073. 

  1073.   { "mina", OP_D_IDX | OP_PAGE2,   3, 0x19,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1074. 

  1074.   { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1075. 

  1075. 

  1076.   { "minm", OP_IDX | OP_PAGE2,     3, 0x1d,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1077. 

  1077.   { "minm", OP_IDX_1 | OP_PAGE2,   4, 0x1d,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1078. 

  1078.   { "minm", OP_IDX_2 | OP_PAGE2,   5, 0x1d,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1079. 

  1079.   { "minm", OP_D_IDX | OP_PAGE2,   3, 0x1d,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1080. 

  1080.   { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d,  7,  7,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1081. 

  1081. 

  1082. /* The S12X additional modes are implemented, but uncommenting here causes a problem */
    1083. 

  1083.   { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2,       5, 0x0b,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1084. 

  1084.   { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2,         4, 0x08,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1085. 

  1085. /*  { "movb", OP_IMM8|OP_IDX1_p2|OP_PAGE2,        5, 0x08,  4,  4,  CHG_NONE, cpu9s12x, 0 },
    1086. 

  1086.   { "movb", OP_IMM8|OP_IDX2_p2|OP_PAGE2,        4, 0x08,  4,  4,  CHG_NONE, cpu9s12x, 0 },
    1087. 

  1087.   { "movb", OP_IMM8|OP_D_IDX|OP_PAGE2,       5, 0x08,  4,  4,  CHG_NONE, cpu9s12x, 0 },
    1088. 

  1088.   { "movb", OP_IMM8|OP_D_IDX2_p2|OP_PAGE2,      4, 0x08,  4,  4,  CHG_NONE, cpu9s12x, 0 },*/
    1089. 

  1089. 

  1090.   { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2,      6, 0x0c,  6,  6,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1091. 

  1091.   { "movb", OP_IND16|OP_IDX_p2|OP_PAGE2,        5, 0x09,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1092. 

  1092. /*  { "movb", OP_IND16|OP_IDX1_p2|OP_PAGE2,       6, 0x09,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1093. 

  1093.   { "movb", OP_IND16|OP_IDX2_p2|OP_PAGE2,       5, 0x09,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1094. 

  1094.   { "movb", OP_IND16|OP_D_IDX_p2|OP_PAGE2,    6, 0x09,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1095. 

  1095.   { "movb", OP_IND16|OP_D_IDX2_p2|OP_PAGE2,     5, 0x09,  5,  5,  CHG_NONE, cpu9s12x, 0 }, */
    1096. 

  1096. 

  1097.   { "movb", OP_IDX|OP_IND16_p2|OP_PAGE2,        5, 0x0d,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1098. 

  1098.   { "movb", OP_IDX|OP_IDX_p2|OP_PAGE2,          4, 0x0a,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1099. 

  1099. /*  { "movb", OP_IDX|OP_IDX1_p2|OP_PAGE2,         5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1100. 

  1100.   { "movb", OP_IDX|OP_IDX2_p2|OP_PAGE2,         4, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1101. 

  1101.   { "movb", OP_IDX|OP_D_IDX_p2|OP_PAGE2,        5, 0x0d,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1102. 

  1102.   { "movb", OP_IDX|OP_D_IDX2_p2|OP_PAGE2,       4, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1103. 

  1103. 

  1104.   { "movb", OP_IDX_1|OP_IND16_p2|OP_PAGE2,       5, 0x0d,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1105. 

  1105.   { "movb", OP_IDX_1|OP_IDX_p2|OP_PAGE2,         4, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1106. 

  1106.   { "movb", OP_IDX_1|OP_IDX1_p2|OP_PAGE2,        6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1107. 

  1107.   { "movb", OP_IDX_1|OP_IDX2_p2|OP_PAGE2,        5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1108. 

  1108.   { "movb", OP_IDX_1|OP_D_IDX_p2|OP_PAGE2,       6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1109. 

  1109.   { "movb", OP_IDX_1|OP_D_IDX2_p2|OP_PAGE2,      5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1110. 

  1110. 

  1111.   { "movb", OP_IDX_2|OP_IND16_p2|OP_PAGE2,       5, 0x0d,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1112. 

  1112.   { "movb", OP_IDX_2|OP_IDX_p2|OP_PAGE2,         4, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1113. 

  1113.   { "movb", OP_IDX_2|OP_IDX1_p2|OP_PAGE2,        6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1114. 

  1114.   { "movb", OP_IDX_2|OP_IDX2_p2|OP_PAGE2,        5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1115. 

  1115.   { "movb", OP_IDX_2|OP_D_IDX_p2|OP_PAGE2,       6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1116. 

  1116.   { "movb", OP_IDX_2|OP_D_IDX2_p2|OP_PAGE2,      5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1117. 

  1117. 

  1118.   { "movb", OP_D_IDX|OP_IND16_p2|OP_PAGE2,       5, 0x0d,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1119. 

  1119.   { "movb", OP_D_IDX|OP_IDX_p2|OP_PAGE2,         4, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1120. 

  1120.   { "movb", OP_D_IDX|OP_IDX1_p2|OP_PAGE2,        6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1121. 

  1121.   { "movb", OP_D_IDX|OP_IDX2_p2|OP_PAGE2,        5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1122. 

  1122.   { "movb", OP_D_IDX|OP_D_IDX_p2|OP_PAGE2,       6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1123. 

  1123.   { "movb", OP_D_IDX|OP_D_IDX2_p2|OP_PAGE2,      5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1124. 

  1124. 

  1125.   { "movb", OP_D_IDX_2|OP_IND16_p2|OP_PAGE2,       5, 0x0d,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1126. 

  1126.   { "movb", OP_D_IDX_2|OP_IDX_p2|OP_PAGE2,         4, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1127. 

  1127.   { "movb", OP_D_IDX_2|OP_IDX1_p2|OP_PAGE2,        6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1128. 

  1128.   { "movb", OP_D_IDX_2|OP_IDX2_p2|OP_PAGE2,        5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1129. 

  1129.   { "movb", OP_D_IDX_2|OP_D_IDX_p2|OP_PAGE2,       6, 0x0a,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1130. 

  1130.   { "movb", OP_D_IDX_2|OP_D_IDX2_p2|OP_PAGE2,      5, 0x0a,  5,  5,  CHG_NONE, cpu9s12x, 0 },*/
    1131. 

  1131. 

  1132.   { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2,  6, 0x03,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1133. 

  1133.   { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2,    5, 0x00,  4,  4,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1134. 

  1134. /*  { "movw", OP_IMM16|OP_IDX1_p2|OP_PAGE2,        5, 0x00,  4,  4,  CHG_NONE, cpu9s12x, 0 },
    1135. 

  1135.   { "movw", OP_IMM16|OP_IDX2_p2|OP_PAGE2,        4, 0x00,  4,  4,  CHG_NONE, cpu9s12x, 0 },
    1136. 

  1136.   { "movw", OP_IMM16|OP_D_IDX_p2|OP_PAGE2,       5, 0x00,  4,  4,  CHG_NONE, cpu9s12x, 0 },
    1137. 

  1137.   { "movw", OP_IMM16|OP_D_IDX2_p2|OP_PAGE2,      4, 0x00,  4,  4,  CHG_NONE, cpu9s12x, 0 },*/
    1138. 

  1138. 

  1139.   { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2,  6, 0x04,  6,  6,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1140. 

  1140.   { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2,    5, 0x01,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1141. 

  1141. /*  { "movw", OP_IND16|OP_IDX1_p2|OP_PAGE2,       6, 0x01,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1142. 

  1142.   { "movw", OP_IND16|OP_IDX2_p2|OP_PAGE2,       5, 0x01,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1143. 

  1143.   { "movw", OP_IND16|OP_D_IDX_p2|OP_PAGE2,      6, 0x01,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1144. 

  1144.   { "movw", OP_IND16|OP_D_IDX2_p2|OP_PAGE2,     5, 0x01,  5,  5,  CHG_NONE, cpu9s12x, 0 },*/
    1145. 

  1145. 

  1146.   { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2,    5, 0x05,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1147. 

  1147.   { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2,      4, 0x02,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1148. 

  1148. /*  { "movw", OP_IDX|OP_IDX1_p2|OP_PAGE2,         5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1149. 

  1149.   { "movw", OP_IDX|OP_IDX2_p2|OP_PAGE2,         4, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1150. 

  1150.   { "movw", OP_IDX|OP_D_IDX_p2|OP_PAGE2,        5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1151. 

  1151.   { "movw", OP_IDX|OP_D_IDX2_p2|OP_PAGE2,       4, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1152. 

  1152. 

  1153.   { "movw", OP_IDX_1|OP_IND16_p2|OP_PAGE2,       5, 0x05,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1154. 

  1154.   { "movw", OP_IDX_1|OP_IDX_p2|OP_PAGE2,         4, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1155. 

  1155.   { "movw", OP_IDX_1|OP_IDX1_p2|OP_PAGE2,        6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1156. 

  1156.   { "movw", OP_IDX_1|OP_IDX2_p2|OP_PAGE2,        5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1157. 

  1157.   { "movw", OP_IDX_1|OP_D_IDX_p2|OP_PAGE2,       6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1158. 

  1158.   { "movw", OP_IDX_1|OP_D_IDX2_p2|OP_PAGE2,      5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1159. 

  1159. 

  1160.   { "movw", OP_IDX_2|OP_IND16_p2|OP_PAGE2,       5, 0x05,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1161. 

  1161.   { "movw", OP_IDX_2|OP_IDX_p2|OP_PAGE2,         4, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1162. 

  1162.   { "movw", OP_IDX_2|OP_IDX1_p2|OP_PAGE2,        6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1163. 

  1163.   { "movw", OP_IDX_2|OP_IDX2_p2|OP_PAGE2,        5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1164. 

  1164.   { "movw", OP_IDX_2|OP_D_IDX_p2|OP_PAGE2,       6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1165. 

  1165.   { "movw", OP_IDX_2|OP_D_IDX2_p2|OP_PAGE2,      5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1166. 

  1166. 

  1167.   { "movw", OP_D_IDX|OP_IND16_p2|OP_PAGE2,       5, 0x05,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1168. 

  1168.   { "movw", OP_D_IDX|OP_IDX_p2|OP_PAGE2,         4, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1169. 

  1169.   { "movw", OP_D_IDX|OP_IDX1_p2|OP_PAGE2,        6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1170. 

  1170.   { "movw", OP_D_IDX|OP_IDX2_p2|OP_PAGE2,        5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1171. 

  1171.   { "movw", OP_D_IDX|OP_D_IDX_p2|OP_PAGE2,       6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1172. 

  1172.   { "movw", OP_D_IDX|OP_D_IDX2_p2|OP_PAGE2,      5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1173. 

  1173. 

  1174.   { "movw", OP_D_IDX_2|OP_IND16_p2|OP_PAGE2,       5, 0x05,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1175. 

  1175.   { "movw", OP_D_IDX_2|OP_IDX_p2|OP_PAGE2,         4, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1176. 

  1176.   { "movw", OP_D_IDX_2|OP_IDX1_p2|OP_PAGE2,        6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1177. 

  1177.   { "movw", OP_D_IDX_2|OP_IDX2_p2|OP_PAGE2,        5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },
    1178. 

  1178.   { "movw", OP_D_IDX_2|OP_D_IDX_p2|OP_PAGE2,       6, 0x02,  6,  6,  CHG_NONE, cpu9s12x, 0 },
    1179. 

  1179.   { "movw", OP_D_IDX_2|OP_D_IDX2_p2|OP_PAGE2,      5, 0x02,  5,  5,  CHG_NONE, cpu9s12x, 0 },*/
    1180. 

  1180. 

  1181.   { "mul",  OP_NONE,           1, 0x3d,  3, 10,  CHG_C, cpu6811, 0 },
    1182. 

  1182.   { "mul",  OP_NONE,           1, 0x12,  3,  3,  CHG_C, cpu6812|cpu9s12x, 0 },
    1183. 

  1183. 

  1184.   { "neg",  OP_IND16,          3, 0x70,  4,  4,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1185. 

  1185.   { "neg",  OP_IX,             2, 0x60,  6,  6,  CHG_NZVC, cpu6811, 0 },
    1186. 

  1186.   { "neg",  OP_IY | OP_PAGE2,  3, 0x60,  7,  7,  CHG_NZVC, cpu6811, 0 },
    1187. 

  1187.   { "neg",  OP_IDX,            2, 0x60,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1188. 

  1188.   { "neg",  OP_IDX_1,          3, 0x60,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1189. 

  1189.   { "neg",  OP_IDX_2,          4, 0x60,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1190. 

  1190.   { "neg",  OP_D_IDX,          2, 0x60,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1191. 

  1191.   { "neg",  OP_D_IDX_2,        4, 0x60,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1192. 

  1192. 

  1193.   { "nega", OP_NONE,           1, 0x40,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1194. 

  1194.   { "negb", OP_NONE,           1, 0x50,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1195. 

  1195. 

  1196.   { "negw",  OP_IND16| OP_PAGE2,          3, 0x70,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1197. 

  1197.   { "negw",  OP_IDX| OP_PAGE2,            2, 0x60,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1198. 

  1198.   { "negw",  OP_IDX_1| OP_PAGE2,          3, 0x60,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1199. 

  1199.   { "negw",  OP_IDX_2| OP_PAGE2,          4, 0x60,  5,  5,  CHG_NZVC, cpu9s12x, 0 },
    1200. 

  1200.   { "negw",  OP_D_IDX| OP_PAGE2,          2, 0x60,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1201. 

  1201.   { "negw",  OP_D_IDX_2| OP_PAGE2,        4, 0x60,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1202. 

  1202. 

  1203.   { "negx", OP_NONE| OP_PAGE2,           1, 0x40,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1204. 

  1204. 

  1205.   { "negy", OP_NONE| OP_PAGE2,           1, 0x50,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1206. 

  1206. 

  1207.   { "nop",  OP_NONE,           1, 0x01,  2,  2,  CHG_NONE, cpu6811, 0 },
    1208. 

  1208.   { "nop",  OP_NONE,           1, 0xa7,  1,  1,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1209. 

  1209. 

  1210.   { "oraa", OP_IMM8,         2, 0x8a,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    1211. 

  1211.   { "oraa", OP_DIRECT,       2, 0x9a,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    1212. 

  1212.   { "oraa", OP_IND16,        3, 0xba,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    1213. 

  1213.   { "oraa", OP_IX,             2, 0xaa,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1214. 

  1214.   { "oraa", OP_IY | OP_PAGE2,  3, 0xaa,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1215. 

  1215.   { "oraa", OP_IDX,            2, 0xaa,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1216. 

  1216.   { "oraa", OP_IDX_1,          3, 0xaa,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1217. 

  1217.   { "oraa", OP_IDX_2,          4, 0xaa,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1218. 

  1218.   { "oraa", OP_D_IDX,          2, 0xaa,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1219. 

  1219.   { "oraa", OP_D_IDX_2,        4, 0xaa,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1220. 

  1220. 

  1221.   { "orab", OP_IMM8,         2, 0xca,  1,  1,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    1222. 

  1222.   { "orab", OP_DIRECT,       2, 0xda,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    1223. 

  1223.   { "orab", OP_IND16,        3, 0xfa,  3,  3,  CLR_V_CHG_NZ, cpu6811|cpu6812|cpu9s12x, 0 },
    1224. 

  1224.   { "orab", OP_IX,             2, 0xea,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1225. 

  1225.   { "orab", OP_IY | OP_PAGE2,  3, 0xea,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1226. 

  1226.   { "orab", OP_IDX,            2, 0xea,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1227. 

  1227.   { "orab", OP_IDX_1,          3, 0xea,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1228. 

  1228.   { "orab", OP_IDX_2,          4, 0xea,  4,  4,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1229. 

  1229.   { "orab", OP_D_IDX,          2, 0xea,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1230. 

  1230.   { "orab", OP_D_IDX_2,        4, 0xea,  6,  6,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1231. 

  1231. 

  1232.   { "orcc", OP_IMM8,           2, 0x14,  1,  1,  CHG_ALL, cpu6812|cpu9s12x, 0 },
    1233. 

  1233. 

  1234.   { "orx", OP_IMM16| OP_PAGE2,  2, 0x8a,  1,  1,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1235. 

  1235.   { "orx", OP_DIRECT| OP_PAGE2, 2, 0x9a,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1236. 

  1236.   { "orx", OP_IND16| OP_PAGE2,  3, 0xba,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1237. 

  1237.   { "orx", OP_IDX| OP_PAGE2,    2, 0xaa,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1238. 

  1238.   { "orx", OP_IDX_1| OP_PAGE2,  3, 0xaa,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1239. 

  1239.   { "orx", OP_IDX_2| OP_PAGE2,  4, 0xaa,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1240. 

  1240.   { "orx", OP_D_IDX| OP_PAGE2,  2, 0xaa,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1241. 

  1241.   { "orx", OP_D_IDX_2| OP_PAGE2,4, 0xaa,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1242. 

  1242. 

  1243.   { "ory", OP_IMM16| OP_PAGE2,  2, 0xca,  1,  1,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1244. 

  1244.   { "ory", OP_DIRECT| OP_PAGE2, 2, 0xda,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1245. 

  1245.   { "ory", OP_IND16| OP_PAGE2,  3, 0xfa,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1246. 

  1246.   { "ory", OP_IDX| OP_PAGE2,    2, 0xea,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1247. 

  1247.   { "ory", OP_IDX_1| OP_PAGE2,  3, 0xea,  3,  3,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1248. 

  1248.   { "ory", OP_IDX_2| OP_PAGE2,  4, 0xea,  4,  4,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1249. 

  1249.   { "ory", OP_D_IDX| OP_PAGE2,  2, 0xea,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1250. 

  1250.   { "ory", OP_D_IDX_2| OP_PAGE2,4, 0xea,  6,  6,  CLR_V_CHG_NZ, cpu9s12x, 0 },
    1251. 

  1251. 

  1252.   { "psha", OP_NONE,           1, 0x36,  2,  2,  CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    1253. 

  1253.   { "pshb", OP_NONE,           1, 0x37,  2,  2,  CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    1254. 

  1254.   { "pshc", OP_NONE,           1, 0x39,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1255. 

  1255.   { "pshcw", OP_NONE| OP_PAGE2,1, 0x39,  2,  2,  CHG_NONE, cpu9s12x, 0 },
    1256. 

  1256.   { "pshd", OP_NONE,           1, 0x3b,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1257. 

  1257.   { "pshx", OP_NONE,           1, 0x3c,  4,  4,  CHG_NONE, cpu6811, 0 },
    1258. 

  1258.   { "pshx", OP_NONE,           1, 0x34,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1259. 

  1259.   { "pshy", OP_NONE | OP_PAGE2,2, 0x3c,  5,  5,  CHG_NONE, cpu6811, 0 },
    1260. 

  1260.   { "pshy", OP_NONE,           1, 0x35,  2,  2,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1261. 

  1261. 

  1262.   { "pula", OP_NONE,           1, 0x32,  3,  3,  CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    1263. 

  1263.   { "pulb", OP_NONE,           1, 0x33,  3,  3,  CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    1264. 

  1264.   { "pulc", OP_NONE,           1, 0x38,  3,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1265. 

  1265.   { "pulcw", OP_NONE| OP_PAGE2,1, 0x38,  2,  2,  CHG_NONE, cpu9s12x, 0 },
    1266. 

  1266.   { "puld", OP_NONE,           1, 0x3a,  3,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1267. 

  1267.   { "pulx", OP_NONE,           1, 0x38,  5,  5,  CHG_NONE, cpu6811, 0 },
    1268. 

  1268.   { "pulx", OP_NONE,           1, 0x30,  3,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1269. 

  1269.   { "puly", OP_NONE | OP_PAGE2,2, 0x38,  6,  6,  CHG_NONE, cpu6811, 0 },
    1270. 

  1270.   { "puly", OP_NONE,           1, 0x31,  3,  3,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1271. 

  1271. 

  1272.   { "rev",  OP_NONE | OP_PAGE2, 2, 0x3a,  _M,  _M,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    1273. 

  1273.   { "revw", OP_NONE | OP_PAGE2, 2, 0x3b,  _M,  _M,  CHG_HNZVC, cpu6812|cpu9s12x, 0 },
    1274. 

  1274. 

  1275.   { "rol",  OP_IND16,          3, 0x79,  6,  6,  CHG_NZVC, cpu6811, 0 },
    1276. 

  1276.   { "rol",  OP_IX,             2, 0x69,  6,  6,  CHG_NZVC, cpu6811, 0 },
    1277. 

  1277.   { "rol",  OP_IY | OP_PAGE2,  3, 0x69,  7,  7,  CHG_NZVC, cpu6811, 0 },
    1278. 

  1278.   { "rol",  OP_IND16,          3, 0x75,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1279. 

  1279.   { "rol",  OP_IDX,            2, 0x65,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1280. 

  1280.   { "rol",  OP_IDX_1,          3, 0x65,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1281. 

  1281.   { "rol",  OP_IDX_2,          4, 0x65,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1282. 

  1282.   { "rol",  OP_D_IDX,          2, 0x65,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1283. 

  1283.   { "rol",  OP_D_IDX_2,        4, 0x65,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1284. 

  1284. 

  1285.   { "rola", OP_NONE,           1, 0x49,  2,  2,  CHG_NZVC, cpu6811, 0 },
    1286. 

  1286.   { "rola", OP_NONE,           1, 0x45,  1,  1,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1287. 

  1287.   { "rolb", OP_NONE,           1, 0x59,  2,  2,  CHG_NZVC, cpu6811, 0 },
    1288. 

  1288.   { "rolb", OP_NONE,           1, 0x55,  1,  1,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1289. 

  1289. 

  1290.   { "rolw",  OP_IND16 | OP_PAGE2,          3, 0x75,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1291. 

  1291.   { "rolw",  OP_IDX | OP_PAGE2,            2, 0x65,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1292. 

  1292.   { "rolw",  OP_IDX_1 | OP_PAGE2,          3, 0x65,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1293. 

  1293.   { "rolw",  OP_IDX_2 | OP_PAGE2,          4, 0x65,  5,  5,  CHG_NZVC, cpu9s12x, 0 },
    1294. 

  1294.   { "rolw",  OP_D_IDX | OP_PAGE2,          2, 0x65,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1295. 

  1295.   { "rolw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x65,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1296. 

  1296. 

  1297.   { "rolx", OP_NONE | OP_PAGE2,           1, 0x45,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1298. 

  1298.   { "roly", OP_NONE | OP_PAGE2,           1, 0x55,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1299. 

  1299. 

  1300.   { "ror",  OP_IND16,          3, 0x76,  4,  4,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1301. 

  1301.   { "ror",  OP_IX,             2, 0x66,  6,  6,  CHG_NZVC, cpu6811, 0 },
    1302. 

  1302.   { "ror",  OP_IY | OP_PAGE2,  3, 0x66,  7,  7,  CHG_NZVC, cpu6811, 0 },
    1303. 

  1303.   { "ror",  OP_IDX,            2, 0x66,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1304. 

  1304.   { "ror",  OP_IDX_1,          3, 0x66,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1305. 

  1305.   { "ror",  OP_IDX_2,          4, 0x66,  5,  5,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1306. 

  1306.   { "ror",  OP_D_IDX,          2, 0x66,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1307. 

  1307.   { "ror",  OP_D_IDX_2,        4, 0x66,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1308. 

  1308. 

  1309.   { "rora", OP_NONE,           1, 0x46,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1310. 

  1310.   { "rorb", OP_NONE,           1, 0x56,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1311. 

  1311. 

  1312.   { "rorw",  OP_IND16 | OP_PAGE2,          3, 0x76,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1313. 

  1313.   { "rorw",  OP_IDX | OP_PAGE2,            2, 0x66,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1314. 

  1314.   { "rorw",  OP_IDX_1 | OP_PAGE2,          3, 0x66,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1315. 

  1315.   { "rorw",  OP_IDX_2 | OP_PAGE2,          4, 0x66,  5,  5,  CHG_NZVC, cpu9s12x, 0 },
    1316. 

  1316.   { "rorw",  OP_D_IDX | OP_PAGE2,          2, 0x66,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1317. 

  1317.   { "rorw",  OP_D_IDX_2 | OP_PAGE2,        4, 0x66,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1318. 

  1318. 

  1319.   { "rorx", OP_NONE | OP_PAGE2,           1, 0x46,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1320. 

  1320.   { "rory", OP_NONE | OP_PAGE2,           1, 0x56,  1,  1,  CHG_NZVC, cpu9s12x, 0 },
    1321. 

  1321. 

  1322.   { "rtc",  OP_NONE,           1, 0x0a,  6,  6,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1323. 

  1323.   { "rti",  OP_NONE,           1, 0x3b, 12, 12,  CHG_ALL, cpu6811, 0 },
    1324. 

  1324.   { "rti",  OP_NONE,           1, 0x0b,  8, 10,  CHG_ALL, cpu6812|cpu9s12x, 0 },
    1325. 

  1325.   { "rts",  OP_NONE,           1, 0x39,  5,  5,  CHG_NONE, cpu6811, 0 },
    1326. 

  1326.   { "rts",  OP_NONE,           1, 0x3d,  5,  5,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1327. 

  1327. 

  1328.   { "sba",  OP_NONE,             1, 0x10,  2,  2,  CHG_NZVC, cpu6811, 0 },
    1329. 

  1329.   { "sba",  OP_NONE | OP_PAGE2, 2, 0x16,  2,  2,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1330. 

  1330. 

  1331.   { "sbca", OP_IMM8,           2, 0x82,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1332. 

  1332.   { "sbca", OP_DIRECT,         2, 0x92,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1333. 

  1333.   { "sbca", OP_IND16,          3, 0xb2,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1334. 

  1334.   { "sbca", OP_IX,             2, 0xa2,  4,  4,  CHG_NZVC, cpu6811, 0 },
    1335. 

  1335.   { "sbca", OP_IY | OP_PAGE2,  3, 0xa2,  5,  5,  CHG_NZVC, cpu6811, 0 },
    1336. 

  1336.   { "sbca", OP_IDX,            2, 0xa2,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1337. 

  1337.   { "sbca", OP_IDX_1,          3, 0xa2,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1338. 

  1338.   { "sbca", OP_IDX_2,          4, 0xa2,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1339. 

  1339.   { "sbca", OP_D_IDX,          2, 0xa2,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1340. 

  1340.   { "sbca", OP_D_IDX_2,        4, 0xa2,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1341. 

  1341. 

  1342.   { "sbcb", OP_IMM8,           2, 0xc2,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1343. 

  1343.   { "sbcb", OP_DIRECT,         2, 0xd2,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1344. 

  1344.   { "sbcb", OP_IND16,          3, 0xf2,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1345. 

  1345.   { "sbcb", OP_IX,             2, 0xe2,  4,  4,  CHG_NZVC, cpu6811, 0 },
    1346. 

  1346.   { "sbcb", OP_IY | OP_PAGE2,  3, 0xe2,  5,  5,  CHG_NZVC, cpu6811, 0 },
    1347. 

  1347.   { "sbcb", OP_IDX,            2, 0xe2,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1348. 

  1348.   { "sbcb", OP_IDX_1,          3, 0xe2,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1349. 

  1349.   { "sbcb", OP_IDX_2,          4, 0xe2,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1350. 

  1350.   { "sbcb", OP_D_IDX,          2, 0xe2,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1351. 

  1351.   { "sbcb", OP_D_IDX_2,        4, 0xe2,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1352. 

  1352. 

  1353.   { "sbed", OP_IMM16 | OP_PAGE2,          3, 0x83,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    1354. 

  1354.   { "sbed", OP_DIRECT | OP_PAGE2,         2, 0x93,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1355. 

  1355.   { "sbed", OP_IND16 | OP_PAGE2,          3, 0xb3,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1356. 

  1356.   { "sbed", OP_IDX | OP_PAGE2,            2, 0xa3,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1357. 

  1357.   { "sbed", OP_IDX_1 | OP_PAGE2,          3, 0xa3,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1358. 

  1358.   { "sbed", OP_IDX_2 | OP_PAGE2,          4, 0xa3,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1359. 

  1359.   { "sbed", OP_D_IDX | OP_PAGE2,          2, 0xa3,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1360. 

  1360.   { "sbed", OP_D_IDX_2 | OP_PAGE2,        4, 0xa3,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1361. 

  1361. 

  1362.   { "sbex", OP_IMM16 | OP_PAGE2,          3, 0x82,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    1363. 

  1363.   { "sbex", OP_DIRECT | OP_PAGE2,         2, 0x92,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1364. 

  1364.   { "sbex", OP_IND16 | OP_PAGE2,          3, 0xb2,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1365. 

  1365.   { "sbex", OP_IDX | OP_PAGE2,            2, 0xa2,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1366. 

  1366.   { "sbex", OP_IDX_1 | OP_PAGE2,          3, 0xa2,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1367. 

  1367.   { "sbex", OP_IDX_2 | OP_PAGE2,          4, 0xa2,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1368. 

  1368.   { "sbex", OP_D_IDX | OP_PAGE2,          2, 0xa2,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1369. 

  1369.   { "sbex", OP_D_IDX_2 | OP_PAGE2,        4, 0xa2,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1370. 

  1370. 

  1371.   { "sbey", OP_IMM16 | OP_PAGE2,          3, 0xc2,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    1372. 

  1372.   { "sbey", OP_DIRECT | OP_PAGE2,         2, 0xd2,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1373. 

  1373.   { "sbey", OP_IND16 | OP_PAGE2,          3, 0xf2,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1374. 

  1374.   { "sbey", OP_IDX | OP_PAGE2,            2, 0xe2,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1375. 

  1375.   { "sbey", OP_IDX_1 | OP_PAGE2,          3, 0xe2,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1376. 

  1376.   { "sbey", OP_IDX_2 | OP_PAGE2,          4, 0xe2,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1377. 

  1377.   { "sbey", OP_D_IDX | OP_PAGE2,          2, 0xe2,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1378. 

  1378.   { "sbey", OP_D_IDX_2 | OP_PAGE2,        4, 0xe2,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1379. 

  1379. 

  1380.   { "sec",  OP_NONE,           1, 0x0d,  2,  2,  SET_C, cpu6811, 0 },
    1381. 

  1381.   { "sei",  OP_NONE,           1, 0x0f,  2,  2,  SET_I, cpu6811, 0 },
    1382. 

  1382.   { "sev",  OP_NONE,           1, 0x0b,  2,  2,  SET_V, cpu6811, 0 },
    1383. 

  1383. 

  1384. /* Some sex opcodes are synonyms for tfr. */
    1385. 

  1385.   { "sex",  M6812_OP_SEX_MARKER
    1386. 

  1386.           | OP_REG | OP_REG_2, 2, 0xb7,  1,  1,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1387. 

  1387. 

  1388.   { "staa", OP_IND16,          3, 0xb7,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1389. 

  1389.   { "staa", OP_DIRECT,         2, 0x97,  3,  3,  CLR_V_CHG_NZ, cpu6811, 0 },
    1390. 

  1390.   { "staa", OP_IX,             2, 0xa7,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1391. 

  1391.   { "staa", OP_IY | OP_PAGE2,  3, 0xa7,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1392. 

  1392.   { "staa", OP_DIRECT,         2, 0x5a,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1393. 

  1393.   { "staa", OP_IND16,          3, 0x7a,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1394. 

  1394.   { "staa", OP_IDX,            2, 0x6a,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1395. 

  1395.   { "staa", OP_IDX_1,          3, 0x6a,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1396. 

  1396.   { "staa", OP_IDX_2,          4, 0x6a,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1397. 

  1397.   { "staa", OP_D_IDX,          2, 0x6a,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1398. 

  1398.   { "staa", OP_D_IDX_2,        4, 0x6a,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1399. 

  1399. 

  1400.   { "stab", OP_IND16,          3, 0xf7,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1401. 

  1401.   { "stab", OP_DIRECT,         2, 0xd7,  3,  3,  CLR_V_CHG_NZ, cpu6811, 0 },
    1402. 

  1402.   { "stab", OP_IX,             2, 0xe7,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1403. 

  1403.   { "stab", OP_IY | OP_PAGE2,  3, 0xe7,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1404. 

  1404.   { "stab", OP_DIRECT,         2, 0x5b,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1405. 

  1405.   { "stab", OP_IND16,          3, 0x7b,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1406. 

  1406.   { "stab", OP_IDX,            2, 0x6b,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1407. 

  1407.   { "stab", OP_IDX_1,          3, 0x6b,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1408. 

  1408.   { "stab", OP_IDX_2,          4, 0x6b,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1409. 

  1409.   { "stab", OP_D_IDX,          2, 0x6b,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1410. 

  1410.   { "stab", OP_D_IDX_2,        4, 0x6b,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1411. 

  1411. 

  1412.   { "std",  OP_IND16,          3, 0xfd,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1413. 

  1413.   { "std",  OP_DIRECT,         2, 0xdd,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1414. 

  1414.   { "std",  OP_IX,             2, 0xed,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1415. 

  1415.   { "std",  OP_IY | OP_PAGE2,  3, 0xed,  6,  6,  CLR_V_CHG_NZ, cpu6811, 0 },
    1416. 

  1416.   { "std",  OP_DIRECT,         2, 0x5c,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1417. 

  1417.   { "std",  OP_IND16,          3, 0x7c,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1418. 

  1418.   { "std",  OP_IDX,            2, 0x6c,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1419. 

  1419.   { "std",  OP_IDX_1,          3, 0x6c,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1420. 

  1420.   { "std",  OP_IDX_2,          4, 0x6c,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1421. 

  1421.   { "std",  OP_D_IDX,          2, 0x6c,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1422. 

  1422.   { "std",  OP_D_IDX_2,        4, 0x6c,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1423. 

  1423. 

  1424.   { "stop", OP_NONE,           1, 0xcf,  2,  2,  CHG_NONE, cpu6811, 0 },
    1425. 

  1425.   { "stop", OP_NONE | OP_PAGE2,2, 0x3e,  2,  9,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1426. 

  1426. 

  1427.   { "sts",  OP_IND16,          3, 0xbf,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1428. 

  1428.   { "sts",  OP_DIRECT,         2, 0x9f,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1429. 

  1429.   { "sts",  OP_IX,             2, 0xaf,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1430. 

  1430.   { "sts",  OP_IY | OP_PAGE2,  3, 0xaf,  6,  6,  CLR_V_CHG_NZ, cpu6811, 0 },
    1431. 

  1431.   { "sts",  OP_DIRECT,         2, 0x5f,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1432. 

  1432.   { "sts",  OP_IND16,          3, 0x7f,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1433. 

  1433.   { "sts",  OP_IDX,            2, 0x6f,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1434. 

  1434.   { "sts",  OP_IDX_1,          3, 0x6f,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1435. 

  1435.   { "sts",  OP_IDX_2,          4, 0x6f,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1436. 

  1436.   { "sts",  OP_D_IDX,          2, 0x6f,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1437. 

  1437.   { "sts",  OP_D_IDX_2,        4, 0x6f,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1438. 

  1438. 

  1439.   { "stx",  OP_IND16,          3, 0xff,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1440. 

  1440.   { "stx",  OP_DIRECT,         2, 0xdf,  4,  4,  CLR_V_CHG_NZ, cpu6811, 0 },
    1441. 

  1441.   { "stx",  OP_IX,             2, 0xef,  5,  5,  CLR_V_CHG_NZ, cpu6811, 0 },
    1442. 

  1442.   { "stx",  OP_IY | OP_PAGE4,  3, 0xef,  6,  6,  CLR_V_CHG_NZ, cpu6811, 0 },
    1443. 

  1443.   { "stx",  OP_DIRECT,         2, 0x5e,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1444. 

  1444.   { "stx",  OP_IND16,          3, 0x7e,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1445. 

  1445.   { "stx",  OP_IDX,            2, 0x6e,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1446. 

  1446.   { "stx",  OP_IDX_1,          3, 0x6e,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1447. 

  1447.   { "stx",  OP_IDX_2,          4, 0x6e,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1448. 

  1448.   { "stx",  OP_D_IDX,          2, 0x6e,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1449. 

  1449.   { "stx",  OP_D_IDX_2,        4, 0x6e,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1450. 

  1450. 

  1451.   { "sty",  OP_IND16 | OP_PAGE2,  4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
    1452. 

  1452.   { "sty",  OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },
    1453. 

  1453.   { "sty",  OP_IY | OP_PAGE2,     3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
    1454. 

  1454.   { "sty",  OP_IX | OP_PAGE3,     3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },
    1455. 

  1455.   { "sty",  OP_DIRECT,         2, 0x5d,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1456. 

  1456.   { "sty",  OP_IND16,          3, 0x7d,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1457. 

  1457.   { "sty",  OP_IDX,            2, 0x6d,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1458. 

  1458.   { "sty",  OP_IDX_1,          3, 0x6d,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1459. 

  1459.   { "sty",  OP_IDX_2,          4, 0x6d,  3,  3,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1460. 

  1460.   { "sty",  OP_D_IDX,          2, 0x6d,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1461. 

  1461.   { "sty",  OP_D_IDX_2,        4, 0x6d,  5,  5,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1462. 

  1462. 

  1463.   { "suba", OP_IMM8,           2, 0x80,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1464. 

  1464.   { "suba", OP_DIRECT,         2, 0x90,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1465. 

  1465.   { "suba", OP_IND16,          3, 0xb0,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1466. 

  1466.   { "suba", OP_IX,             2, 0xa0,  4,  4,  CHG_NZVC, cpu6811, 0 },
    1467. 

  1467.   { "suba", OP_IY | OP_PAGE2,  3, 0xa0,  5,  5,  CHG_NZVC, cpu6811, 0 },
    1468. 

  1468.   { "suba", OP_IDX,            2, 0xa0,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1469. 

  1469.   { "suba", OP_IDX_1,          3, 0xa0,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1470. 

  1470.   { "suba", OP_IDX_2,          4, 0xa0,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1471. 

  1471.   { "suba", OP_D_IDX,          2, 0xa0,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1472. 

  1472.   { "suba", OP_D_IDX_2,        4, 0xa0,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1473. 

  1473. 

  1474.   { "subb", OP_IMM8,           2, 0xc0,  1,  1,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1475. 

  1475.   { "subb", OP_DIRECT,         2, 0xd0,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1476. 

  1476.   { "subb", OP_IND16,          3, 0xf0,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1477. 

  1477.   { "subb", OP_IX,             2, 0xe0,  4,  4,  CHG_NZVC, cpu6811, 0 },
    1478. 

  1478.   { "subb", OP_IY | OP_PAGE2,  3, 0xe0,  5,  5,  CHG_NZVC, cpu6811, 0 },
    1479. 

  1479.   { "subb", OP_IDX,            2, 0xe0,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1480. 

  1480.   { "subb", OP_IDX_1,          3, 0xe0,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1481. 

  1481.   { "subb", OP_IDX_2,          4, 0xe0,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1482. 

  1482.   { "subb", OP_D_IDX,          2, 0xe0,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1483. 

  1483.   { "subb", OP_D_IDX_2,        4, 0xe0,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1484. 

  1484. 

  1485.   { "subd", OP_IMM16,          3, 0x83,  2,  2,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1486. 

  1486.   { "subd", OP_DIRECT,         2, 0x93,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1487. 

  1487.   { "subd", OP_IND16,          3, 0xb3,  3,  3,  CHG_NZVC, cpu6811|cpu6812|cpu9s12x, 0 },
    1488. 

  1488.   { "subd", OP_IX,             2, 0xa3,  6,  6,  CHG_NZVC, cpu6811, 0 },
    1489. 

  1489.   { "subd", OP_IY | OP_PAGE2,  3, 0xa3,  7,  7,  CHG_NZVC, cpu6811, 0 },
    1490. 

  1490.   { "subd", OP_IDX,            2, 0xa3,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1491. 

  1491.   { "subd", OP_IDX_1,          3, 0xa3,  3,  3,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1492. 

  1492.   { "subd", OP_IDX_2,          4, 0xa3,  4,  4,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1493. 

  1493.   { "subd", OP_D_IDX,          2, 0xa3,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1494. 

  1494.   { "subd", OP_D_IDX_2,        4, 0xa3,  6,  6,  CHG_NZVC, cpu6812|cpu9s12x, 0 },
    1495. 

  1495. 

  1496.   { "subx", OP_IMM16 | OP_PAGE2,          3, 0x80,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    1497. 

  1497.   { "subx", OP_DIRECT | OP_PAGE2,         2, 0x90,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1498. 

  1498.   { "subx", OP_IND16 | OP_PAGE2,          3, 0xb0,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1499. 

  1499.   { "subx", OP_IDX | OP_PAGE2,            2, 0xa0,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1500. 

  1500.   { "subx", OP_IDX_1 | OP_PAGE2,          3, 0xa0,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1501. 

  1501.   { "subx", OP_IDX_2 | OP_PAGE2,          4, 0xa0,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1502. 

  1502.   { "subx", OP_D_IDX | OP_PAGE2,          2, 0xa0,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1503. 

  1503.   { "subx", OP_D_IDX_2 | OP_PAGE2,        4, 0xa0,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1504. 

  1504. 

  1505.   { "suby", OP_IMM16 | OP_PAGE2,          3, 0xc0,  2,  2,  CHG_NZVC, cpu9s12x, 0 },
    1506. 

  1506.   { "suby", OP_DIRECT | OP_PAGE2,         2, 0xd0,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1507. 

  1507.   { "suby", OP_IND16 | OP_PAGE2,          3, 0xf0,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1508. 

  1508.   { "suby", OP_IDX | OP_PAGE2,            2, 0xe0,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1509. 

  1509.   { "suby", OP_IDX_1 | OP_PAGE2,          3, 0xe0,  3,  3,  CHG_NZVC, cpu9s12x, 0 },
    1510. 

  1510.   { "suby", OP_IDX_2 | OP_PAGE2,          4, 0xe0,  4,  4,  CHG_NZVC, cpu9s12x, 0 },
    1511. 

  1511.   { "suby", OP_D_IDX | OP_PAGE2,          2, 0xe0,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1512. 

  1512.   { "suby", OP_D_IDX_2 | OP_PAGE2,        4, 0xe0,  6,  6,  CHG_NZVC, cpu9s12x, 0 },
    1513. 

  1513. 

  1514.   { "swi",  OP_NONE,           1, 0x3f,  9,  9,  CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    1515. 

  1515.   { "sys",  OP_NONE | OP_PAGE2,2, 0xa7,  9,  9,  SET_I, cpu9s12x, 0 },
    1516. 

  1516. 

  1517.   { "tab",  OP_NONE,           1, 0x16,  2,  2,  CLR_V_CHG_NZ, cpu6811, 0 },
    1518. 

  1518.   { "tab",  OP_NONE | OP_PAGE2,2, 0x0e,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1519. 

  1519. 

  1520.   { "tap",  OP_NONE,           1, 0x06,  2,  2,  CHG_ALL, cpu6811, 0 },
    1521. 

  1521. 

  1522.   { "tba",  OP_NONE,           1, 0x17,  2,  2,  CLR_V_CHG_NZ, cpu6811, 0 },
    1523. 

  1523.   { "tba",  OP_NONE | OP_PAGE2,2, 0x0f,  2,  2,  CLR_V_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1524. 

  1524. 

  1525.   { "test", OP_NONE,           1, 0x00,  5, _M,  CHG_NONE, cpu6811, 0 },
    1526. 

  1526. 

  1527.   { "tpa",  OP_NONE,           1, 0x07,  2,  2,  CHG_NONE, cpu6811, 0 },
    1528. 

  1528. 

  1529.   { "tbeq", OP_TBEQ_MARKER
    1530. 

  1530.           | OP_REG | OP_JUMP_REL,  3, 0x04,  3,  3, CHG_NONE, cpu6812|cpu9s12x, 0 },
    1531. 

  1531. 

  1532.   { "tbl",  OP_IDX | OP_PAGE2,  3, 0x3d,  8,  8, CHG_NZC, cpu6812|cpu9s12x, 0 },
    1533. 

  1533. 

  1534.   { "tbne", OP_TBNE_MARKER
    1535. 

  1535.           | OP_REG | OP_JUMP_REL,  3, 0x04,  3,  3, CHG_NONE, cpu6812|cpu9s12x, 0 },
    1536. 

  1536. 

  1537. /* The S12X has more tfr variants, but most are pointless so not supported. */
    1538. 

  1538.   { "tfr",  OP_TFR_MARKER
    1539. 

  1539.           | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1,  CHG_NONE, cpu6812|cpu9s12x, 0 },
    1540. 

  1540. 

  1541.   { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18,  11,  11,  SET_I, cpu6812|cpu9s12x, 0 },
    1542. 

  1542. 

  1543.   { "tst",  OP_IND16,          3, 0x7d,  6,  6,  CLR_VC_CHG_NZ, cpu6811, 0 },
    1544. 

  1544.   { "tst",  OP_IX,             2, 0x6d,  6,  6,  CLR_VC_CHG_NZ, cpu6811, 0 },
    1545. 

  1545.   { "tst",  OP_IY | OP_PAGE2,  3, 0x6d,  7,  7,  CLR_VC_CHG_NZ, cpu6811, 0 },
    1546. 

  1546.   { "tst",  OP_IND16,          3, 0xf7,  3,  3,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1547. 

  1547.   { "tst",  OP_IDX,            2, 0xe7,  3,  3,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1548. 

  1548.   { "tst",  OP_IDX_1,          3, 0xe7,  3,  3,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1549. 

  1549.   { "tst",  OP_IDX_2,          4, 0xe7,  4,  4,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1550. 

  1550.   { "tst",  OP_D_IDX,          2, 0xe7,  6,  6,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1551. 

  1551.   { "tst",  OP_D_IDX_2,        4, 0xe7,  6,  6,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1552. 

  1552. 

  1553.   { "tsta", OP_NONE,           1, 0x4d,  2,  2,  CLR_VC_CHG_NZ, cpu6811, 0 },
    1554. 

  1554.   { "tsta", OP_NONE,           1, 0x97,  1,  1,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1555. 

  1555.   { "tstb", OP_NONE,           1, 0x5d,  2,  2,  CLR_VC_CHG_NZ, cpu6811, 0 },
    1556. 

  1556.   { "tstb", OP_NONE,           1, 0xd7,  1,  1,  CLR_VC_CHG_NZ, cpu6812|cpu9s12x, 0 },
    1557. 

  1557. 

  1558.   { "tstw",  OP_IND16| OP_PAGE2,          3, 0xf7,  3,  3,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1559. 

  1559.   { "tstw",  OP_IDX| OP_PAGE2,            2, 0xe7,  3,  3,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1560. 

  1560.   { "tstw",  OP_IDX_1| OP_PAGE2,          3, 0xe7,  3,  3,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1561. 

  1561.   { "tstw",  OP_IDX_2| OP_PAGE2,          4, 0xe7,  4,  4,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1562. 

  1562.   { "tstw",  OP_D_IDX| OP_PAGE2,          2, 0xe7,  6,  6,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1563. 

  1563.   { "tstw",  OP_D_IDX_2| OP_PAGE2,        4, 0xe7,  6,  6,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1564. 

  1564. 

  1565.   { "tstx", OP_NONE| OP_PAGE2,           1, 0x97,  1,  1,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1566. 

  1566.   { "tsty", OP_NONE| OP_PAGE2,           1, 0xd7,  1,  1,  CLR_VC_CHG_NZ, cpu9s12x, 0 },
    1567. 

  1567. 

  1568.   { "tsx",  OP_NONE,           1, 0x30,  3,  3,  CHG_NONE, cpu6811, 0 },
    1569. 

  1569.   { "tsy",  OP_NONE | OP_PAGE2,2, 0x30,  4,  4,  CHG_NONE, cpu6811, 0 },
    1570. 

  1570.   { "txs",  OP_NONE,           1, 0x35,  3,  3,  CHG_NONE, cpu6811, 0 },
    1571. 

  1571.   { "tys",  OP_NONE | OP_PAGE2,2, 0x35,  4,  4,  CHG_NONE, cpu6811, 0 },
    1572. 

  1572. 

  1573.   { "wai",  OP_NONE,           1, 0x3e,  5,  _M, CHG_NONE, cpu6811|cpu6812|cpu9s12x, 0 },
    1574. 

  1574. 

  1575.   { "wav",  OP_NONE | OP_PAGE2, 2, 0x3c,  8,  _M, SET_Z_CHG_HNVC, cpu6812|cpu9s12x, 0 },
    1576. 

  1576. 

  1577.   { "xgdx", OP_NONE,           1, 0x8f,  3,  3,  CHG_NONE, cpu6811, 0 },
    1578. 

  1578.   { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f,  4,  4,  CHG_NONE, cpu6811, 0 },
    1579. 

  1579. 

  1580. /* XGATE opcodes */
    1581. 

  1581. /* Return to Scheduler and Others*/
    1582. 

  1582.   { "brk",   M68XG_OP_NONE,           2, 0x0000, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
    1583. 

  1583.   { "nop",   M68XG_OP_NONE,           2, 0x0100, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
    1584. 

  1584.   { "rts",   M68XG_OP_NONE,           2, 0x0200, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
    1585. 

  1585.   { "sif",   M68XG_OP_NONE,           2, 0x0300, 0, 0, 0, 0, 0, cpuxgate, 0xffff },
    1586. 

  1586. /* Semaphore Instructions */
    1587. 

  1587.   { "csem",  M68XG_OP_IMM3,           2, 0x00f0, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1588. 

  1588.   { "csem",  M68XG_OP_R,              2, 0x00f1, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1589. 

  1589.   { "ssem",  M68XG_OP_IMM3,           2, 0x00f2, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1590. 

  1590.   { "ssem",  M68XG_OP_R,              2, 0x00f3, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1591. 

  1591. /* Single Register Instructions */
    1592. 

  1592.   { "sex",   M68XG_OP_R,              2, 0x00f4, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1593. 

  1593.   { "par",   M68XG_OP_R,              2, 0x00f5, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1594. 

  1594.   { "jal",   M68XG_OP_R,              2, 0x00f6, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1595. 

  1595.   { "sif",   M68XG_OP_R,              2, 0x00f7, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },
    1596. 

  1596. /* Special Move instructions */
    1597. 

  1597.   { "tfr",   M68XG_OP_R,              2, 0x00f8, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,CCR */
    1598. 

  1598.   { "tfr",   M68XG_OP_R,              2, 0x00f9, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* CCR,RS */
    1599. 

  1599.   { "tfr",   M68XG_OP_R,              2, 0x00fa, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,PC  */
    1600. 

  1600. /* Shift instructions Dyadic */
    1601. 

  1601.   { "bffo",  M68XG_OP_R_R,            2, 0x0810, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1602. 

  1602.   { "asr",   M68XG_OP_R_R,            2, 0x0811, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1603. 

  1603.   { "csl",   M68XG_OP_R_R,            2, 0x0812, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1604. 

  1604.   { "csr",   M68XG_OP_R_R,            2, 0x0813, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1605. 

  1605.   { "lsl",   M68XG_OP_R_R,            2, 0x0814, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1606. 

  1606.   { "lsr",   M68XG_OP_R_R,            2, 0x0815, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1607. 

  1607.   { "rol",   M68XG_OP_R_R,            2, 0x0816, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1608. 

  1608.   { "ror",   M68XG_OP_R_R,            2, 0x0817, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },
    1609. 

  1609. /* Dyadic aliases */
    1610. 

  1610.   { "cmp",   M68XG_OP_R_R,            2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1611. 

  1611.   { "com",   M68XG_OP_R_R,            2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1612. 

  1612.   { "cpc",   M68XG_OP_R_R,            2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1613. 

  1613.   { "mov",   M68XG_OP_R_R,            2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1614. 

  1614.   { "neg",   M68XG_OP_R_R,            2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1615. 

  1615. /* Monadic aliases */
    1616. 

  1616.   { "com",   M68XG_OP_R,              2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1617. 

  1617.   { "neg",   M68XG_OP_R,              2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1618. 

  1618.   { "tst",   M68XG_OP_R,              2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1619. 

  1619. /* Shift instructions immediate */
    1620. 

  1620.   { "asr",   M68XG_OP_R_IMM4,         2, 0x0809, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
    1621. 

  1621.   { "csl",   M68XG_OP_R_IMM4,         2, 0x080a, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
    1622. 

  1622.   { "csr",   M68XG_OP_R_IMM4,         2, 0x080b, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
    1623. 

  1623.   { "lsl",   M68XG_OP_R_IMM4,         2, 0x080c, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
    1624. 

  1624.   { "lsr",   M68XG_OP_R_IMM4,         2, 0x080d, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
    1625. 

  1625.   { "rol",   M68XG_OP_R_IMM4,         2, 0x080e, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
    1626. 

  1626.   { "ror",   M68XG_OP_R_IMM4,         2, 0x080f, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },
    1627. 

  1627. /* Logical Triadic */
    1628. 

  1628.   { "and",   M68XG_OP_R_R_R,          2, 0x1000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1629. 

  1629.   { "or",    M68XG_OP_R_R_R,          2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1630. 

  1630.   { "xnor",  M68XG_OP_R_R_R,          2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1631. 

  1631. /* Arithmetic Triadic */
    1632. 

  1632.   { "sub",   M68XG_OP_R_R_R,          2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1633. 

  1633.   { "sbc",   M68XG_OP_R_R_R,          2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1634. 

  1634.   { "add",   M68XG_OP_R_R_R,          2, 0x1802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1635. 

  1635.   { "adc",   M68XG_OP_R_R_R,          2, 0x1803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1636. 

  1636. /* Branches */
    1637. 

  1637.   { "bcc",   M68XG_OP_REL9,           2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1638. 

  1638.   { "bhs",   M68XG_OP_REL9,           2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, /* Synonym. */
    1639. 

  1639.   { "bcs",   M68XG_OP_REL9,           2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1640. 

  1640.   { "blo",   M68XG_OP_REL9,           2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, /* Synonym. */
    1641. 

  1641.   { "bne",   M68XG_OP_REL9,           2, 0x2400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1642. 

  1642.   { "beq",   M68XG_OP_REL9,           2, 0x2600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1643. 

  1643.   { "bpl",   M68XG_OP_REL9,           2, 0x2800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1644. 

  1644.   { "bmi",   M68XG_OP_REL9,           2, 0x2a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1645. 

  1645.   { "bvc",   M68XG_OP_REL9,           2, 0x2c00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1646. 

  1646.   { "bvs",   M68XG_OP_REL9,           2, 0x2e00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1647. 

  1647.   { "bhi",   M68XG_OP_REL9,           2, 0x3000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1648. 

  1648.   { "bls",   M68XG_OP_REL9,           2, 0x3200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1649. 

  1649.   { "bge",   M68XG_OP_REL9,           2, 0x3400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1650. 

  1650.   { "blt",   M68XG_OP_REL9,           2, 0x3600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1651. 

  1651.   { "bgt",   M68XG_OP_REL9,           2, 0x3800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1652. 

  1652.   { "ble",   M68XG_OP_REL9,           2, 0x3a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },
    1653. 

  1653.   { "bra",   M68XG_OP_REL10,          2, 0x3c00, 0, 0, 0, 0, 0, cpuxgate, 0xfc00 },
    1654. 

  1654. /* Load and Store Instructions */
    1655. 

  1655.   { "ldb",   M68XG_OP_R_R_OFFS5,      2, 0x4000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1656. 

  1656.   { "ldw",   M68XG_OP_R_R_OFFS5,      2, 0x4800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1657. 

  1657.   { "stb",   M68XG_OP_R_R_OFFS5,      2, 0x5000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1658. 

  1658.   { "stw",   M68XG_OP_R_R_OFFS5,      2, 0x5800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1659. 

  1659. 

  1660.   { "ldb",   M68XG_OP_RD_RB_RI,       2, 0x6000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1661. 

  1661.   { "ldw",   M68XG_OP_RD_RB_RI,       2, 0x6800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1662. 

  1662.   { "stb",   M68XG_OP_RD_RB_RI,       2, 0x7000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1663. 

  1663.   { "stw",   M68XG_OP_RD_RB_RI,       2, 0x7800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1664. 

  1664. 

  1665.   { "ldb",   M68XG_OP_RD_RB_RIp,      2, 0x6001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1666. 

  1666.   { "ldw",   M68XG_OP_RD_RB_RIp,      2, 0x6801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1667. 

  1667.   { "stb",   M68XG_OP_RD_RB_RIp,      2, 0x7001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1668. 

  1668.   { "stw",   M68XG_OP_RD_RB_RIp,      2, 0x7801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1669. 

  1669. 

  1670.   { "ldb",   M68XG_OP_RD_RB_mRI,      2, 0x6002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1671. 

  1671.   { "ldw",   M68XG_OP_RD_RB_mRI,      2, 0x6802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1672. 

  1672.   { "stb",   M68XG_OP_RD_RB_mRI,      2, 0x7002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1673. 

  1673.   { "stw",   M68XG_OP_RD_RB_mRI,      2, 0x7802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1674. 

  1674. /* Bit Field Instructions */
    1675. 

  1675.   { "bfext", M68XG_OP_R_R_R,          2, 0x6003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1676. 

  1676.   { "bfins", M68XG_OP_R_R_R,          2, 0x6803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1677. 

  1677.   { "bfinsi",M68XG_OP_R_R_R,          2, 0x7003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1678. 

  1678.   { "bfinsx",M68XG_OP_R_R_R,          2, 0x7803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },
    1679. 

  1679. /* Logic Immediate Instructions */
    1680. 

  1680.   { "andl",  M68XG_OP_R_IMM8,         2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1681. 

  1681.   { "andh",  M68XG_OP_R_IMM8,         2, 0x8800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1682. 

  1682.   { "bitl",  M68XG_OP_R_IMM8,         2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1683. 

  1683.   { "bith",  M68XG_OP_R_IMM8,         2, 0x9800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1684. 

  1684.   { "orl",   M68XG_OP_R_IMM8,         2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1685. 

  1685.   { "orh",   M68XG_OP_R_IMM8,         2, 0xa800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1686. 

  1686.   { "xnorl", M68XG_OP_R_IMM8,         2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1687. 

  1687.   { "xnorh", M68XG_OP_R_IMM8,         2, 0xb800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1688. 

  1688. /* Arithmetic Immediate Instructions */
    1689. 

  1689.   { "subl",  M68XG_OP_R_IMM8,         2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1690. 

  1690.   { "subh",  M68XG_OP_R_IMM8,         2, 0xc800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1691. 

  1691.   { "cmpl",  M68XG_OP_R_IMM8,         2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1692. 

  1692.   { "cpch",  M68XG_OP_R_IMM8,         2, 0xd800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1693. 

  1693.   { "addl",  M68XG_OP_R_IMM8,         2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1694. 

  1694.   { "addh",  M68XG_OP_R_IMM8,         2, 0xe800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1695. 

  1695.   { "ldl",   M68XG_OP_R_IMM8,         2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1696. 

  1696.   { "ldh",   M68XG_OP_R_IMM8,         2, 0xf800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },
    1697. 

  1697. /* 16 bit versions.
    1698. 

  1698.  * These are pseudo opcodes to allow 16 bit addresses to be passed.
    1699. 

  1699.  * The mask ensures that we will never disassemble to these instructions.
    1700. 

  1700.  */
    1701. 

  1701. /* Logic Immediate Instructions */
    1702. 

  1702.   { "and",   M68XG_OP_R_IMM16,        2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1703. 

  1703.   { "bit",   M68XG_OP_R_IMM16,        2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1704. 

  1704.   { "or",    M68XG_OP_R_IMM16,        2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1705. 

  1705.   { "xnor",  M68XG_OP_R_IMM16,        2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1706. 

  1706. /* Arithmetic Immediate Instructions */
    1707. 

  1707.   { "sub",   M68XG_OP_R_IMM16,        2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1708. 

  1708.   { "cmp",   M68XG_OP_R_IMM16,        2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1709. 

  1709.   { "add",   M68XG_OP_R_IMM16,        2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1710. 

  1710.  /* ld is for backwards compatability only, the correct opcode is ldw */
    1711. 

  1711.   { "ld",    M68XG_OP_R_IMM16,        2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },
    1712. 

  1712.   { "ldw",   M68XG_OP_R_IMM16,        2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }
    1713. 

  1713. };
    1714. 

  1714. 

  1715. const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes);
    1716. 

  1716. 

  1717. /* The following alias table provides source compatibility to
    1718. 

  1718.    move from 68HC11 assembly to 68HC12.  */
    1719. 

  1719. const struct m68hc12_opcode_alias m68hc12_alias[] = {
    1720. 

  1720.   { "abx", "leax b,x",   2, 0x1a, 0xe5 },
    1721. 

  1721.   { "aby", "leay b,y",   2, 0x19, 0xed },
    1722. 

  1722.   { "clc", "andcc #$fe", 2, 0x10, 0xfe },
    1723. 

  1723.   { "cli", "andcc #$ef", 2, 0x10, 0xef },
    1724. 

  1724.   { "clv", "andcc #$fd", 2, 0x10, 0xfd },
    1725. 

  1725.   { "des", "leas -1,sp", 2, 0x1b, 0x9f },
    1726. 

  1726.   { "ins", "leas 1,sp",  2, 0x1b, 0x81 },
    1727. 

  1727.   { "sec", "orcc #$01",  2, 0x14, 0x01 },
    1728. 

  1728.   { "sei", "orcc #$10",  2, 0x14, 0x10 },
    1729. 

  1729.   { "sev", "orcc #$02",  2, 0x14, 0x02 },
    1730. 

  1730.   { "tap", "tfr a,ccr",  2, 0xb7, 0x02 },
    1731. 

  1731.   { "tpa", "tfr ccr,a",  2, 0xb7, 0x20 },
    1732. 

  1732.   { "tsx", "tfr sp,x",   2, 0xb7, 0x75 },
    1733. 

  1733.   { "tsy", "tfr sp,y",   2, 0xb7, 0x76 },
    1734. 

  1734.   { "txs", "tfr x,sp",   2, 0xb7, 0x57 },
    1735. 

  1735.   { "tys", "tfr y,sp",   2, 0xb7, 0x67 },
    1736. 

  1736.   { "xgdx","exg d,x",    2, 0xb7, 0xc5 },
    1737. 

  1737.   { "xgdy","exg d,y",    2, 0xb7, 0xc6 }
    1738. 

  1738. };
    1739. 

  1739. const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias);
    1740. 

  1740.