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6502opcodes_03.html

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  1. 

  2. <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
    3. 

  3. <html><head><title>6502.org: Tutorials and Aids</title>
    4. 

  4. <meta name="description" content="Learn how to do all kinds of things with the 6502 microprocessor.">
    5. 

  5. <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
    6. 

  6. </head>
    7. 

  7. <body>
    8. 

  8. <a href="/">[Return to Main Page]</a>
    9. 

  9. <FONT size="+1">NMOS 6502 Opcodes</FONT>&nbsp;<FONT SIZE="-1">by John Pickens,
    10. 

  10. Updated by Bruce Clark and by Ed Spittles</FONT>
    11. 

  11. <BR><A HREF="tutorials.htm">[Up to Tutorials and Aids]</A>
    12. 

  12. <BR>
    13. 

  13. <HR>
    14. 

  14. <h2>INDEX</h2>
    15. 

  15. <TABLE border=2 cellpadding=2 width="90%" style="font-family:'Lucida Console', monospace">
    16. 

  16.   <TBODY>
    17. 

  17.   <TR>
    18. 

  18.     <TD align="center"><A
    19. 

  19.       href="#BRA">Branches</A></TD>
    20. 

  20.     <TD align="center"><A
    21. 

  21.       href="#DFLAG">Decimal Mode</A></TD>
    22. 

  22.     <TD align="center"><A
    23. 

  23.       href="#IFLAG">Interrupt Flag</A></TD>
    24. 

  24.     <TD align="center"><A
    25. 

  25.       href="#VFLAG">Overflow Flag</A></TD>
    26. 

  26.     <TD align="center"><A href="#PC">Program
    27. 

  27.       Counter</A></TD>
    28. 

  28.     <TD align="center"><A
    29. 

  29.       href="#STACK">Stack</A></TD>
    30. 

  30.     <TD align="center"><A
    31. 

  31.       href="#TIMES">Times</A></TD>
    32. 

  32.     <TD align="center"><A
    33. 

  33.       href="#WRAP">Wrap-around</A></TD></TR></TBODY></TABLE>
    34. 

  34. <P>
    35. 

  35. <TABLE border=2 cellPadding=2 width="90%">
    36. 

  36.   <TBODY>
    37. 

  37.   <TR>
    38. 

  38.     <TD align="center"><A
    39. 

  39.     href="#ADC">ADC</A></TD>
    40. 

  40.     <TD align="center"><A
    41. 

  41.     href="#AND">AND</A></TD>
    42. 

  42.     <TD align="center"><A
    43. 

  43.     href="#ASL">ASL</A></TD>
    44. 

  44.     <TD align="center"><A
    45. 

  45.     href="#BCC">BCC</A></TD>
    46. 

  46.     <TD align="center"><A
    47. 

  47.     href="#BCS">BCS</A></TD>
    48. 

  48.     <TD align="center"><A
    49. 

  49.     href="#BEQ">BEQ</A></TD>
    50. 

  50.     <TD align="center"><A
    51. 

  51.     href="#BIT">BIT</A></TD>
    52. 

  52.     <TD align="center"><A
    53. 

  53.     href="#BMI">BMI</A></TD>
    54. 

  54.     <TD align="center"><A
    55. 

  55.     href="#BNE">BNE</A></TD>
    56. 

  56.     <TD align="center"><A
    57. 

  57.     href="#BPL">BPL</A></TD>
    58. 

  58.     <TD align="center"><A
    59. 

  59.     href="#BRK">BRK</A></TD>
    60. 

  60.     <TD align="center"><A
    61. 

  61.     href="#BVC">BVC</A></TD>
    62. 

  62.     <TD align="center"><A
    63. 

  63.     href="#BVS">BVS</A></TD>
    64. 

  64.     <TD align="center"><A
    65. 

  65.     href="#CLC">CLC</A></TD></TR>
    66. 

  66.   <TR>
    67. 

  67.     <TD align="center"><A
    68. 

  68.     href="#CLD">CLD</A></TD>
    69. 

  69.     <TD align="center"><A
    70. 

  70.     href="#CLI">CLI</A></TD>
    71. 

  71.     <TD align="center"><A
    72. 

  72.     href="#CLV">CLV</A></TD>
    73. 

  73.     <TD align="center"><A
    74. 

  74.     href="#CMP">CMP</A></TD>
    75. 

  75.     <TD align="center"><A
    76. 

  76.     href="#CPX">CPX</A></TD>
    77. 

  77.     <TD align="center"><A
    78. 

  78.     href="#CPY">CPY</A></TD>
    79. 

  79.     <TD align="center"><A
    80. 

  80.     href="#DEC">DEC</A></TD>
    81. 

  81.     <TD align="center"><A
    82. 

  82.     href="#DEX">DEX</A></TD>
    83. 

  83.     <TD align="center"><A
    84. 

  84.     href="#DEY">DEY</A></TD>
    85. 

  85.     <TD align="center"><A
    86. 

  86.     href="#EOR">EOR</A></TD>
    87. 

  87.     <TD align="center"><A
    88. 

  88.     href="#INC">INC</A></TD>
    89. 

  89.     <TD align="center"><A
    90. 

  90.     href="#INX">INX</A></TD>
    91. 

  91.     <TD align="center"><A
    92. 

  92.     href="#INY">INY</A></TD>
    93. 

  93.     <TD align="center"><A
    94. 

  94.     href="#JMP">JMP</A></TD></TR>
    95. 

  95.   <TR>
    96. 

  96.     <TD align="center"><A
    97. 

  97.     href="#JSR">JSR</A></TD>
    98. 

  98.     <TD align="center"><A
    99. 

  99.     href="#LDA">LDA</A></TD>
    100. 

  100.     <TD align="center"><A
    101. 

  101.     href="#LDX">LDX</A></TD>
    102. 

  102.     <TD align="center"><A
    103. 

  103.     href="#LDY">LDY</A></TD>
    104. 

  104.     <TD align="center"><A
    105. 

  105.     href="#LSR">LSR</A></TD>
    106. 

  106.     <TD align="center"><A
    107. 

  107.     href="#NOP">NOP</A></TD>
    108. 

  108.     <TD align="center"><A
    109. 

  109.     href="#ORA">ORA</A></TD>
    110. 

  110.     <TD align="center"><A
    111. 

  111.     href="#PHA">PHA</A></TD>
    112. 

  112.     <TD align="center"><A
    113. 

  113.     href="#PHP">PHP</A></TD>
    114. 

  114.     <TD align="center"><A
    115. 

  115.     href="#PLA">PLA</A></TD>
    116. 

  116.     <TD align="center"><A
    117. 

  117.     href="#PLP">PLP</A></TD>
    118. 

  118.     <TD align="center"><A
    119. 

  119.     href="#ROL">ROL</A></TD>
    120. 

  120.     <TD align="center"><A
    121. 

  121.     href="#ROR">ROR</A></TD>
    122. 

  122.     <TD align="center"><A
    123. 

  123.     href="#RTI">RTI</A></TD></TR>
    124. 

  124.   <TR>
    125. 

  125.     <TD align="center"><A
    126. 

  126.     href="#RTS">RTS</A></TD>
    127. 

  127.     <TD align="center"><A
    128. 

  128.     href="#SBC">SBC</A></TD>
    129. 

  129.     <TD align="center"><A
    130. 

  130.     href="#SEC">SEC</A></TD>
    131. 

  131.     <TD align="center"><A
    132. 

  132.     href="#SED">SED</A></TD>
    133. 

  133.     <TD align="center"><A
    134. 

  134.     href="#SEI">SEI</A></TD>
    135. 

  135.     <TD align="center"><A
    136. 

  136.     href="#STA">STA</A></TD>
    137. 

  137.     <TD align="center"><A
    138. 

  138.     href="#STX">STX</A></TD>
    139. 

  139.     <TD align="center"><A
    140. 

  140.     href="#STY">STY</A></TD>
    141. 

  141.     <TD align="center"><A
    142. 

  142.     href="#TAX">TAX</A></TD>
    143. 

  143.     <TD align="center"><A
    144. 

  144.     href="#TAY">TAY</A></TD>
    145. 

  145.     <TD align="center"><A
    146. 

  146.     href="#TSX">TSX</A></TD>
    147. 

  147.     <TD align="center"><A
    148. 

  148.     href="#TXA">TXA</A></TD>
    149. 

  149.     <TD align="center"><A
    150. 

  150.     href="#TXS">TXS</A></TD>
    151. 

  151.     <TD align="center"><A
    152. 

  152.     href="#TYA">TYA</A></TD></TR></TBODY></TABLE>
    153. 

  153. <P><A name=ADC>&nbsp;</A>
    154. 

  154. <H2>ADC (ADd with Carry)</H2>
    155. 

  155. <P>Affects Flags: S V Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    156. 

  156. Immediate     ADC #$44      $69  2   2
    157. 

  157. Zero Page     ADC $44       $65  2   3
    158. 

  158. Zero Page,X   ADC $44,X     $75  2   4
    159. 

  159. Absolute      ADC $4400     $6D  3   4
    160. 

  160. Absolute,X    ADC $4400,X   $7D  3   4+
    161. 

  161. Absolute,Y    ADC $4400,Y   $79  3   4+
    162. 

  162. Indirect,X    ADC ($44,X)   $61  2   6
    163. 

  163. Indirect,Y    ADC ($44),Y   $71  2   5+
    164. 

  164. 

  165. + add 1 cycle if page boundary crossed
    166. 

  166. 

  167. </PRE>ADC results are dependant on the setting of the <A
    168. 

  168. href="#DFLAG">decimal flag</A>. In decimal
    169. 

  169. mode, addition is carried out on the assumption that the values involved are
    170. 

  170. packed BCD (Binary Coded Decimal).
    171. 

  171. <P>There is no way to add without carry.
    172. 

  172. 

  173. <P><A name=AND>&nbsp;</A>
    174. 

  174. <H2>AND (bitwise AND with accumulator) </H2>
    175. 

  175. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    176. 

  176. Immediate     AND #$44      $29  2   2
    177. 

  177. Zero Page     AND $44       $25  2   3
    178. 

  178. Zero Page,X   AND $44,X     $35  2   4
    179. 

  179. Absolute      AND $4400     $2D  3   4
    180. 

  180. Absolute,X    AND $4400,X   $3D  3   4+
    181. 

  181. Absolute,Y    AND $4400,Y   $39  3   4+
    182. 

  182. Indirect,X    AND ($44,X)   $21  2   6
    183. 

  183. Indirect,Y    AND ($44),Y   $31  2   5+
    184. 

  184. 

  185. + add 1 cycle if page boundary crossed
    186. 

  186. </PRE>
    187. 

  187. 

  188. <P><A name=ASL>&nbsp;</A>
    189. 

  189. <H2>ASL (Arithmetic Shift Left) </H2>
    190. 

  190. <P>Affects Flags: S Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    191. 

  191. Accumulator   ASL A         $0A  1   2
    192. 

  192. Zero Page     ASL $44       $06  2   5
    193. 

  193. Zero Page,X   ASL $44,X     $16  2   6
    194. 

  194. Absolute      ASL $4400     $0E  3   6
    195. 

  195. Absolute,X    ASL $4400,X   $1E  3   7
    196. 

  196. 

  197. </PRE>ASL shifts all bits left one position. 0 is shifted into bit 0 and the
    198. 

  198. original bit 7 is shifted into the Carry.
    199. 

  199. <P>
    200. 

  200. <P><A name=BIT>&nbsp;</A>
    201. 

  201. <H2>BIT (test BITs) </H2>
    202. 

  202. <P>Affects Flags: N V Z <PRE>MODE           SYNTAX       HEX LEN TIM
    203. 

  203. Zero Page     BIT $44       $24  2   3
    204. 

  204. Absolute      BIT $4400     $2C  3   4
    205. 

  205. 

  206. </PRE>BIT sets the Z flag as though the value in the address tested were ANDed
    207. 

  207. with the accumulator. The S and V flags are set to match bits 7 and 6
    208. 

  208. respectively in the value stored at the tested address.
    209. 

  209. <P>BIT is often used to skip one or two following bytes as in:
    210. 

  210. <P><PRE>CLOSE1 LDX #$10   If entered here, we
    211. 

  211.        .BYTE $2C  effectively perform
    212. 

  212. CLOSE2 LDX #$20   a BIT test on $20A2,
    213. 

  213.        .BYTE $2C  another one on $30A2,
    214. 

  214. CLOSE3 LDX #$30   and end up with the X
    215. 

  215. CLOSEX LDA #12    register still at $10
    216. 

  216.        STA ICCOM,X upon arrival here.
    217. 

  217. 

  218. </PRE>
    219. 

  219. Beware: a BIT instruction used in this way as a NOP does have effects: the flags
    220. 

  220. may be modified, and the read of the absolute address, if it happens to access an
    221. 

  221. I/O device, may cause an unwanted action.
    222. 

  222. <P><A name=BCC>&nbsp;</A> <A name=BCS>&nbsp;</A> <A name=BEQ>&nbsp;</A> <A
    223. 

  223. name=BNE>&nbsp;</A> <A name=BMI>&nbsp;</A> <A name=BPL>&nbsp;</A> <A
    224. 

  224. name=BVC>&nbsp;</A> <A name=BVS>&nbsp;</A> <A name=BRA>&nbsp;</A>
    225. 

  225. <H2>Branch Instructions</H2>
    226. 

  226. <P>Affect Flags: none
    227. 

  227. <P>All branches are relative mode and have a length of two bytes. Syntax is "Bxx
    228. 

  228. Displacement" or (better) "Bxx Label". See the notes on the <A
    229. 

  229. href="#PC">Program Counter</A> for more on
    230. 

  230. displacements.
    231. 

  231. <P>Branches are dependant on the status of the flag bits when the op code is
    232. 

  232. encountered. A branch not taken requires two machine cycles. Add one if the
    233. 

  233. branch is taken and add one more if the branch crosses a page boundary. <PRE>MNEMONIC                       HEX
    234. 

  234. BPL (Branch on PLus)           $10
    235. 

  235. BMI (Branch on MInus)          $30
    236. 

  236. BVC (Branch on oVerflow Clear) $50
    237. 

  237. BVS (Branch on oVerflow Set)   $70
    238. 

  238. BCC (Branch on Carry Clear)    $90
    239. 

  239. BCS (Branch on Carry Set)      $B0
    240. 

  240. BNE (Branch on Not Equal)      $D0
    241. 

  241. BEQ (Branch on EQual)          $F0
    242. 

  242. 

  243. </PRE>There is no BRA (BRanch Always) instruction but it can be easily emulated
    244. 

  244. by branching on the basis of a known condition. One of the best flags to use for
    245. 

  245. this purpose is the <A
    246. 

  246. href="#VFLAG">oVerflow</A> which is unchanged
    247. 

  247. by all but addition and subtraction operations.
    248. 

  248. <P>
    249. 

  249. A page boundary crossing occurs when the branch destination is on a different
    250. 

  250. page than the instruction AFTER the branch instruction. For example:
    251. 

  251. <pre>
    252. 

  252.   SEC
    253. 

  253.   BCS LABEL
    254. 

  254.   NOP
    255. 

  255. </pre>
    256. 

  256. A page boundary crossing occurs (i.e. the BCS takes 4 cycles) when (the
    257. 

  257. address of) LABEL and the NOP are on different pages. This means that
    258. 

  258. <pre>
    259. 

  259.         CLV
    260. 

  260.         BVC LABEL
    261. 

  261.   LABEL NOP
    262. 

  262. </pre>
    263. 

  263. the BVC instruction will take 3 cycles no matter what address it is located
    264. 

  264. at.
    265. 

  265. <P>
    266. 

  266. <P><A name=BRK>&nbsp;</A>
    267. 

  267. <H2>BRK (BReaK) </H2>
    268. 

  268. <P>Affects Flags: B <PRE>MODE           SYNTAX       HEX LEN TIM
    269. 

  269. Implied       BRK           $00  1   7
    270. 

  270. 

  271. </PRE>BRK causes a non-maskable interrupt and increments the program counter by
    272. 

  272. one.  Therefore an <A href="#RTI">RTI</A> will
    273. 

  273. go to the address of the BRK +2 so that BRK may be used to replace a
    274. 

  274. two-byte instruction for debugging and the subsequent RTI will be correct.
    275. 

  275. <P>
    276. 

  276. <P><A name=CMP>&nbsp;</A>
    277. 

  277. <H2>CMP (CoMPare accumulator) </H2>
    278. 

  278. <P>Affects Flags: S Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    279. 

  279. Immediate     CMP #$44      $C9  2   2
    280. 

  280. Zero Page     CMP $44       $C5  2   3
    281. 

  281. Zero Page,X   CMP $44,X     $D5  2   4
    282. 

  282. Absolute      CMP $4400     $CD  3   4
    283. 

  283. Absolute,X    CMP $4400,X   $DD  3   4+
    284. 

  284. Absolute,Y    CMP $4400,Y   $D9  3   4+
    285. 

  285. Indirect,X    CMP ($44,X)   $C1  2   6
    286. 

  286. Indirect,Y    CMP ($44),Y   $D1  2   5+
    287. 

  287. 

  288. + add 1 cycle if page boundary crossed
    289. 

  289. 

  290. </PRE>Compare sets flags as if a subtraction had been carried out. If the value
    291. 

  291. in the accumulator is equal or greater than the compared value, the Carry will
    292. 

  292. be set. The equal (Z) and sign (S) flags will be set based on equality or lack
    293. 

  293. thereof and the sign (i.e. A&gt;=$80) of the accumulator.
    294. 

  294. <P>
    295. 

  295. <P><A name=CPX>&nbsp;</A>
    296. 

  296. <H2>CPX (ComPare X register) </H2>
    297. 

  297. <P>Affects Flags: S Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    298. 

  298. Immediate     CPX #$44      $E0  2   2
    299. 

  299. Zero Page     CPX $44       $E4  2   3
    300. 

  300. Absolute      CPX $4400     $EC  3   4
    301. 

  301. 

  302. </PRE>Operation and flag results are identical to equivalent mode accumulator <A
    303. 

  303. href="#CMP">CMP</A> ops.
    304. 

  304. <P>
    305. 

  305. <P><A name=CPY>&nbsp;</A>
    306. 

  306. <H2>CPY (ComPare Y register) </H2>
    307. 

  307. <P>Affects Flags: S Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    308. 

  308. Immediate     CPY #$44      $C0  2   2
    309. 

  309. Zero Page     CPY $44       $C4  2   3
    310. 

  310. Absolute      CPY $4400     $CC  3   4
    311. 

  311. 

  312. </PRE>Operation and flag results are identical to equivalent mode accumulator <A
    313. 

  313. href="#CMP">CMP</A> ops.
    314. 

  314. <P>
    315. 

  315. <P><A name=DEC>&nbsp;</A>
    316. 

  316. <H2>DEC (DECrement memory) </H2>
    317. 

  317. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    318. 

  318. Zero Page     DEC $44       $C6  2   5
    319. 

  319. Zero Page,X   DEC $44,X     $D6  2   6
    320. 

  320. Absolute      DEC $4400     $CE  3   6
    321. 

  321. Absolute,X    DEC $4400,X   $DE  3   7
    322. 

  322. 

  323. </PRE>
    324. 

  324. <P><A name=EOR>&nbsp;</A>
    325. 

  325. <H2>EOR (bitwise Exclusive OR) </H2>
    326. 

  326. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    327. 

  327. Immediate     EOR #$44      $49  2   2
    328. 

  328. Zero Page     EOR $44       $45  2   3
    329. 

  329. Zero Page,X   EOR $44,X     $55  2   4
    330. 

  330. Absolute      EOR $4400     $4D  3   4
    331. 

  331. Absolute,X    EOR $4400,X   $5D  3   4+
    332. 

  332. Absolute,Y    EOR $4400,Y   $59  3   4+
    333. 

  333. Indirect,X    EOR ($44,X)   $41  2   6
    334. 

  334. Indirect,Y    EOR ($44),Y   $51  2   5+
    335. 

  335. 

  336. + add 1 cycle if page boundary crossed
    337. 

  337. </PRE>
    338. 

  338. <P><A name=CLC>&nbsp;</A> <A name=SEC>&nbsp;</A> <A name=CLD>&nbsp;</A> <A
    339. 

  339. name=SED>&nbsp;</A> <A name=CLI>&nbsp;</A> <A name=SEI>&nbsp;</A> <A
    340. 

  340. name=CLV>&nbsp;</A>
    341. 

  341. <H2>Flag (Processor Status) Instructions</H2>
    342. 

  342. <P>Affect Flags: as noted
    343. 

  343. <P>These instructions are implied mode, have a length of one byte and require
    344. 

  344. two machine cycles. <PRE>MNEMONIC                       HEX
    345. 

  345. CLC (CLear Carry)              $18
    346. 

  346. SEC (SEt Carry)                $38
    347. 

  347. CLI (CLear Interrupt)          $58
    348. 

  348. SEI (SEt Interrupt)            $78
    349. 

  349. CLV (CLear oVerflow)           $B8
    350. 

  350. CLD (CLear Decimal)            $D8
    351. 

  351. SED (SEt Decimal)              $F8
    352. 

  352. 

  353. </PRE>Notes:
    354. 

  354. <P><A name=IFLAG>&nbsp;</A> The Interrupt flag is used to prevent (SEI) or
    355. 

  355. enable (CLI) maskable interrupts (aka IRQ's). It does not signal the presence or
    356. 

  356. absence of an interrupt condition. The 6502 will set this flag automatically in
    357. 

  357. response to an interrupt and restore it to its prior status on completion of the
    358. 

  358. interrupt service routine. If you want your interrupt service routine to permit
    359. 

  359. other maskable interrupts, you must clear the I flag in your code.
    360. 

  360. <P><A name=DFLAG>&nbsp;</A> The Decimal flag controls how the 6502 adds and
    361. 

  361. subtracts. If set, arithmetic is carried out in packed binary coded decimal.
    362. 

  362. This flag is unchanged by interrupts and is unknown on power-up. The implication
    363. 

  363. is that a CLD should be included in boot or interrupt coding.
    364. 

  364. <P><A name=VFLAG>&nbsp;</A> The Overflow flag is generally misunderstood and
    365. 

  365. therefore under-utilised. After an ADC or SBC instruction, the overflow flag
    366. 

  366. will be set if the twos complement result is less than -128 or greater than
    367. 

  367. +127, and it will cleared otherwise. In twos complement, $80 through $FF
    368. 

  368. represents -128 through -1, and $00 through $7F represents 0 through +127.
    369. 

  369. Thus, after:
    370. 

  370. <pre>
    371. 

  371.   CLC
    372. 

  372.   LDA #$7F ;   +127
    373. 

  373.   ADC #$01 ; +   +1
    374. 

  374. </pre>
    375. 

  375. the overflow flag is 1 (+127 + +1 = +128), and after:
    376. 

  376. <pre>
    377. 

  377.   CLC
    378. 

  378.   LDA #$81 ;   -127
    379. 

  379.   ADC #$FF ; +   -1
    380. 

  380. </pre>
    381. 

  381. the overflow flag is 0 (-127 + -1 = -128). The overflow flag is not
    382. 

  382. affected by increments, decrements, shifts and logical operations i.e. only
    383. 

  383. ADC, BIT, CLV, PLP, RTI and SBC affect it. There is no op code to set the
    384. 

  384. overflow but a BIT test on an RTS instruction will do the trick.
    385. 

  385. <P>
    386. 

  386. <P>
    387. 

  387. <P><A name=INC>&nbsp;</A>
    388. 

  388. <H2>INC (INCrement memory) </H2>
    389. 

  389. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    390. 

  390. Zero Page     INC $44       $E6  2   5
    391. 

  391. Zero Page,X   INC $44,X     $F6  2   6
    392. 

  392. Absolute      INC $4400     $EE  3   6
    393. 

  393. Absolute,X    INC $4400,X   $FE  3   7
    394. 

  394. </PRE>
    395. 

  395. <P>
    396. 

  396. <P>
    397. 

  397. <P><A name=JMP>&nbsp;</A>
    398. 

  398. <H2>JMP (JuMP) </H2>
    399. 

  399. <P>Affects Flags: none <PRE>
    400. 

  400. MODE           SYNTAX       HEX LEN TIM
    401. 

  401. Absolute      JMP $5597     $4C  3   3
    402. 

  402. Indirect      JMP ($5597)   $6C  3   5
    403. 

  403. 

  404. </PRE>JMP transfers program execution to the following address (absolute) or to
    405. 

  405. the location contained in the following address (indirect). Note that there is
    406. 

  406. no carry associated with the indirect jump so: <PRE><strong>AN INDIRECT JUMP MUST NEVER USE A
    407. 

  407. VECTOR BEGINNING ON THE LAST BYTE
    408. 

  408. OF A PAGE</strong>
    409. 

  409. </PRE>For example if address $3000 contains $40, $30FF contains $80, and $3100
    410. 

  410. contains $50, the result of JMP ($30FF) will be a transfer of control to $4080
    411. 

  411. rather than $5080 as you intended i.e. the 6502 took the low byte of the address
    412. 

  412. from $30FF and the high byte from $3000.
    413. 

  413. <P>
    414. 

  414. <P>
    415. 

  415. <P><A name=JSR>&nbsp;</A>
    416. 

  416. <H2>JSR (Jump to SubRoutine) </H2>
    417. 

  417. <P>Affects Flags: none <PRE>MODE           SYNTAX       HEX LEN TIM
    418. 

  418. Absolute      JSR $5597     $20  3   6
    419. 

  419. 

  420. </PRE>JSR pushes the address-1 of the next operation on to the stack before
    421. 

  421. transferring program control to the following address. Subroutines are normally
    422. 

  422. terminated by a <A href="#RTS">RTS</A> op
    423. 

  423. code.
    424. 

  424. <P>
    425. 

  425. <P>
    426. 

  426. <P><A name=LDA>&nbsp;</A>
    427. 

  427. <H2>LDA (LoaD Accumulator) </H2>
    428. 

  428. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    429. 

  429. Immediate     LDA #$44      $A9  2   2
    430. 

  430. Zero Page     LDA $44       $A5  2   3
    431. 

  431. Zero Page,X   LDA $44,X     $B5  2   4
    432. 

  432. Absolute      LDA $4400     $AD  3   4
    433. 

  433. Absolute,X    LDA $4400,X   $BD  3   4+
    434. 

  434. Absolute,Y    LDA $4400,Y   $B9  3   4+
    435. 

  435. Indirect,X    LDA ($44,X)   $A1  2   6
    436. 

  436. Indirect,Y    LDA ($44),Y   $B1  2   5+
    437. 

  437. 

  438. + add 1 cycle if page boundary crossed
    439. 

  439. </PRE>
    440. 

  440. <P>
    441. 

  441. <P>
    442. 

  442. <P><A name=LDX>&nbsp;</A>
    443. 

  443. <H2>LDX (LoaD X register) </H2>
    444. 

  444. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    445. 

  445. Immediate     LDX #$44      $A2  2   2
    446. 

  446. Zero Page     LDX $44       $A6  2   3
    447. 

  447. Zero Page,Y   LDX $44,Y     $B6  2   4
    448. 

  448. Absolute      LDX $4400     $AE  3   4
    449. 

  449. Absolute,Y    LDX $4400,Y   $BE  3   4+
    450. 

  450. 

  451. + add 1 cycle if page boundary crossed
    452. 

  452. </PRE>
    453. 

  453. <P>
    454. 

  454. <P>
    455. 

  455. <P><A name=LDY>&nbsp;</A>
    456. 

  456. <H2>LDY (LoaD Y register) </H2>
    457. 

  457. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    458. 

  458. Immediate     LDY #$44      $A0  2   2
    459. 

  459. Zero Page     LDY $44       $A4  2   3
    460. 

  460. Zero Page,X   LDY $44,X     $B4  2   4
    461. 

  461. Absolute      LDY $4400     $AC  3   4
    462. 

  462. Absolute,X    LDY $4400,X   $BC  3   4+
    463. 

  463. 

  464. + add 1 cycle if page boundary crossed
    465. 

  465. </PRE>
    466. 

  466. <P>
    467. 

  467. <P>
    468. 

  468. <P><A name=LSR>&nbsp;</A>
    469. 

  469. <H2>LSR (Logical Shift Right) </H2>
    470. 

  470. <P>Affects Flags: S Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    471. 

  471. Accumulator   LSR A         $4A  1   2
    472. 

  472. Zero Page     LSR $44       $46  2   5
    473. 

  473. Zero Page,X   LSR $44,X     $56  2   6
    474. 

  474. Absolute      LSR $4400     $4E  3   6
    475. 

  475. Absolute,X    LSR $4400,X   $5E  3   7
    476. 

  476. 

  477. </PRE>LSR shifts all bits right one position. 0 is shifted into bit 7 and the
    478. 

  478. original bit 0 is shifted into the Carry.
    479. 

  479. <P>
    480. 

  480. <P>
    481. 

  481. <P><A name=WRAP>&nbsp;</A>
    482. 

  482. <H2>Wrap-Around</H2>
    483. 

  483. <P>Use caution with indexed zero page operations as they are subject to
    484. 

  484. wrap-around. For example, if the X register holds $FF and you execute LDA $80,X
    485. 

  485. you will not access $017F as you might expect; instead you access $7F i.e.
    486. 

  486. $80-1. This characteristic can be used to advantage but make sure your code is
    487. 

  487. well commented.
    488. 

  488. <P>
    489. 

  489. It is possible, however, to access $017F when X = $FF by using the Absolute,X
    490. 

  490. addressing mode of LDA $80,X.  That is, instead of:
    491. 

  491. <pre>
    492. 

  492.   LDA $80,X    ; ZeroPage,X - the resulting object code is: B5 80
    493. 

  493. </pre>
    494. 

  494. which accesses $007F when X=$FF, use:
    495. 

  495. <pre>
    496. 

  496.   LDA $0080,X  ; Absolute,X - the resulting object code is: BD 80 00
    497. 

  497. </pre>
    498. 

  498. which accesses $017F when X = $FF (a at cost of one additional byte and one
    499. 

  499. additional cycle). All of the ZeroPage,X and ZeroPage,Y instructions except
    500. 

  500. STX ZeroPage,Y and STY ZeroPage,X have a corresponding Absolute,X and
    501. 

  501. Absolute,Y instruction. Unfortunately, a lot of 6502 assemblers don't have an
    502. 

  502. easy way to force Absolute addressing, i.e. most will assemble a LDA $0080,X
    503. 

  503. as B5 80.  One way to overcome this is to insert the bytes using the .BYTE
    504. 

  504. pseudo-op (on some 6502 assemblers this pseudo-op is called DB or DFB,
    505. 

  505. consult the assembler documentation) as follows:
    506. 

  506. <pre>
    507. 

  507.   .BYTE $BD,$80,$00  ; LDA $0080,X (absolute,X addressing mode)
    508. 

  508. </pre>
    509. 

  509. The comment is optional, but highly recommended for clarity.
    510. 

  510. <P>In cases where you are writing code that will be relocated you must consider
    511. 

  511. wrap-around when assigning dummy values for addresses that will be adjusted.
    512. 

  512. Both zero and the semi-standard $FFFF should be avoided for dummy labels. The
    513. 

  513. use of zero or zero page values will result in assembled code with zero page
    514. 

  514. opcodes when you wanted absolute codes. With $FFFF, the problem is in
    515. 

  515. addresses+1 as you wrap around to page 0.
    516. 

  516. <P><A name=PC>&nbsp;</A>
    517. 

  517. <H2>Program Counter</H2>
    518. 

  518. <P>When the 6502 is ready for the next instruction it increments the program
    519. 

  519. counter before fetching the instruction. Once it has the op code, it increments
    520. 

  520. the program counter by the length of the operand, if any. This must be accounted
    521. 

  521. for when calculating branches or when pushing bytes to create a false return
    522. 

  522. address (i.e. jump table addresses are made up of addresses-1 when it is
    523. 

  523. intended to use an RTS rather than a JMP).
    524. 

  524. <P>The program counter is loaded least signifigant byte first. Therefore the
    525. 

  525. most signifigant byte must be pushed first when creating a false return address.
    526. 

  526. 

  527. <P>When calculating branches a forward branch of 6 skips the following 6 bytes
    528. 

  528. so, effectively the program counter points to the address that is 8 bytes beyond
    529. 

  529. the address of the branch opcode; and a backward branch of $FA (256-6) goes to
    530. 

  530. an address 4 bytes before the branch instruction.
    531. 

  531. <P><A name=TIMES>&nbsp;</A>
    532. 

  532. <H2>Execution Times</H2>
    533. 

  533. <P>Op code execution times are measured in machine cycles; one machine cycle
    534. 

  534. equals one clock cycle. Many instructions require one extra cycle for
    535. 

  535. execution if a page boundary is crossed; these are indicated by a + following
    536. 

  536. the time values shown.
    537. 

  537. <P>
    538. 

  538. <P>
    539. 

  539. <P><A name=NOP>&nbsp;</A>
    540. 

  540. <H2>NOP (No OPeration) </H2>
    541. 

  541. <P>Affects Flags: none <PRE>MODE           SYNTAX       HEX LEN TIM
    542. 

  542. Implied       NOP           $EA  1   2
    543. 

  543. 

  544. </PRE>NOP is used to reserve space for future modifications or effectively REM
    545. 

  545. out existing code.
    546. 

  546. <P>
    547. 

  547. <P>
    548. 

  548. <P><A name=ORA>&nbsp;</A>
    549. 

  549. <H2>ORA (bitwise OR with Accumulator) </H2>
    550. 

  550. <P>Affects Flags: S Z <PRE>MODE           SYNTAX       HEX LEN TIM
    551. 

  551. Immediate     ORA #$44      $09  2   2
    552. 

  552. Zero Page     ORA $44       $05  2   3
    553. 

  553. Zero Page,X   ORA $44,X     $15  2   4
    554. 

  554. Absolute      ORA $4400     $0D  3   4
    555. 

  555. Absolute,X    ORA $4400,X   $1D  3   4+
    556. 

  556. Absolute,Y    ORA $4400,Y   $19  3   4+
    557. 

  557. Indirect,X    ORA ($44,X)   $01  2   6
    558. 

  558. Indirect,Y    ORA ($44),Y   $11  2   5+
    559. 

  559. 

  560. + add 1 cycle if page boundary crossed
    561. 

  561. </PRE>
    562. 

  562. <P>
    563. 

  563. <P>
    564. 

  564. <P><A name=TAX>&nbsp;</A> <A name=TXA>&nbsp;</A> <A name=TAY>&nbsp;</A> <A
    565. 

  565. name=TYA>&nbsp;</A> <A name=INX>&nbsp;</A> <A name=DEX>&nbsp;</A> <A
    566. 

  566. name=INY>&nbsp;</A> <A name=DEY>&nbsp;</A>
    567. 

  567. <H2>Register Instructions </H2>
    568. 

  568. <P>Affect Flags: S Z
    569. 

  569. <P>These instructions are implied mode, have a length of one byte and require
    570. 

  570. two machine cycles. <PRE>MNEMONIC                 HEX
    571. 

  571. TAX (Transfer A to X)    $AA
    572. 

  572. TXA (Transfer X to A)    $8A
    573. 

  573. DEX (DEcrement X)        $CA
    574. 

  574. INX (INcrement X)        $E8
    575. 

  575. TAY (Transfer A to Y)    $A8
    576. 

  576. TYA (Transfer Y to A)    $98
    577. 

  577. DEY (DEcrement Y)        $88
    578. 

  578. INY (INcrement Y)        $C8
    579. 

  579. </PRE>
    580. 

  580. <P>
    581. 

  581. <P>
    582. 

  582. <P><A name=ROL>&nbsp;</A>
    583. 

  583. <H2>ROL (ROtate Left) </H2>
    584. 

  584. <P>Affects Flags: S Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    585. 

  585. Accumulator   ROL A         $2A  1   2
    586. 

  586. Zero Page     ROL $44       $26  2   5
    587. 

  587. Zero Page,X   ROL $44,X     $36  2   6
    588. 

  588. Absolute      ROL $4400     $2E  3   6
    589. 

  589. Absolute,X    ROL $4400,X   $3E  3   7
    590. 

  590. 

  591. </PRE>ROL shifts all bits left one position. The Carry is shifted into bit 0 and
    592. 

  592. the original bit 7 is shifted into the Carry.
    593. 

  593. <P>
    594. 

  594. <P>
    595. 

  595. <P><A name=ROR>&nbsp;</A>
    596. 

  596. <H2>ROR (ROtate Right) </H2>
    597. 

  597. <P>Affects Flags: S Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    598. 

  598. Accumulator   ROR A         $6A  1   2
    599. 

  599. Zero Page     ROR $44       $66  2   5
    600. 

  600. Zero Page,X   ROR $44,X     $76  2   6
    601. 

  601. Absolute      ROR $4400     $6E  3   6
    602. 

  602. Absolute,X    ROR $4400,X   $7E  3   7
    603. 

  603. 

  604. </PRE>ROR shifts all bits right one position. The Carry is shifted into bit 7
    605. 

  605. and the original bit 0 is shifted into the Carry.
    606. 

  606. <P>
    607. 

  607. <P>
    608. 

  608. <P><A name=RTI>&nbsp;</A>
    609. 

  609. <H2>RTI (ReTurn from Interrupt) </H2>
    610. 

  610. <P>Affects Flags: all <PRE>MODE           SYNTAX       HEX LEN TIM
    611. 

  611. Implied       RTI           $40  1   6
    612. 

  612. 

  613. </PRE>RTI retrieves the Processor Status Word (flags) and the Program Counter
    614. 

  614. from the stack in that order (interrupts push the PC first and then the PSW).
    615. 

  615. <P>Note that unlike RTS, the return address on the stack is the actual address
    616. 

  616. rather than the address-1.
    617. 

  617. <P>
    618. 

  618. <P>
    619. 

  619. <P><A name=RTS>&nbsp;</A>
    620. 

  620. <H2>RTS (ReTurn from Subroutine) </H2>
    621. 

  621. <P>Affects Flags: none <PRE>MODE           SYNTAX       HEX LEN TIM
    622. 

  622. Implied       RTS           $60  1   6
    623. 

  623. 

  624. </PRE>RTS pulls the top two bytes off the stack (low byte first) and transfers
    625. 

  625. program control to that address+1. It is used, as expected, to exit a subroutine
    626. 

  626. invoked via <A href="#JSR">JSR</A> which
    627. 

  627. pushed the address-1.
    628. 

  628. <P>RTS is frequently used to implement a jump table where addresses-1 are pushed
    629. 

  629. onto the stack and accessed via RTS eg. to access the second of four routines: <PRE> LDX #1
    630. 

  630.  JSR EXEC
    631. 

  631.  JMP SOMEWHERE
    632. 

  632. 

  633. LOBYTE
    634. 

  634.  .BYTE &lt;ROUTINE0-1,&lt;ROUTINE1-1
    635. 

  635.  .BYTE &lt;ROUTINE2-1,&lt;ROUTINE3-1
    636. 

  636. 

  637. HIBYTE
    638. 

  638.  .BYTE &gt;ROUTINE0-1,&gt;ROUTINE1-1
    639. 

  639.  .BYTE &gt;ROUTINE2-1,&gt;ROUTINE3-1
    640. 

  640. 

  641. EXEC
    642. 

  642.  LDA HIBYTE,X
    643. 

  643.  PHA
    644. 

  644.  LDA LOBYTE,X
    645. 

  645.  PHA
    646. 

  646.  RTS
    647. 

  647. </PRE>
    648. 

  648. <P>
    649. 

  649. <P><A name=SBC>&nbsp;</A>
    650. 

  650. <H2>SBC (SuBtract with Carry)</H2>
    651. 

  651. <P>Affects Flags: S V Z C <PRE>MODE           SYNTAX       HEX LEN TIM
    652. 

  652. Immediate     SBC #$44      $E9  2   2
    653. 

  653. Zero Page     SBC $44       $E5  2   3
    654. 

  654. Zero Page,X   SBC $44,X     $F5  2   4
    655. 

  655. Absolute      SBC $4400     $ED  3   4
    656. 

  656. Absolute,X    SBC $4400,X   $FD  3   4+
    657. 

  657. Absolute,Y    SBC $4400,Y   $F9  3   4+
    658. 

  658. Indirect,X    SBC ($44,X)   $E1  2   6
    659. 

  659. Indirect,Y    SBC ($44),Y   $F1  2   5+
    660. 

  660. 

  661. + add 1 cycle if page boundary crossed
    662. 

  662. 

  663. </PRE>SBC results are dependant on the setting of the decimal flag. In decimal
    664. 

  664. mode, subtraction is carried out on the assumption that the values involved are
    665. 

  665. packed BCD (Binary Coded Decimal).
    666. 

  666. <P>There is no way to subtract without the carry which works as an inverse
    667. 

  667. borrow. i.e, to subtract you set the carry before the operation. If the carry is
    668. 

  668. cleared by the operation, it indicates a borrow occurred.
    669. 

  669. <P>
    670. 

  670. <P>
    671. 

  671. <P><A name=STA>&nbsp;</A>
    672. 

  672. <H2>STA (STore Accumulator) </H2>
    673. 

  673. <P>Affects Flags: none <PRE>MODE           SYNTAX       HEX LEN TIM
    674. 

  674. Zero Page     STA $44       $85  2   3
    675. 

  675. Zero Page,X   STA $44,X     $95  2   4
    676. 

  676. Absolute      STA $4400     $8D  3   4
    677. 

  677. Absolute,X    STA $4400,X   $9D  3   5
    678. 

  678. Absolute,Y    STA $4400,Y   $99  3   5
    679. 

  679. Indirect,X    STA ($44,X)   $81  2   6
    680. 

  680. Indirect,Y    STA ($44),Y   $91  2   6
    681. 

  681. </PRE>
    682. 

  682. <P>
    683. 

  683. <P><A name=TXS>&nbsp;</A> <A name=TSX>&nbsp;</A> <A name=PHA>&nbsp;</A> <A
    684. 

  684. name=PLA>&nbsp;</A> <A name=PHP>&nbsp;</A> <A name=PLP>&nbsp;</A> <A
    685. 

  685. name=STACK>&nbsp;</A>
    686. 

  686. <H2>Stack Instructions</H2>
    687. 

  687. <P>These instructions are implied mode, have a length of one byte and require
    688. 

  688. machine cycles as indicated. The "PuLl" operations are known as "POP" on most
    689. 

  689. other microprocessors. With the 6502, the stack is always on page one
    690. 

  690. ($100-$1FF) and works top down. <PRE>MNEMONIC                        HEX TIM
    691. 

  691. TXS (Transfer X to Stack ptr)   $9A  2
    692. 

  692. TSX (Transfer Stack ptr to X)   $BA  2
    693. 

  693. PHA (PusH Accumulator)          $48  3
    694. 

  694. PLA (PuLl Accumulator)          $68  4
    695. 

  695. PHP (PusH Processor status)     $08  3
    696. 

  696. PLP (PuLl Processor status)     $28  4
    697. 

  697. </PRE>
    698. 

  698. <P>
    699. 

  699. <P>
    700. 

  700. <P><A name=STX>&nbsp;</A>
    701. 

  701. <H2>STX (STore X register)</H2>
    702. 

  702. <P>Affects Flags: none <PRE>MODE           SYNTAX       HEX LEN TIM
    703. 

  703. Zero Page     STX $44       $86  2   3
    704. 

  704. Zero Page,Y   STX $44,Y     $96  2   4
    705. 

  705. Absolute      STX $4400     $8E  3   4
    706. 

  706. </PRE>
    707. 

  707. <P>
    708. 

  708. <P>
    709. 

  709. <P><A name=STY>&nbsp;</A>
    710. 

  710. <H2>STY (STore Y register)</H2>
    711. 

  711. <P>Affects Flags: none <PRE>MODE           SYNTAX       HEX LEN TIM
    712. 

  712. Zero Page     STY $44       $84  2   3
    713. 

  713. Zero Page,X   STY $44,X     $94  2   4
    714. 

  714. Absolute      STY $4400     $8C  3   4
    715. 

  715. </PRE>
    716. 

  716. <P>
    717. 

  717. <P><FONT SIZE="-1">Last Updated May 5, 2017.</FONT>
    718. 

  718. </body></html>
    719. 

  719. 

  720.