i386-opcode.h 30 KB

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  1. /* i386-opcode.h -- Intel 80386 opcode table
  2. Copyright (C) 1989, Free Software Foundation.
  3. This file is part of GAS, the GNU Assembler.
  4. GAS is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 1, or (at your option)
  7. any later version.
  8. GAS is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with GAS; see the file COPYING. If not, write to
  14. the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
  15. template i386_optab[] = {
  16. #define _ None
  17. /* move instructions */
  18. { "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 },
  19. { "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 },
  20. { "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 },
  21. { "mov", 2, 0xc6, _, W|Modrm, Imm, Reg|Mem, 0 },
  22. { "mov", 2, 0x8c, _, D|Modrm, SReg3|SReg2, Reg16|Mem16, 0 },
  23. /* move to/from control debug registers */
  24. { "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0},
  25. { "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0},
  26. { "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0},
  27. /* move with sign extend */
  28. /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
  29. conflict with the "movs" string move instruction. Thus,
  30. {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
  31. is not kosher; we must seperate the two instructions. */
  32. {"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg32, 0},
  33. {"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16, 0},
  34. {"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
  35. /* move with zero extend */
  36. {"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
  37. {"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
  38. /* push instructions */
  39. {"push", 1, 0x50, _, ShortForm, WordReg,0,0 },
  40. {"push", 1, 0xff, 0x6, Modrm, WordReg|WordMem, 0, 0 },
  41. {"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0},
  42. {"push", 1, 0x68, _, NoModrm, Imm32, 0, 0},
  43. {"push", 1, 0x06, _, Seg2ShortForm, SReg2,0,0 },
  44. {"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 },
  45. /* push all */
  46. {"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 },
  47. /* pop instructions */
  48. {"pop", 1, 0x58, _, ShortForm, WordReg,0,0 },
  49. {"pop", 1, 0x8f, 0x0, Modrm, WordReg|WordMem, 0, 0 },
  50. #define POP_SEG_SHORT 0x7
  51. {"pop", 1, 0x07, _, Seg2ShortForm, SReg2,0,0 },
  52. {"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 },
  53. /* pop all */
  54. {"popa", 0, 0x61, _, NoModrm, 0, 0, 0 },
  55. /* xchg exchange instructions
  56. xchg commutes: we allow both operand orders */
  57. {"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 },
  58. {"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 },
  59. {"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 },
  60. {"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 },
  61. /* in/out from ports */
  62. {"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 },
  63. {"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 },
  64. {"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 },
  65. {"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 },
  66. /* load effective address */
  67. {"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 },
  68. /* load segment registers from memory */
  69. {"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0},
  70. {"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0},
  71. {"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0},
  72. {"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0},
  73. {"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0},
  74. /* flags register instructions */
  75. {"clc", 0, 0xf8, _, NoModrm, 0, 0, 0},
  76. {"cld", 0, 0xfc, _, NoModrm, 0, 0, 0},
  77. {"cli", 0, 0xfa, _, NoModrm, 0, 0, 0},
  78. {"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0},
  79. {"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0},
  80. {"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0},
  81. {"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0},
  82. {"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0},
  83. {"popf", 0, 0x9d, _, NoModrm, 0, 0, 0},
  84. {"stc", 0, 0xf9, _, NoModrm, 0, 0, 0},
  85. {"std", 0, 0xfd, _, NoModrm, 0, 0, 0},
  86. {"sti", 0, 0xfb, _, NoModrm, 0, 0, 0},
  87. {"add", 2, 0x0, _, DW|Modrm, Reg, Reg|Mem, 0},
  88. {"add", 2, 0x83, 0, Modrm, Imm8S, WordReg|WordMem, 0},
  89. {"add", 2, 0x4, _, W|NoModrm, Imm, Acc, 0},
  90. {"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0},
  91. {"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0},
  92. {"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0},
  93. {"sub", 2, 0x28, _, DW|Modrm, Reg, Reg|Mem, 0},
  94. {"sub", 2, 0x83, 5, Modrm, Imm8S, WordReg|WordMem, 0},
  95. {"sub", 2, 0x2c, _, W|NoModrm, Imm, Acc, 0},
  96. {"sub", 2, 0x80, 5, W|Modrm, Imm, Reg|Mem, 0},
  97. {"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0},
  98. {"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0},
  99. {"sbb", 2, 0x18, _, DW|Modrm, Reg, Reg|Mem, 0},
  100. {"sbb", 2, 0x83, 3, Modrm, Imm8S, WordReg|WordMem, 0},
  101. {"sbb", 2, 0x1c, _, W|NoModrm, Imm, Acc, 0},
  102. {"sbb", 2, 0x80, 3, W|Modrm, Imm, Reg|Mem, 0},
  103. {"cmp", 2, 0x38, _, DW|Modrm, Reg, Reg|Mem, 0},
  104. {"cmp", 2, 0x83, 7, Modrm, Imm8S, WordReg|WordMem, 0},
  105. {"cmp", 2, 0x3c, _, W|NoModrm, Imm, Acc, 0},
  106. {"cmp", 2, 0x80, 7, W|Modrm, Imm, Reg|Mem, 0},
  107. {"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0},
  108. {"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0},
  109. {"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0},
  110. {"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0},
  111. {"and", 2, 0x20, _, DW|Modrm, Reg, Reg|Mem, 0},
  112. {"and", 2, 0x83, 4, Modrm, Imm8S, WordReg|WordMem, 0},
  113. {"and", 2, 0x24, _, W|NoModrm, Imm, Acc, 0},
  114. {"and", 2, 0x80, 4, W|Modrm, Imm, Reg|Mem, 0},
  115. {"or", 2, 0x08, _, DW|Modrm, Reg, Reg|Mem, 0},
  116. {"or", 2, 0x83, 1, Modrm, Imm8S, WordReg|WordMem, 0},
  117. {"or", 2, 0x0c, _, W|NoModrm, Imm, Acc, 0},
  118. {"or", 2, 0x80, 1, W|Modrm, Imm, Reg|Mem, 0},
  119. {"xor", 2, 0x30, _, DW|Modrm, Reg, Reg|Mem, 0},
  120. {"xor", 2, 0x83, 6, Modrm, Imm8S, WordReg|WordMem, 0},
  121. {"xor", 2, 0x34, _, W|NoModrm, Imm, Acc, 0},
  122. {"xor", 2, 0x80, 6, W|Modrm, Imm, Reg|Mem, 0},
  123. {"adc", 2, 0x10, _, DW|Modrm, Reg, Reg|Mem, 0},
  124. {"adc", 2, 0x83, 2, Modrm, Imm8S, WordReg|WordMem, 0},
  125. {"adc", 2, 0x14, _, W|NoModrm, Imm, Acc, 0},
  126. {"adc", 2, 0x80, 2, W|Modrm, Imm, Reg|Mem, 0},
  127. {"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0},
  128. {"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0},
  129. {"aaa", 0, 0x37, _, NoModrm, 0, 0, 0},
  130. {"aas", 0, 0x3f, _, NoModrm, 0, 0, 0},
  131. {"daa", 0, 0x27, _, NoModrm, 0, 0, 0},
  132. {"das", 0, 0x2f, _, NoModrm, 0, 0, 0},
  133. {"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0},
  134. {"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0},
  135. /* conversion insns */
  136. /* conversion: intel naming */
  137. {"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0},
  138. {"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0},
  139. {"cwde", 0, 0x98, _, NoModrm, 0, 0, 0},
  140. {"cdq", 0, 0x99, _, NoModrm, 0, 0, 0},
  141. /* att naming */
  142. {"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0},
  143. {"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0},
  144. {"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0},
  145. {"cltd", 0, 0x99, _, NoModrm, 0, 0, 0},
  146. /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
  147. expanding 64-bit multiplies, and *cannot* be selected to accomplish
  148. 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
  149. These multiplies can only be selected with single opearnd forms. */
  150. {"mul", 1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0},
  151. {"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0},
  152. /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
  153. These instructions are exceptions: 'imul $2, %eax, %ecx' would put
  154. '%eax' in the reg field and '%ecx' in the regmem field if we did not
  155. switch them. */
  156. {"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
  157. {"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg},
  158. {"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg},
  159. /*
  160. imul with 2 operands mimicks imul with 3 by puting register both
  161. in i.rm.reg & i.rm.regmem fields
  162. */
  163. {"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0},
  164. {"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0},
  165. {"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0},
  166. {"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0},
  167. {"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0},
  168. {"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0},
  169. {"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0},
  170. {"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0},
  171. {"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0},
  172. {"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0},
  173. {"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0},
  174. {"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0},
  175. {"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0},
  176. {"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0},
  177. {"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0},
  178. {"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0},
  179. {"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0},
  180. {"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0},
  181. {"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0},
  182. {"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0},
  183. {"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0},
  184. {"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0},
  185. {"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
  186. {"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
  187. {"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
  188. {"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
  189. {"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
  190. {"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
  191. {"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
  192. {"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
  193. {"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem},
  194. {"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
  195. {"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0},
  196. {"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0},
  197. {"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0},
  198. {"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0},
  199. {"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem},
  200. {"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
  201. {"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0},
  202. {"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0},
  203. {"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0},
  204. {"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0},
  205. /* control transfer instructions */
  206. #define CALL_PC_RELATIVE 0xe8
  207. {"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0},
  208. {"call", 1, 0xff, 2, Modrm, Reg|Mem|JumpAbsolute, 0, 0},
  209. #define CALL_FAR_IMMEDIATE 0x9a
  210. {"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Abs32, 0},
  211. {"lcall", 1, 0xff, 3, Modrm, Mem, 0, 0},
  212. #define JUMP_PC_RELATIVE 0xeb
  213. {"jmp", 1, 0xeb, _, Jump, Disp, 0, 0},
  214. {"jmp", 1, 0xff, 4, Modrm, Reg32|Mem|JumpAbsolute, 0, 0},
  215. #define JUMP_FAR_IMMEDIATE 0xea
  216. {"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0},
  217. {"ljmp", 1, 0xff, 4, Modrm, Mem, 0, 0},
  218. {"ret", 0, 0xc3, _, NoModrm, 0, 0, 0},
  219. {"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0},
  220. {"lret", 0, 0xcb, _, NoModrm, 0, 0, 0},
  221. {"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0},
  222. {"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0},
  223. {"leave", 0, 0xc9, _, NoModrm, 0, 0, 0},
  224. /* conditional jumps */
  225. {"jo", 1, 0x70, _, Jump, Disp, 0, 0},
  226. {"jno", 1, 0x71, _, Jump, Disp, 0, 0},
  227. {"jb", 1, 0x72, _, Jump, Disp, 0, 0},
  228. {"jnae", 1, 0x72, _, Jump, Disp, 0, 0},
  229. {"jnb", 1, 0x73, _, Jump, Disp, 0, 0},
  230. {"jae", 1, 0x73, _, Jump, Disp, 0, 0},
  231. {"je", 1, 0x74, _, Jump, Disp, 0, 0},
  232. {"jz", 1, 0x74, _, Jump, Disp, 0, 0},
  233. {"jne", 1, 0x75, _, Jump, Disp, 0, 0},
  234. {"jnz", 1, 0x75, _, Jump, Disp, 0, 0},
  235. {"jbe", 1, 0x76, _, Jump, Disp, 0, 0},
  236. {"jna", 1, 0x76, _, Jump, Disp, 0, 0},
  237. {"jnbe", 1, 0x77, _, Jump, Disp, 0, 0},
  238. {"ja", 1, 0x77, _, Jump, Disp, 0, 0},
  239. {"js", 1, 0x78, _, Jump, Disp, 0, 0},
  240. {"jns", 1, 0x79, _, Jump, Disp, 0, 0},
  241. {"jp", 1, 0x7a, _, Jump, Disp, 0, 0},
  242. {"jpe", 1, 0x7a, _, Jump, Disp, 0, 0},
  243. {"jnp", 1, 0x7b, _, Jump, Disp, 0, 0},
  244. {"jpo", 1, 0x7b, _, Jump, Disp, 0, 0},
  245. {"jl", 1, 0x7c, _, Jump, Disp, 0, 0},
  246. {"jnge", 1, 0x7c, _, Jump, Disp, 0, 0},
  247. {"jnl", 1, 0x7d, _, Jump, Disp, 0, 0},
  248. {"jge", 1, 0x7d, _, Jump, Disp, 0, 0},
  249. {"jle", 1, 0x7e, _, Jump, Disp, 0, 0},
  250. {"jng", 1, 0x7e, _, Jump, Disp, 0, 0},
  251. {"jnle", 1, 0x7f, _, Jump, Disp, 0, 0},
  252. {"jg", 1, 0x7f, _, Jump, Disp, 0, 0},
  253. /* these turn into pseudo operations when disp is larger than 8 bits */
  254. #define IS_JUMP_ON_CX_ZERO(o) \
  255. (o == 0x67e3)
  256. #define IS_JUMP_ON_ECX_ZERO(o) \
  257. (o == 0xe3)
  258. {"jcxz", 1, 0x67e3, _, JumpByte, Disp, 0, 0},
  259. {"jecxz", 1, 0xe3, _, JumpByte, Disp, 0, 0},
  260. #define IS_LOOP_ECX_TIMES(o) \
  261. (o == 0xe2 || o == 0xe1 || o == 0xe0)
  262. {"loop", 1, 0xe2, _, JumpByte, Disp, 0, 0},
  263. {"loopz", 1, 0xe1, _, JumpByte, Disp, 0, 0},
  264. {"loope", 1, 0xe1, _, JumpByte, Disp, 0, 0},
  265. {"loopnz", 1, 0xe0, _, JumpByte, Disp, 0, 0},
  266. {"loopne", 1, 0xe0, _, JumpByte, Disp, 0, 0},
  267. /* set byte on flag instructions */
  268. {"seto", 1, 0x0f90, 0, Modrm, Reg8|Mem, 0, 0},
  269. {"setno", 1, 0x0f91, 0, Modrm, Reg8|Mem, 0, 0},
  270. {"setb", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
  271. {"setnae", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
  272. {"setnb", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
  273. {"setae", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
  274. {"sete", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
  275. {"setz", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
  276. {"setne", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
  277. {"setnz", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
  278. {"setbe", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
  279. {"setna", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
  280. {"setnbe", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
  281. {"seta", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
  282. {"sets", 1, 0x0f98, 0, Modrm, Reg8|Mem, 0, 0},
  283. {"setns", 1, 0x0f99, 0, Modrm, Reg8|Mem, 0, 0},
  284. {"setp", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
  285. {"setpe", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
  286. {"setnp", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
  287. {"setpo", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
  288. {"setl", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
  289. {"setnge", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
  290. {"setnl", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
  291. {"setge", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
  292. {"setle", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
  293. {"setng", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
  294. {"setnle", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
  295. {"setg", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
  296. #define IS_STRING_INSTRUCTION(o) \
  297. ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
  298. (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
  299. (o) == 0xd7)
  300. /* string manipulation */
  301. {"cmps", 0, 0xa6, _, W|NoModrm, 0, 0, 0},
  302. {"ins", 0, 0x6c, _, W|NoModrm, 0, 0, 0},
  303. {"outs", 0, 0x6e, _, W|NoModrm, 0, 0, 0},
  304. {"lods", 0, 0xac, _, W|NoModrm, 0, 0, 0},
  305. {"movs", 0, 0xa4, _, W|NoModrm, 0, 0, 0},
  306. {"scas", 0, 0xae, _, W|NoModrm, 0, 0, 0},
  307. {"stos", 0, 0xaa, _, W|NoModrm, 0, 0, 0},
  308. {"xlat", 0, 0xd7, _, NoModrm, 0, 0, 0},
  309. /* bit manipulation */
  310. {"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
  311. {"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
  312. {"bt", 2, 0x0fa3, _, Modrm, Reg, Reg|Mem, 0},
  313. {"bt", 2, 0x0fba, 4, Modrm, Imm8, Reg|Mem, 0},
  314. {"btc", 2, 0x0fbb, _, Modrm, Reg, Reg|Mem, 0},
  315. {"btc", 2, 0x0fba, 7, Modrm, Imm8, Reg|Mem, 0},
  316. {"btr", 2, 0x0fb3, _, Modrm, Reg, Reg|Mem, 0},
  317. {"btr", 2, 0x0fba, 6, Modrm, Imm8, Reg|Mem, 0},
  318. {"bts", 2, 0x0fab, _, Modrm, Reg, Reg|Mem, 0},
  319. {"bts", 2, 0x0fba, 5, Modrm, Imm8, Reg|Mem, 0},
  320. /* interrupts & op. sys insns */
  321. /* See i386.c for conversion of 'int $3' into the special int 3 insn. */
  322. #define INT_OPCODE 0xcd
  323. #define INT3_OPCODE 0xcc
  324. {"int", 1, 0xcd, _, NoModrm, Imm8, 0, 0},
  325. {"int3", 0, 0xcc, _, NoModrm, 0, 0, 0},
  326. {"into", 0, 0xce, _, NoModrm, 0, 0, 0},
  327. {"iret", 0, 0xcf, _, NoModrm, 0, 0, 0},
  328. {"boundl", 2, 0x62, _, Modrm, Reg32, Mem, 0},
  329. {"boundw", 2, 0x6662, _, Modrm, Reg16, Mem, 0},
  330. {"hlt", 0, 0xf4, _, NoModrm, 0, 0, 0},
  331. {"wait", 0, 0x9b, _, NoModrm, 0, 0, 0},
  332. /* nop is actually 'xchgl %eax, %eax' */
  333. {"nop", 0, 0x90, _, NoModrm, 0, 0, 0},
  334. /* protection control */
  335. {"arpl", 2, 0x63, _, Modrm, Reg16, Reg16|Mem, 0},
  336. {"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
  337. {"lgdt", 1, 0x0f01, 2, Modrm, Mem, 0, 0},
  338. {"lidt", 1, 0x0f01, 3, Modrm, Mem, 0, 0},
  339. {"lldt", 1, 0x0f00, 2, Modrm, WordReg|Mem, 0, 0},
  340. {"lmsw", 1, 0x0f01, 6, Modrm, WordReg|Mem, 0, 0},
  341. {"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
  342. {"ltr", 1, 0x0f00, 3, Modrm, WordReg|Mem, 0, 0},
  343. {"sgdt", 1, 0x0f01, 0, Modrm, Mem, 0, 0},
  344. {"sidt", 1, 0x0f01, 1, Modrm, Mem, 0, 0},
  345. {"sldt", 1, 0x0f00, 0, Modrm, WordReg|Mem, 0, 0},
  346. {"smsw", 1, 0x0f01, 4, Modrm, WordReg|Mem, 0, 0},
  347. {"str", 1, 0x0f00, 1, Modrm, Reg16|Mem, 0, 0},
  348. {"verr", 1, 0x0f00, 4, Modrm, WordReg|Mem, 0, 0},
  349. {"verw", 1, 0x0f00, 5, Modrm, WordReg|Mem, 0, 0},
  350. /* floating point instructions */
  351. /* load */
  352. {"fld", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
  353. {"flds", 1, 0xd9, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem float */
  354. {"fildl", 1, 0xdb, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem word */
  355. {"fldl", 1, 0xdd, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem double */
  356. {"fldl", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
  357. {"filds", 1, 0xdf, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem dword */
  358. {"fildq", 1, 0xdf, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem qword */
  359. {"fldt", 1, 0xdb, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem efloat */
  360. {"fbld", 1, 0xdf, 4, Modrm, Mem, 0, 0}, /* %st0 <-- mem bcd */
  361. /* store (no pop) */
  362. {"fst", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
  363. {"fsts", 1, 0xd9, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem float */
  364. {"fistl", 1, 0xdb, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */
  365. {"fstl", 1, 0xdd, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem double */
  366. {"fstl", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
  367. {"fists", 1, 0xdf, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem word */
  368. /* store (with pop) */
  369. {"fstp", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
  370. {"fstps", 1, 0xd9, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem float */
  371. {"fistpl", 1, 0xdb, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem word */
  372. {"fstpl", 1, 0xdd, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem double */
  373. {"fstpl", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
  374. {"fistps", 1, 0xdf, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */
  375. {"fistpq", 1, 0xdf, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem qword */
  376. {"fstpt", 1, 0xdb, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem efloat */
  377. {"fbstp", 1, 0xdf, 6, Modrm, Mem, 0, 0}, /* %st0 --> mem bcd */
  378. /* exchange %st<n> with %st0 */
  379. {"fxch", 1, 0xd9c8, _, ShortForm, FloatReg, 0, 0},
  380. /* comparison (without pop) */
  381. {"fcom", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
  382. {"fcoms", 1, 0xd8, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem float */
  383. {"ficoml", 1, 0xda, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem word */
  384. {"fcoml", 1, 0xdc, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem double */
  385. {"fcoml", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
  386. {"ficoms", 1, 0xde, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
  387. /* comparison (with pop) */
  388. {"fcomp", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
  389. {"fcomps", 1, 0xd8, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem float */
  390. {"ficompl", 1, 0xda, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem word */
  391. {"fcompl", 1, 0xdc, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem double */
  392. {"fcompl", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
  393. {"ficomps", 1, 0xde, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
  394. {"fcompp", 0, 0xded9, _, NoModrm, 0, 0, 0}, /* compare %st0, %st1 & pop twice */
  395. /* unordered comparison (with pop) */
  396. {"fucom", 1, 0xdde0, _, ShortForm, FloatReg, 0, 0},
  397. {"fucomp", 1, 0xdde8, _, ShortForm, FloatReg, 0, 0},
  398. {"fucompp", 0, 0xdae9, _, NoModrm, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */
  399. {"ftst", 0, 0xd9e4, _, NoModrm, 0, 0, 0}, /* test %st0 */
  400. {"fxam", 0, 0xd9e5, _, NoModrm, 0, 0, 0}, /* examine %st0 */
  401. /* load constants into %st0 */
  402. {"fld1", 0, 0xd9e8, _, NoModrm, 0, 0, 0}, /* %st0 <-- 1.0 */
  403. {"fldl2t", 0, 0xd9e9, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(10) */
  404. {"fldl2e", 0, 0xd9ea, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(e) */
  405. {"fldpi", 0, 0xd9eb, _, NoModrm, 0, 0, 0}, /* %st0 <-- pi */
  406. {"fldlg2", 0, 0xd9ec, _, NoModrm, 0, 0, 0}, /* %st0 <-- log10(2) */
  407. {"fldln2", 0, 0xd9ed, _, NoModrm, 0, 0, 0}, /* %st0 <-- ln(2) */
  408. {"fldz", 0, 0xd9ee, _, NoModrm, 0, 0, 0}, /* %st0 <-- 0.0 */
  409. /* arithmetic */
  410. /* add */
  411. {"fadd", 1, 0xd8c0, _, ShortForm, FloatReg, 0, 0},
  412. {"fadd", 2, 0xd8c0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
  413. {"fadd", 0, 0xdcc1, _, NoModrm, 0, 0, 0}, /* alias for fadd %st, %st(1) */
  414. {"faddp", 1, 0xdac0, _, ShortForm, FloatReg, 0, 0},
  415. {"faddp", 2, 0xdac0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
  416. {"faddp", 0, 0xdec1, _, NoModrm, 0, 0, 0}, /* alias for faddp %st, %st(1) */
  417. {"fadds", 1, 0xd8, 0, Modrm, Mem, 0, 0},
  418. {"fiaddl", 1, 0xda, 0, Modrm, Mem, 0, 0},
  419. {"faddl", 1, 0xdc, 0, Modrm, Mem, 0, 0},
  420. {"fiadds", 1, 0xde, 0, Modrm, Mem, 0, 0},
  421. /* sub */
  422. /* Note: intel has decided that certain of these operations are reversed
  423. in assembler syntax. */
  424. {"fsub", 1, 0xd8e0, _, ShortForm, FloatReg, 0, 0},
  425. {"fsub", 2, 0xd8e0, _, ShortForm, FloatReg, FloatAcc, 0},
  426. #ifdef NON_BROKEN_OPCODES
  427. {"fsub", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
  428. #else
  429. {"fsub", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
  430. #endif
  431. {"fsub", 0, 0xdce1, _, NoModrm, 0, 0, 0},
  432. {"fsubp", 1, 0xdae0, _, ShortForm, FloatReg, 0, 0},
  433. {"fsubp", 2, 0xdae0, _, ShortForm, FloatReg, FloatAcc, 0},
  434. #ifdef NON_BROKEN_OPCODES
  435. {"fsubp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
  436. #else
  437. {"fsubp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
  438. #endif
  439. {"fsubp", 0, 0xdee1, _, NoModrm, 0, 0, 0},
  440. {"fsubs", 1, 0xd8, 4, Modrm, Mem, 0, 0},
  441. {"fisubl", 1, 0xda, 4, Modrm, Mem, 0, 0},
  442. {"fsubl", 1, 0xdc, 4, Modrm, Mem, 0, 0},
  443. {"fisubs", 1, 0xde, 4, Modrm, Mem, 0, 0},
  444. /* sub reverse */
  445. {"fsubr", 1, 0xd8e8, _, ShortForm, FloatReg, 0, 0},
  446. {"fsubr", 2, 0xd8e8, _, ShortForm, FloatReg, FloatAcc, 0},
  447. #ifdef NON_BROKEN_OPCODES
  448. {"fsubr", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
  449. #else
  450. {"fsubr", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
  451. #endif
  452. {"fsubr", 0, 0xdce9, _, NoModrm, 0, 0, 0},
  453. {"fsubrp", 1, 0xdae8, _, ShortForm, FloatReg, 0, 0},
  454. {"fsubrp", 2, 0xdae8, _, ShortForm, FloatReg, FloatAcc, 0},
  455. #ifdef NON_BROKEN_OPCODES
  456. {"fsubrp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
  457. #else
  458. {"fsubrp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
  459. #endif
  460. {"fsubrp", 0, 0xdee9, _, NoModrm, 0, 0, 0},
  461. {"fsubrs", 1, 0xd8, 5, Modrm, Mem, 0, 0},
  462. {"fisubrl", 1, 0xda, 5, Modrm, Mem, 0, 0},
  463. {"fsubrl", 1, 0xdc, 5, Modrm, Mem, 0, 0},
  464. {"fisubrs", 1, 0xde, 5, Modrm, Mem, 0, 0},
  465. /* mul */
  466. {"fmul", 1, 0xd8c8, _, ShortForm, FloatReg, 0, 0},
  467. {"fmul", 2, 0xd8c8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
  468. {"fmul", 0, 0xdcc9, _, NoModrm, 0, 0, 0},
  469. {"fmulp", 1, 0xdac8, _, ShortForm, FloatReg, 0, 0},
  470. {"fmulp", 2, 0xdac8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
  471. {"fmulp", 0, 0xdec9, _, NoModrm, 0, 0, 0},
  472. {"fmuls", 1, 0xd8, 1, Modrm, Mem, 0, 0},
  473. {"fimull", 1, 0xda, 1, Modrm, Mem, 0, 0},
  474. {"fmull", 1, 0xdc, 1, Modrm, Mem, 0, 0},
  475. {"fimuls", 1, 0xde, 1, Modrm, Mem, 0, 0},
  476. /* div */
  477. /* Note: intel has decided that certain of these operations are reversed
  478. in assembler syntax. */
  479. {"fdiv", 1, 0xd8f0, _, ShortForm, FloatReg, 0, 0},
  480. {"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0},
  481. #ifdef NON_BROKEN_OPCODES
  482. {"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
  483. #else
  484. {"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
  485. #endif
  486. {"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0},
  487. {"fdivp", 1, 0xdaf0, _, ShortForm, FloatReg, 0, 0},
  488. {"fdivp", 2, 0xdaf0, _, ShortForm, FloatReg, FloatAcc, 0},
  489. #ifdef NON_BROKEN_OPCODES
  490. {"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
  491. #else
  492. {"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
  493. #endif
  494. {"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0},
  495. {"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0},
  496. {"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0},
  497. {"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0},
  498. {"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0},
  499. /* div reverse */
  500. {"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0},
  501. {"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0},
  502. #ifdef NON_BROKEN_OPCODES
  503. {"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
  504. #else
  505. {"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
  506. #endif
  507. {"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0},
  508. {"fdivrp", 1, 0xdaf8, _, ShortForm, FloatReg, 0, 0},
  509. {"fdivrp", 2, 0xdaf8, _, ShortForm, FloatReg, FloatAcc, 0},
  510. #ifdef NON_BROKEN_OPCODES
  511. {"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
  512. #else
  513. {"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
  514. #endif
  515. {"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0},
  516. {"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0},
  517. {"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0},
  518. {"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0},
  519. {"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0},
  520. {"f2xm1", 0, 0xd9f0, _, NoModrm, 0, 0, 0},
  521. {"fyl2x", 0, 0xd9f1, _, NoModrm, 0, 0, 0},
  522. {"fptan", 0, 0xd9f2, _, NoModrm, 0, 0, 0},
  523. {"fpatan", 0, 0xd9f3, _, NoModrm, 0, 0, 0},
  524. {"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0},
  525. {"fprem1", 0, 0xd9f5, _, NoModrm, 0, 0, 0},
  526. {"fdecstp", 0, 0xd9f6, _, NoModrm, 0, 0, 0},
  527. {"fincstp", 0, 0xd9f7, _, NoModrm, 0, 0, 0},
  528. {"fprem", 0, 0xd9f8, _, NoModrm, 0, 0, 0},
  529. {"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0},
  530. {"fsqrt", 0, 0xd9fa, _, NoModrm, 0, 0, 0},
  531. {"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0},
  532. {"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0},
  533. {"fscale", 0, 0xd9fd, _, NoModrm, 0, 0, 0},
  534. {"fsin", 0, 0xd9fe, _, NoModrm, 0, 0, 0},
  535. {"fcos", 0, 0xd9ff, _, NoModrm, 0, 0, 0},
  536. {"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0},
  537. {"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0},
  538. /* processor control */
  539. {"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
  540. {"finit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
  541. {"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0},
  542. {"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
  543. {"fstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
  544. {"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
  545. {"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
  546. {"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
  547. {"fstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
  548. {"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
  549. {"fstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
  550. {"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
  551. {"fclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
  552. /*
  553. We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
  554. instructions; i'm not sure how to add them or how they are different.
  555. My 386/387 book offers no details about this.
  556. */
  557. {"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
  558. {"fstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
  559. {"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0},
  560. {"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
  561. {"fsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
  562. {"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0},
  563. {"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0},
  564. {"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0},
  565. {"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0},
  566. /*
  567. opcode prefixes; we allow them as seperate insns too
  568. (see prefix table below)
  569. */
  570. {"aword", 0, 0x67, _, NoModrm, 0, 0, 0},
  571. {"word", 0, 0x66, _, NoModrm, 0, 0, 0},
  572. {"lock", 0, 0xf0, _, NoModrm, 0, 0, 0},
  573. {"cs", 0, 0x2e, _, NoModrm, 0, 0, 0},
  574. {"ds", 0, 0x3e, _, NoModrm, 0, 0, 0},
  575. {"es", 0, 0x26, _, NoModrm, 0, 0, 0},
  576. {"fs", 0, 0x64, _, NoModrm, 0, 0, 0},
  577. {"gs", 0, 0x65, _, NoModrm, 0, 0, 0},
  578. {"ss", 0, 0x36, _, NoModrm, 0, 0, 0},
  579. {"rep", 0, 0xf3, _, NoModrm, 0, 0, 0},
  580. {"repe", 0, 0xf3, _, NoModrm, 0, 0, 0},
  581. { "repne", 0, 0xf2, _, NoModrm, 0, 0, 0},
  582. {"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */
  583. };
  584. #undef _
  585. template *i386_optab_end
  586. = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
  587. /* 386 register table */
  588. reg_entry i386_regtab[] = {
  589. /* 8 bit regs */
  590. {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
  591. {"bl", Reg8, 3},
  592. {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
  593. /* 16 bit regs */
  594. {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
  595. {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
  596. /* 32 bit regs */
  597. {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
  598. {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
  599. /* segment registers */
  600. {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
  601. {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
  602. /* control registers */
  603. {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
  604. /* debug registers */
  605. {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
  606. {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
  607. /* test registers */
  608. {"tr6", Test, 6}, {"tr7", Test, 7},
  609. /* float registers */
  610. {"st(0)", FloatReg|FloatAcc, 0},
  611. {"st", FloatReg|FloatAcc, 0},
  612. {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
  613. {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
  614. {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
  615. };
  616. #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
  617. reg_entry *i386_regtab_end
  618. = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
  619. /* segment stuff */
  620. seg_entry cs = { "cs", 0x2e };
  621. seg_entry ds = { "ds", 0x3e };
  622. seg_entry ss = { "ss", 0x36 };
  623. seg_entry es = { "es", 0x26 };
  624. seg_entry fs = { "fs", 0x64 };
  625. seg_entry gs = { "gs", 0x65 };
  626. seg_entry null = { "", 0x0 };
  627. /*
  628. This table is used to store the default segment register implied by all
  629. possible memory addressing modes.
  630. It is indexed by the mode & modrm entries of the modrm byte as follows:
  631. index = (mode<<3) | modrm;
  632. */
  633. seg_entry *one_byte_segment_defaults[] = {
  634. /* mode 0 */
  635. &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
  636. /* mode 1 */
  637. &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
  638. /* mode 2 */
  639. &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
  640. /* mode 3 --- not a memory reference; never referenced */
  641. };
  642. seg_entry *two_byte_segment_defaults[] = {
  643. /* mode 0 */
  644. &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
  645. /* mode 1 */
  646. &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
  647. /* mode 2 */
  648. &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
  649. /* mode 3 --- not a memory reference; never referenced */
  650. };
  651. prefix_entry i386_prefixtab[] = {
  652. { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
  653. * (How is this useful?) */
  654. #define WORD_PREFIX_OPCODE 0x66
  655. { "data16", 0x66 }, /* operand size prefix */
  656. { "lock", 0xf0 }, /* bus lock prefix */
  657. { "wait", 0x9b }, /* wait for coprocessor */
  658. { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
  659. { "es", 0x26 }, { "fs", 0x64 },
  660. { "gs", 0x65 }, { "ss", 0x36 },
  661. /* REPE & REPNE used to detect rep/repne with a non-string instruction */
  662. #define REPNE 0xf2
  663. #define REPE 0xf3
  664. { "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */
  665. { "repne", 0xf2 }
  666. };
  667. prefix_entry *i386_prefixtab_end
  668. = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);