Ana Sayfa Keşfet Yardım
Giriş Yap
misspapaya
/
cpu32
şundan çatallanmış scuti/cpu32
İzle 1
Yıldızla 0
Çatalla 0
Dosyalar
Dal: rewrite-in-c
Dallar Biçim İmleri
cpu32
/
riscv
/
riscv_rtl
/
riscv_rtl.runs
/
synth_1
/
runme.log

runme.log 17 KB
Kalıcı Bağlantı Geçmiş Ham

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224 
  1. 

  2. *** Running vivado
    3. 

  3.     with args -log basys3top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source basys3top.tcl
    4. 

  4. 

  5. 

  6. ECHO is off.
    7. 

  7. ECHO is off.
    8. 

  8. 

  9. ****** Vivado v2023.1 (64-bit)
    10. 

  10.   **** SW Build 3865809 on Sun May  7 15:05:29 MDT 2023
    11. 

  11.   **** IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
    12. 

  12.   **** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
    13. 

  13.     ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    14. 

  14.     ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
    15. 

  15. 

  16. source basys3top.tcl -notrace
    17. 

  17. Command: read_checkpoint -auto_incremental -incremental C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/utils_1/imports/synth_1/basys3top.dcp
    18. 

  18. INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/utils_1/imports/synth_1/basys3top.dcp for incremental synthesis
    19. 

  19. INFO: [Vivado 12-7989] Please ensure there are no constraint changes
    20. 

  20. Command: synth_design -top basys3top -part xc7a35tcpg236-1
    21. 

  21. Starting synth_design
    22. 

  22. Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
    23. 

  23. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
    24. 

  24. INFO: [Device 21-403] Loading part xc7a35tcpg236-1
    25. 

  25. INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
    26. 

  26. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
    27. 

  27. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
    28. 

  28. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
    29. 

  29. INFO: [Synth 8-7075] Helper process launched with PID 3452
    30. 

  30. ---------------------------------------------------------------------------------
    31. 

  31. Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1253.184 ; gain = 411.832
    32. 

  32. ---------------------------------------------------------------------------------
    33. 

  33. INFO: [Synth 8-638] synthesizing module 'basys3top' [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/basys3top.vhd:40]
    34. 

  34. INFO: [Synth 8-3491] module 'seven_seg' declared at 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/seven_seg.vhd:34' bound to instance 'sseg' of component 'seven_seg' [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/basys3top.vhd:44]
    35. 

  35. INFO: [Synth 8-638] synthesizing module 'seven_seg' [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/seven_seg.vhd:41]
    36. 

  36. INFO: [Synth 8-256] done synthesizing module 'seven_seg' (0#1) [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/seven_seg.vhd:41]
    37. 

  37. INFO: [Synth 8-256] done synthesizing module 'basys3top' (0#1) [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/sources_1/new/basys3top.vhd:40]
    38. 

  38. ---------------------------------------------------------------------------------
    39. 

  39. Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1343.922 ; gain = 502.570
    40. 

  40. ---------------------------------------------------------------------------------
    41. 

  41. ---------------------------------------------------------------------------------
    42. 

  42. Start Handling Custom Attributes
    43. 

  43. ---------------------------------------------------------------------------------
    44. 

  44. ---------------------------------------------------------------------------------
    45. 

  45. Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1343.922 ; gain = 502.570
    46. 

  46. ---------------------------------------------------------------------------------
    47. 

  47. ---------------------------------------------------------------------------------
    48. 

  48. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1343.922 ; gain = 502.570
    49. 

  49. ---------------------------------------------------------------------------------
    50. 

  50. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1343.922 ; gain = 0.000
    51. 

  51. INFO: [Project 1-570] Preparing netlist for logic optimization
    52. 

  52. 

  53. Processing XDC Constraints
    54. 

  54. Initializing timing engine
    55. 

  55. Parsing XDC File [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]
    56. 

  56. Finished Parsing XDC File [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]
    57. 

  57. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.srcs/constrs_1/new/basys3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/basys3top_propImpl.xdc].
    58. 

  58. Resolution: To avoid this warning, move constraints listed in [.Xil/basys3top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
    59. 

  59. Completed Processing XDC Constraints
    60. 

  60. 

  61. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.855 ; gain = 0.000
    62. 

  62. INFO: [Project 1-111] Unisim Transformation Summary:
    63. 

  63. No Unisim elements were transformed.
    64. 

  64. 

  65. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1436.855 ; gain = 0.000
    66. 

  66. INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
    67. 

  67. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
    68. 

  68. ---------------------------------------------------------------------------------
    69. 

  69. Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
    70. 

  70. ---------------------------------------------------------------------------------
    71. 

  71. ---------------------------------------------------------------------------------
    72. 

  72. Start Loading Part and Timing Information
    73. 

  73. ---------------------------------------------------------------------------------
    74. 

  74. Loading part: xc7a35tcpg236-1
    75. 

  75. ---------------------------------------------------------------------------------
    76. 

  76. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
    77. 

  77. ---------------------------------------------------------------------------------
    78. 

  78. ---------------------------------------------------------------------------------
    79. 

  79. Start Applying 'set_property' XDC Constraints
    80. 

  80. ---------------------------------------------------------------------------------
    81. 

  81. ---------------------------------------------------------------------------------
    82. 

  82. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
    83. 

  83. ---------------------------------------------------------------------------------
    84. 

  84. ---------------------------------------------------------------------------------
    85. 

  85. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1436.855 ; gain = 595.504
    86. 

  86. ---------------------------------------------------------------------------------
    87. 

  87. ---------------------------------------------------------------------------------
    88. 

  88. Start RTL Component Statistics 
    89. 

  89. ---------------------------------------------------------------------------------
    90. 

  90. Detailed RTL Component Info : 
    91. 

  91. +---Muxes : 
    92. 

  92. 	   5 Input    4 Bit        Muxes := 2     
    93. 

  93. ---------------------------------------------------------------------------------
    94. 

  94. Finished RTL Component Statistics 
    95. 

  95. ---------------------------------------------------------------------------------
    96. 

  96. ---------------------------------------------------------------------------------
    97. 

  97. Start Part Resource Summary
    98. 

  98. ---------------------------------------------------------------------------------
    99. 

  99. Part Resources:
    100. 

  100. DSPs: 90 (col length:60)
    101. 

  101. BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
    102. 

  102. ---------------------------------------------------------------------------------
    103. 

  103. Finished Part Resource Summary
    104. 

  104. ---------------------------------------------------------------------------------
    105. 

  105. ---------------------------------------------------------------------------------
    106. 

  106. Start Cross Boundary and Area Optimization
    107. 

  107. ---------------------------------------------------------------------------------
    108. 

  108. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
    109. 

  109. ---------------------------------------------------------------------------------
    110. 

  110. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1436.855 ; gain = 595.504
    111. 

  111. ---------------------------------------------------------------------------------
    112. 

  112. ---------------------------------------------------------------------------------
    113. 

  113. Start Applying XDC Timing Constraints
    114. 

  114. ---------------------------------------------------------------------------------
    115. 

  115. ---------------------------------------------------------------------------------
    116. 

  116. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1436.855 ; gain = 595.504
    117. 

  117. ---------------------------------------------------------------------------------
    118. 

  118. ---------------------------------------------------------------------------------
    119. 

  119. Start Timing Optimization
    120. 

  120. ---------------------------------------------------------------------------------
    121. 

  121. ---------------------------------------------------------------------------------
    122. 

  122. Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1436.855 ; gain = 595.504
    123. 

  123. ---------------------------------------------------------------------------------
    124. 

  124. ---------------------------------------------------------------------------------
    125. 

  125. Start Technology Mapping
    126. 

  126. ---------------------------------------------------------------------------------
    127. 

  127. ---------------------------------------------------------------------------------
    128. 

  128. Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1436.855 ; gain = 595.504
    129. 

  129. ---------------------------------------------------------------------------------
    130. 

  130. ---------------------------------------------------------------------------------
    131. 

  131. Start IO Insertion
    132. 

  132. ---------------------------------------------------------------------------------
    133. 

  133. ---------------------------------------------------------------------------------
    134. 

  134. Start Flattening Before IO Insertion
    135. 

  135. ---------------------------------------------------------------------------------
    136. 

  136. ---------------------------------------------------------------------------------
    137. 

  137. Finished Flattening Before IO Insertion
    138. 

  138. ---------------------------------------------------------------------------------
    139. 

  139. ---------------------------------------------------------------------------------
    140. 

  140. Start Final Netlist Cleanup
    141. 

  141. ---------------------------------------------------------------------------------
    142. 

  142. ---------------------------------------------------------------------------------
    143. 

  143. Finished Final Netlist Cleanup
    144. 

  144. ---------------------------------------------------------------------------------
    145. 

  145. ---------------------------------------------------------------------------------
    146. 

  146. Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    147. 

  147. ---------------------------------------------------------------------------------
    148. 

  148. ---------------------------------------------------------------------------------
    149. 

  149. Start Renaming Generated Instances
    150. 

  150. ---------------------------------------------------------------------------------
    151. 

  151. ---------------------------------------------------------------------------------
    152. 

  152. Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    153. 

  153. ---------------------------------------------------------------------------------
    154. 

  154. ---------------------------------------------------------------------------------
    155. 

  155. Start Rebuilding User Hierarchy
    156. 

  156. ---------------------------------------------------------------------------------
    157. 

  157. ---------------------------------------------------------------------------------
    158. 

  158. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    159. 

  159. ---------------------------------------------------------------------------------
    160. 

  160. ---------------------------------------------------------------------------------
    161. 

  161. Start Renaming Generated Ports
    162. 

  162. ---------------------------------------------------------------------------------
    163. 

  163. ---------------------------------------------------------------------------------
    164. 

  164. Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    165. 

  165. ---------------------------------------------------------------------------------
    166. 

  166. ---------------------------------------------------------------------------------
    167. 

  167. Start Handling Custom Attributes
    168. 

  168. ---------------------------------------------------------------------------------
    169. 

  169. ---------------------------------------------------------------------------------
    170. 

  170. Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    171. 

  171. ---------------------------------------------------------------------------------
    172. 

  172. ---------------------------------------------------------------------------------
    173. 

  173. Start Renaming Generated Nets
    174. 

  174. ---------------------------------------------------------------------------------
    175. 

  175. ---------------------------------------------------------------------------------
    176. 

  176. Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    177. 

  177. ---------------------------------------------------------------------------------
    178. 

  178. ---------------------------------------------------------------------------------
    179. 

  179. Start Writing Synthesis Report
    180. 

  180. ---------------------------------------------------------------------------------
    181. 

  181. 

  182. Report BlackBoxes: 
    183. 

  183. +-+--------------+----------+
    184. 

  184. | |BlackBox name |Instances |
    185. 

  185. +-+--------------+----------+
    186. 

  186. +-+--------------+----------+
    187. 

  187. 

  188. Report Cell Usage: 
    189. 

  189. +------+-------+------+
    190. 

  190. |      |Cell   |Count |
    191. 

  191. +------+-------+------+
    192. 

  192. |1     |BUFG   |     1|
    193. 

  193. |2     |CARRY4 |     4|
    194. 

  194. |3     |LUT1   |     3|
    195. 

  195. |4     |LUT3   |     6|
    196. 

  196. |5     |FDRE   |    13|
    197. 

  197. |6     |IBUF   |     1|
    198. 

  198. |7     |OBUF   |    12|
    199. 

  199. +------+-------+------+
    200. 

  200. ---------------------------------------------------------------------------------
    201. 

  201. Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    202. 

  202. ---------------------------------------------------------------------------------
    203. 

  203. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
    204. 

  204. Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1436.855 ; gain = 502.570
    205. 

  205. Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1436.855 ; gain = 595.504
    206. 

  206. INFO: [Project 1-571] Translating synthesized netlist
    207. 

  207. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.855 ; gain = 0.000
    208. 

  208. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
    209. 

  209. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
    210. 

  210. INFO: [Project 1-570] Preparing netlist for logic optimization
    211. 

  211. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
    212. 

  212. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1436.855 ; gain = 0.000
    213. 

  213. INFO: [Project 1-111] Unisim Transformation Summary:
    214. 

  214. No Unisim elements were transformed.
    215. 

  215. 

  216. Synth Design complete | Checksum: 4dde06ef
    217. 

  217. INFO: [Common 17-83] Releasing license: Synthesis
    218. 

  218. 26 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
    219. 

  219. synth_design completed successfully
    220. 

  220. synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.855 ; gain = 974.078
    221. 

  221. INFO: [Common 17-1381] The checkpoint 'C:/Users/misspapaya/projects/cpu32/riscv/riscv_rtl/riscv_rtl.runs/synth_1/basys3top.dcp' has been generated.
    222. 

  222. INFO: [runtcl-4] Executing : report_utilization -file basys3top_utilization_synth.rpt -pb basys3top_utilization_synth.pb
    223. 

  223. INFO: [Common 17-206] Exiting Vivado at Thu Jun  8 10:53:38 2023...
    224. 

  224.