Cronologia Commit

Autore SHA1 Messaggio Data
  mr1337357 65338a7170 forgot a file 1 anno fa
  mr1337357 a0d7e9a6ae more instructions i think 1 anno fa
  Your Name f6a2e3059a rebuild example instruction program and add disassembly of assembly programs (lol) 1 anno fa
  mr1337357 ecdc4f6521 testing more instructions and fixing bug in test program 1 anno fa
  mr1337357 439684972b improve pc handling 1 anno fa
  Your Name f140f16153 more examples 1 anno fa
  Your Name 758f93def8 partially fixed assembly stuff 1 anno fa
  Your Name 74f45f765d update examples 1 anno fa
  mr1337357 12f015c012 Merge remote-tracking branch 'origin/master' 1 anno fa
  mr1337357 21465abab6 add assembly programs 1 anno fa
  misspapaya f065b35825 started riscv32c but i think im going to stop for now and focus on rtl 1 anno fa
  mr1337357 e67f799aff asdf 1 anno fa
  misspapaya e247e660de add loading global variables and fix a mem load bug 1 anno fa
  misspapaya ec4b1ad214 can simulate one simple program 1 anno fa
  Your Name eb0532bac9 update examples 1 anno fa
  mr1337357 344c2a3f07 starting the simulation and adding int32 to help keep math in line 1 anno fa
  mr1337357 c3c1f69ba2 re-order functions to match docs 1 anno fa
  mr1337357 d191e0271d broke out opcodes to separate file so i can share work between disassembler and simulator 1 anno fa
  misspapaya d126aa6d6a simplified opcode matching 1 anno fa
  misspapaya 191b0b2414 riscv work 1 anno fa
  mr1337357 271b60f63a partial disassembler 1 anno fa
  Your Name fe6c298eb0 build script 1 anno fa
  Your Name 6447712c85 example hello world 1 anno fa
  mr1337357 4122100352 start elf parser 1 anno fa
  mr1337357 abfa0b0a30 start rtl project, start sim 1 anno fa
  mr1337357 0bd44d528c asdf 1 anno fa