awlsim/tests/tc100_instructions/insn_SA.awl

ORGANIZATION_BLOCK OB 1
BEGIN

	// Start timer and let it expire
	__STWRST
	L		0
	SA		T 10
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	SET
	L		W#16#0010
	SA		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT==	__ACCU 1,	0
	__SLEEP		101
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT==	__ACCU 1,	0


	// Start timer and reset VKE
	__STWRST
	L		0
	SA		T 10
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	SET
	L		W#16#0010
	SA		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT==	__ACCU 1,	0
	__SLEEP		101
	L		T 10
	__ASSERT==	__ACCU 1,	0
	CLR
	L		W#16#0010
	SA		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT>=	__ACCU 1,	5
	__SLEEP		101
	U		T 10
	__ASSERT==	__STW VKE,	0
	L		T 10
	__ASSERT==	__ACCU 1,	0


	// Retrigger
	__STWRST
	L		0
	SA		T 10
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	SET
	L		W#16#0010
	SA		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT==	__ACCU 1,	0
	CLR
	L		W#16#0010
	SA		T 10
	__SLEEP		20
	SET
	SA		T 10
	L		T 10
	__ASSERT>=	__ACCU 1,	2
	__SLEEP		101
	L		T 10
	__ASSERT==	__ACCU 1,	__ACCU 2


	// Reset signal
	__STWRST
	L		0
	SA		T 10
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	SET
	L		W#16#0010
	SA		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT==	__ACCU 1,	0
	__ASSERT==	__ACCU 1,	0
	CLR
	L		W#16#0010
	SA		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT>=	__ACCU 1,	5
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	L		T 10
	__ASSERT==	__ACCU 1,	0
	__SLEEP		101
	U		T 10
	__ASSERT==	__STW VKE,	0
	L		T 10
	__ASSERT==	__ACCU 1,	0


	// Test timer parameter
	AUF		DB 1
	L		DBW 0
	__ASSERT==	__ACCU 1,	24
	CALL FB 1, DB 1 (
		TIMER_VAR	:= T 42
	)


	CALL SFC 46 // STOP CPU
END_ORGANIZATION_BLOCK


FUNCTION_BLOCK FB 1
	VAR_INPUT
		TIMER_VAR	: TIMER;
	END_VAR
BEGIN
	L		DIW 0
	__ASSERT==	__ACCU 1,	42
	L		#TIMER_VAR
	__ASSERT==	__ACCU 1,	0
	U		#TIMER_VAR
	__ASSERT==	__STW VKE,	0

	SA		#TIMER_VAR
END_FUNCTION_BLOCK


DATA_BLOCK DB 1
	FB 1
BEGIN
	TIMER_VAR	:= T 24;
END_DATA_BLOCK