liberatehongkong
/
linux-kernel-module-cheat


			
				
					
						
						
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<meta name="description" content="The perfect emulation setup to study and develop the &lt;&lt;linux-kernel&gt;&gt; v5.9.2, kernel modules, &lt;&lt;qemu-buildroot-setup,QEMU&gt;&gt;, &lt;&lt;gem5-buildroot-setup,gem5&gt;&gt; and x86_64, ARMv7 and ARMv8 &lt;&lt;userland-assembly,userland&gt;&gt; and &lt;&lt;baremetal-setup,baremetal&gt;&gt; assembly, &lt;&lt;c,ANSI C&gt;&gt;, &lt;&lt;cpp,C++&gt;&gt; and &lt;&lt;posix,POSIX&gt;&gt;. &lt;&lt;gdb&gt;&gt; and &lt;&lt;kgdb&gt;&gt; just work. Powered by &lt;&lt;about-the-qemu-buildroot-setup,Buildroot&gt;&gt; and &lt;&lt;about-the-baremetal-setup,crosstool-NG&gt;&gt;. Highly automated. Thoroughly documented. Automated &lt;&lt;test-this-repo,tests&gt;&gt;. "Tested" in an Ubuntu 20.04 host.">
<title>Linux Kernel Module Cheat</title>
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</head>
<body id="timingsimplecpu-analysis-ldr-stall" class="article">
<div id="header">
<h1>Linux Kernel Module Cheat</h1>
</div>
<div id="content">
<div class="sect5">
<h6 id="timingsimplecpu-analysis-ldr-stall"><a class="anchor" href="#timingsimplecpu-analysis-ldr-stall"></a><a class="link" href="#timingsimplecpu-analysis-ldr-stall">24.22.4.2.30. TimingSimpleCPU analysis: LDR stall</a></h6>
<div class="paragraph">
<p>One important thing we want to check now, is how the memory reads are going to make the processor stall in the middle of an instruction.</p>
</div>
<div class="paragraph">
<p>This is also discussed at: <a href="gem5-execute-vs-initiateacc-vs-completeacc.html">gem5 <code>execute</code> vs <code>initiateAcc</code> vs <code>completeAcc</code></a>.</p>
</div>
<div class="paragraph">
<p>Since we were using a simple CPU without a pipeline, the data memory access stall everything: there is no further progress until memory comes back.</p>
</div>
<div class="paragraph">
<p>For that, we can GDB to the <code>TimingSimpleCPU::completeIfetch</code> of the first LDR done in our test program.</p>
</div>
<div class="paragraph">
<p>By doing that, we see that this time at:</p>
</div>
<div class="literalblock">
<div class="content">
<pre>if (curStaticInst &amp;&amp; curStaticInst-&gt;isMemRef()) {
    // load or store: just send to dcache
    Fault fault = curStaticInst-&gt;initiateAcc(&amp;t_info, traceData);

    if (_status == BaseSimpleCPU::Running) {
    }
} else if (curStaticInst) {
    // non-memory instruction: execute completely now
    Fault fault = curStaticInst-&gt;execute(&amp;t_info, traceData);</pre>
</div>
</div>
<div class="ulist">
<ul>
<li>
<p><code>curStaticInst-&gt;isMemRef()</code> is true, and there is no instruction <code>execute</code> call in that part of the branch, only for instructions that don&#8217;t touch memory</p>
</li>
<li>
<p><code>_status</code> is <code>BaseSimpleCPU::Status::DcacheWaitResponse</code> and <code>advanceInst</code> is not yet called</p>
</li>
</ul>
</div>
<div class="paragraph">
<p>We can verify that <code>execute</code> never happens by putting a breakpoint on <code>ArmISAInst::LDRXL64_LIT::execute</code> which never gets called.</p>
</div>
<div class="paragraph">
<p>Therefore, we conclude that <code>initiateAcc</code> is what actually starts the memory request.</p>
</div>
<div class="paragraph">
<p>Later on, when the memory access completes the event calls <code>TimingSimpleCPU::completeDataAccess</code> which calls <code>ArmISAInst::LDRXL64_LIT::completeAcc</code>, which sets the register value to what was read from memory.</p>
</div>
<div class="paragraph">
<p>More memory event details can be seen at: <a href="gem5-functional-vs-atomic-vs-timing-memory-requests.html">gem5 functional vs atomic vs timing memory requests</a>.</p>
</div>
<div class="paragraph">
<p>The following is the region of interest of the event log:</p>
</div>
<div class="literalblock">
<div class="content">
<pre> 175000: Event: Event_40: Timing CPU icache tick 40 executed @ 175000
 175000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 175000
 175000: Event: system.membus.reqLayer0.wrapped_function_event: EventFunctionWrapped 60 scheduled @ 176000

 175000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 9 executed @ 175000
 175000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 scheduled @ 193750
 175000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 9 scheduled @ 175000

 175000: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 9 executed @ 175000

 176000: Event: system.membus.reqLayer0.wrapped_function_event: EventFunctionWrapped 60 executed @ 176000

 193750: Event: system.mem_ctrls.wrapped_function_event: EventFunctionWrapped 10 executed @ 193750
 193750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 8 scheduled @ 221750

 221750: Event: system.mem_ctrls.port-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 8 executed @ 221750
 221750: Event: system.membus.slave[2]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 66 scheduled @ 224000
 221750: Event: system.membus.respLayer2.wrapped_function_event: EventFunctionWrapped 67 scheduled @ 224000

 224000: Event: system.membus.respLayer2.wrapped_function_event: EventFunctionWrapped 67 executed @ 224000

 224000: Event: system.membus.slave[2]-RespPacketQueue.wrapped_function_event: EventFunctionWrapped 66 executed @ 224000
 224000: Event: Event_42: Timing CPU dcache tick 42 scheduled @ 224000

 224000: Event: Event_42: Timing CPU dcache tick 42 executed @ 224000
 175000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8    :   ldr   w2, #4194464       : MemRead :  D=0x0000000000000006 A=0x4000a0  flags=(IsInteger|IsMemRef|IsLoad)</pre>
</div>
</div>
<div class="paragraph">
<p>We first find it by looking for the <code>ExecEnable</code> of LDR.</p>
</div>
<div class="paragraph">
<p>Then, we go up to the previous <code>Timing CPU icache tick</code> event, which from the analysis of previous instruction traces, we know is where the instruction execution starts, the LDR instruction fetch is done by then!</p>
</div>
<div class="paragraph">
<p>Next, several events happen as the data request must be percolating through the memory system, it must be very similar to the instruction fetches. TODO analyze event function names.</p>
</div>
<div class="paragraph">
<p>Finally, at last we reach</p>
</div>
<div class="literalblock">
<div class="content">
<pre> 224000: Event: Event_42: Timing CPU dcache tick 42 executed @ 224000
 175000: ExecEnable: system.cpu: A0 T0 : @asm_main_after_prologue+8    :   ldr   w2, #4194464       : MemRead :  D=0x0000000000000006 A=0x4000a0  flags=(IsInteger|IsMemRef|IsLoad)</pre>
</div>
</div>
<div class="paragraph">
<p>from which we guess:</p>
</div>
<div class="ulist">
<ul>
<li>
<p><code>224000</code>: this is the time that the data request finally returned, and at which execute gets called</p>
</li>
<li>
<p><code>175000</code>: the log finally prints at the end of execution, but it does not show the actual time that things finished, but rather the time that the ifetch finished, which happened in the past</p>
</li>
</ul>
</div>
<div class="ulist">
<ul>
</ul>
</div>
</div>
<div class="paragraph nav-footer">
<p>← Previous: <a href="timingsimplecpu-analysis-29.html">TimingSimpleCPU analysis #29</a> | ↑ Up: <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="gem5-event-queue-timingsimplecpu-syscall-emulation-freestanding-example-analysis-with-caches.html">gem5 event queue TimingSimpleCPU syscall emulation freestanding example analysis with caches</a> →</p>
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