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- Verilator is the fastest free Verilog HDL simulator, and beats most
- commercial simulators. It compiles synthesizable Verilog (not test-bench
- code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
- or SystemC code. It is designed for large projects where fast simulation
- performance is of primary concern, and is especially well suited to
- generate executable models of CPUs for embedded software design teams.
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