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- # $OpenBSD: Makefile,v 1.9 2017/04/10 11:46:22 sthen Exp $
- COMMENT= very fast free Verilog HDL simulator
- DISTNAME = verilator-3.900
- CATEGORIES= lang devel
- HOMEPAGE= http://www.veripool.org/wiki/verilator/Intro
- # LGPLv3 or Perl
- PERMIT_PACKAGE_CDROM= Yes
- MASTER_SITES= http://www.veripool.org/ftp/
- EXTRACT_SUFX= .tgz
- WANTLIB= c m ${LIBCXX}
- BUILD_DEPENDS += devel/bison
- CONFIGURE_STYLE= gnu
- MAKE_FLAGS= VERILATOR_ROOT=${PREFIX}/share/verilator/ \
- COPT="${CFLAGS}"
- USE_GMAKE= Yes
- TEST_TARGET= test
- TEST_FLAGS= VERILATOR_ROOT=${WRKSRC}
- .include <bsd.port.mk>
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