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- Icarus Verilog is a Verilog simulation and synthesis tool. It operates
- as a compiler, compiling source code writen in Verilog (IEEE-1364) into
- some target format. For batch simulation, the compiler can generate an
- intermediate form called vvp assembly. This intermediate form is
- executed by the "vvp" command. For synthesis, the compiler generates
- netlists in the desired format.
- The compiler proper is intended to parse and elaborate design
- descriptions written to the IEEE standard IEEE Std 1364-2005. This is a
- fairly large and complex standard, so it will take some time for it to
- get there, but that's the goal.
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