ssb_driver_gige.h 4.9 KB

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  1. #ifndef LINUX_SSB_DRIVER_GIGE_H_
  2. #define LINUX_SSB_DRIVER_GIGE_H_
  3. #include <linux/ssb/ssb.h>
  4. #include <linux/bug.h>
  5. #include <linux/pci.h>
  6. #include <linux/spinlock.h>
  7. #ifdef CONFIG_SSB_DRIVER_GIGE
  8. #define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
  9. #define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
  10. #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
  11. #define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
  12. #define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
  13. #define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
  14. #define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
  15. #define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
  16. #define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
  17. /* TM Status High flags */
  18. #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
  19. /* TM Status Low flags */
  20. #define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
  21. #define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
  22. #define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
  23. /* Boardflags (low) */
  24. #define SSB_GIGE_BFL_ROBOSWITCH 0x0010
  25. #define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
  26. #define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
  27. struct ssb_gige {
  28. struct ssb_device *dev;
  29. spinlock_t lock;
  30. /* True, if the device has an RGMII bus.
  31. * False, if the device has a GMII bus. */
  32. bool has_rgmii;
  33. /* The PCI controller device. */
  34. struct pci_controller pci_controller;
  35. struct pci_ops pci_ops;
  36. struct resource mem_resource;
  37. struct resource io_resource;
  38. };
  39. /* Check whether a PCI device is a SSB Gigabit Ethernet core. */
  40. extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
  41. /* Convert a pci_dev pointer to a ssb_gige pointer. */
  42. static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
  43. {
  44. if (!pdev_is_ssb_gige_core(pdev))
  45. return NULL;
  46. return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
  47. }
  48. /* Returns whether the PHY is connected by an RGMII bus. */
  49. static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
  50. {
  51. struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
  52. return (dev ? dev->has_rgmii : 0);
  53. }
  54. /* Returns whether we have a Roboswitch. */
  55. static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
  56. {
  57. struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
  58. if (dev)
  59. return !!(dev->dev->bus->sprom.boardflags_lo &
  60. SSB_GIGE_BFL_ROBOSWITCH);
  61. return 0;
  62. }
  63. /* Returns whether we can only do one DMA at once. */
  64. static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
  65. {
  66. struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
  67. if (dev)
  68. return ((dev->dev->bus->chip_id == 0x4785) &&
  69. (dev->dev->bus->chip_rev < 2));
  70. return 0;
  71. }
  72. /* Returns whether we must flush posted writes. */
  73. static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
  74. {
  75. struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
  76. if (dev)
  77. return (dev->dev->bus->chip_id == 0x4785);
  78. return 0;
  79. }
  80. #ifdef CONFIG_BCM47XX
  81. #include <asm/mach-bcm47xx/nvram.h>
  82. /* Get the device MAC address */
  83. static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
  84. {
  85. char buf[20];
  86. if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
  87. return;
  88. nvram_parse_macaddr(buf, macaddr);
  89. }
  90. #else
  91. static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
  92. {
  93. }
  94. #endif
  95. extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
  96. struct pci_dev *pdev);
  97. extern int ssb_gige_map_irq(struct ssb_device *sdev,
  98. const struct pci_dev *pdev);
  99. /* The GigE driver is not a standalone module, because we don't have support
  100. * for unregistering the driver. So we could not unload the module anyway. */
  101. extern int ssb_gige_init(void);
  102. static inline void ssb_gige_exit(void)
  103. {
  104. /* Currently we can not unregister the GigE driver,
  105. * because we can not unregister the PCI bridge. */
  106. BUG();
  107. }
  108. #else /* CONFIG_SSB_DRIVER_GIGE */
  109. /* Gigabit Ethernet driver disabled */
  110. static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
  111. struct pci_dev *pdev)
  112. {
  113. return -ENOSYS;
  114. }
  115. static inline int ssb_gige_map_irq(struct ssb_device *sdev,
  116. const struct pci_dev *pdev)
  117. {
  118. return -ENOSYS;
  119. }
  120. static inline int ssb_gige_init(void)
  121. {
  122. return 0;
  123. }
  124. static inline void ssb_gige_exit(void)
  125. {
  126. }
  127. static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
  128. {
  129. return 0;
  130. }
  131. static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
  132. {
  133. return NULL;
  134. }
  135. static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
  136. {
  137. return 0;
  138. }
  139. static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
  140. {
  141. return 0;
  142. }
  143. static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
  144. {
  145. return 0;
  146. }
  147. static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
  148. {
  149. return 0;
  150. }
  151. #endif /* CONFIG_SSB_DRIVER_GIGE */
  152. #endif /* LINUX_SSB_DRIVER_GIGE_H_ */