cm_bf537u.c 18 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2008-2009 Bluetechnix
  4. * 2005 National ICT Australia (NICTA)
  5. * Aidan Williams <aidan@nicta.com.au>
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <linux/device.h>
  10. #include <linux/etherdevice.h>
  11. #include <linux/export.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/partitions.h>
  15. #include <linux/mtd/physmap.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/spi/flash.h>
  18. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  19. #include <linux/usb/isp1362.h>
  20. #endif
  21. #include <linux/ata_platform.h>
  22. #include <linux/irq.h>
  23. #include <asm/dma.h>
  24. #include <asm/bfin5xx_spi.h>
  25. #include <asm/portmux.h>
  26. #include <asm/dpmc.h>
  27. #include <linux/spi/mmc_spi.h>
  28. /*
  29. * Name the Board for the /proc/cpuinfo
  30. */
  31. const char bfin_board_name[] = "Bluetechnix CM BF537U";
  32. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  33. /* all SPI peripherals info goes here */
  34. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  35. static struct mtd_partition bfin_spi_flash_partitions[] = {
  36. {
  37. .name = "bootloader(spi)",
  38. .size = 0x00020000,
  39. .offset = 0,
  40. .mask_flags = MTD_CAP_ROM
  41. }, {
  42. .name = "linux kernel(spi)",
  43. .size = 0xe0000,
  44. .offset = 0x20000
  45. }, {
  46. .name = "file system(spi)",
  47. .size = 0x700000,
  48. .offset = 0x00100000,
  49. }
  50. };
  51. static struct flash_platform_data bfin_spi_flash_data = {
  52. .name = "m25p80",
  53. .parts = bfin_spi_flash_partitions,
  54. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  55. .type = "m25p64",
  56. };
  57. /* SPI flash chip (m25p64) */
  58. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  59. .enable_dma = 0, /* use dma transfer with this chip*/
  60. };
  61. #endif
  62. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  63. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  64. .enable_dma = 0,
  65. };
  66. #endif
  67. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  68. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  69. {
  70. /* the modalias must be the same as spi device driver name */
  71. .modalias = "m25p80", /* Name of spi_driver for this device */
  72. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  73. .bus_num = 0, /* Framework bus number */
  74. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  75. .platform_data = &bfin_spi_flash_data,
  76. .controller_data = &spi_flash_chip_info,
  77. .mode = SPI_MODE_3,
  78. },
  79. #endif
  80. #if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
  81. {
  82. .modalias = "ad183x",
  83. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  84. .bus_num = 0,
  85. .chip_select = 4,
  86. },
  87. #endif
  88. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  89. {
  90. .modalias = "mmc_spi",
  91. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  92. .bus_num = 0,
  93. .chip_select = 1,
  94. .controller_data = &mmc_spi_chip_info,
  95. .mode = SPI_MODE_3,
  96. },
  97. #endif
  98. };
  99. /* SPI (0) */
  100. static struct resource bfin_spi0_resource[] = {
  101. [0] = {
  102. .start = SPI0_REGBASE,
  103. .end = SPI0_REGBASE + 0xFF,
  104. .flags = IORESOURCE_MEM,
  105. },
  106. [1] = {
  107. .start = CH_SPI,
  108. .end = CH_SPI,
  109. .flags = IORESOURCE_DMA,
  110. },
  111. [2] = {
  112. .start = IRQ_SPI,
  113. .end = IRQ_SPI,
  114. .flags = IORESOURCE_IRQ,
  115. },
  116. };
  117. /* SPI controller data */
  118. static struct bfin5xx_spi_master bfin_spi0_info = {
  119. .num_chipselect = 8,
  120. .enable_dma = 1, /* master has the ability to do dma transfer */
  121. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  122. };
  123. static struct platform_device bfin_spi0_device = {
  124. .name = "bfin-spi",
  125. .id = 0, /* Bus number */
  126. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  127. .resource = bfin_spi0_resource,
  128. .dev = {
  129. .platform_data = &bfin_spi0_info, /* Passed to driver */
  130. },
  131. };
  132. #endif /* spi master and devices */
  133. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  134. static struct platform_device rtc_device = {
  135. .name = "rtc-bfin",
  136. .id = -1,
  137. };
  138. #endif
  139. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  140. static struct platform_device hitachi_fb_device = {
  141. .name = "hitachi-tx09",
  142. };
  143. #endif
  144. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  145. #include <linux/smc91x.h>
  146. static struct smc91x_platdata smc91x_info = {
  147. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  148. .leda = RPC_LED_100_10,
  149. .ledb = RPC_LED_TX_RX,
  150. };
  151. static struct resource smc91x_resources[] = {
  152. {
  153. .start = 0x20200300,
  154. .end = 0x20200300 + 16,
  155. .flags = IORESOURCE_MEM,
  156. }, {
  157. .start = IRQ_PF14,
  158. .end = IRQ_PF14,
  159. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  160. },
  161. };
  162. static struct platform_device smc91x_device = {
  163. .name = "smc91x",
  164. .id = 0,
  165. .num_resources = ARRAY_SIZE(smc91x_resources),
  166. .resource = smc91x_resources,
  167. .dev = {
  168. .platform_data = &smc91x_info,
  169. },
  170. };
  171. #endif
  172. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  173. static struct resource isp1362_hcd_resources[] = {
  174. {
  175. .start = 0x20308000,
  176. .end = 0x20308000,
  177. .flags = IORESOURCE_MEM,
  178. }, {
  179. .start = 0x20308004,
  180. .end = 0x20308004,
  181. .flags = IORESOURCE_MEM,
  182. }, {
  183. .start = IRQ_PG15,
  184. .end = IRQ_PG15,
  185. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  186. },
  187. };
  188. static struct isp1362_platform_data isp1362_priv = {
  189. .sel15Kres = 1,
  190. .clknotstop = 0,
  191. .oc_enable = 0,
  192. .int_act_high = 0,
  193. .int_edge_triggered = 0,
  194. .remote_wakeup_connected = 0,
  195. .no_power_switching = 1,
  196. .power_switching_mode = 0,
  197. };
  198. static struct platform_device isp1362_hcd_device = {
  199. .name = "isp1362-hcd",
  200. .id = 0,
  201. .dev = {
  202. .platform_data = &isp1362_priv,
  203. },
  204. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  205. .resource = isp1362_hcd_resources,
  206. };
  207. #endif
  208. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  209. static struct resource net2272_bfin_resources[] = {
  210. {
  211. .start = 0x20200000,
  212. .end = 0x20200000 + 0x100,
  213. .flags = IORESOURCE_MEM,
  214. }, {
  215. .start = IRQ_PH14,
  216. .end = IRQ_PH14,
  217. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  218. },
  219. };
  220. static struct platform_device net2272_bfin_device = {
  221. .name = "net2272",
  222. .id = -1,
  223. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  224. .resource = net2272_bfin_resources,
  225. };
  226. #endif
  227. #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
  228. static struct mtd_partition cm_partitions[] = {
  229. {
  230. .name = "bootloader(nor)",
  231. .size = 0x40000,
  232. .offset = 0,
  233. }, {
  234. .name = "linux kernel(nor)",
  235. .size = 0x100000,
  236. .offset = MTDPART_OFS_APPEND,
  237. }, {
  238. .name = "file system(nor)",
  239. .size = MTDPART_SIZ_FULL,
  240. .offset = MTDPART_OFS_APPEND,
  241. }
  242. };
  243. static struct physmap_flash_data cm_flash_data = {
  244. .width = 2,
  245. .parts = cm_partitions,
  246. .nr_parts = ARRAY_SIZE(cm_partitions),
  247. };
  248. static unsigned cm_flash_gpios[] = { GPIO_PH0 };
  249. static struct resource cm_flash_resource[] = {
  250. {
  251. .name = "cfi_probe",
  252. .start = 0x20000000,
  253. .end = 0x201fffff,
  254. .flags = IORESOURCE_MEM,
  255. }, {
  256. .start = (unsigned long)cm_flash_gpios,
  257. .end = ARRAY_SIZE(cm_flash_gpios),
  258. .flags = IORESOURCE_IRQ,
  259. }
  260. };
  261. static struct platform_device cm_flash_device = {
  262. .name = "gpio-addr-flash",
  263. .id = 0,
  264. .dev = {
  265. .platform_data = &cm_flash_data,
  266. },
  267. .num_resources = ARRAY_SIZE(cm_flash_resource),
  268. .resource = cm_flash_resource,
  269. };
  270. #endif
  271. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  272. #ifdef CONFIG_SERIAL_BFIN_UART0
  273. static struct resource bfin_uart0_resources[] = {
  274. {
  275. .start = UART0_THR,
  276. .end = UART0_GCTL+2,
  277. .flags = IORESOURCE_MEM,
  278. },
  279. {
  280. .start = IRQ_UART0_TX,
  281. .end = IRQ_UART0_TX,
  282. .flags = IORESOURCE_IRQ,
  283. },
  284. {
  285. .start = IRQ_UART0_RX,
  286. .end = IRQ_UART0_RX,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. {
  290. .start = IRQ_UART0_ERROR,
  291. .end = IRQ_UART0_ERROR,
  292. .flags = IORESOURCE_IRQ,
  293. },
  294. {
  295. .start = CH_UART0_TX,
  296. .end = CH_UART0_TX,
  297. .flags = IORESOURCE_DMA,
  298. },
  299. {
  300. .start = CH_UART0_RX,
  301. .end = CH_UART0_RX,
  302. .flags = IORESOURCE_DMA,
  303. },
  304. };
  305. static unsigned short bfin_uart0_peripherals[] = {
  306. P_UART0_TX, P_UART0_RX, 0
  307. };
  308. static struct platform_device bfin_uart0_device = {
  309. .name = "bfin-uart",
  310. .id = 0,
  311. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  312. .resource = bfin_uart0_resources,
  313. .dev = {
  314. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  315. },
  316. };
  317. #endif
  318. #ifdef CONFIG_SERIAL_BFIN_UART1
  319. static struct resource bfin_uart1_resources[] = {
  320. {
  321. .start = UART1_THR,
  322. .end = UART1_GCTL+2,
  323. .flags = IORESOURCE_MEM,
  324. },
  325. {
  326. .start = IRQ_UART1_TX,
  327. .end = IRQ_UART1_TX,
  328. .flags = IORESOURCE_IRQ,
  329. },
  330. {
  331. .start = IRQ_UART1_RX,
  332. .end = IRQ_UART1_RX,
  333. .flags = IORESOURCE_IRQ,
  334. },
  335. {
  336. .start = IRQ_UART1_ERROR,
  337. .end = IRQ_UART1_ERROR,
  338. .flags = IORESOURCE_IRQ,
  339. },
  340. {
  341. .start = CH_UART1_TX,
  342. .end = CH_UART1_TX,
  343. .flags = IORESOURCE_DMA,
  344. },
  345. {
  346. .start = CH_UART1_RX,
  347. .end = CH_UART1_RX,
  348. .flags = IORESOURCE_DMA,
  349. },
  350. };
  351. static unsigned short bfin_uart1_peripherals[] = {
  352. P_UART1_TX, P_UART1_RX, 0
  353. };
  354. static struct platform_device bfin_uart1_device = {
  355. .name = "bfin-uart",
  356. .id = 1,
  357. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  358. .resource = bfin_uart1_resources,
  359. .dev = {
  360. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  361. },
  362. };
  363. #endif
  364. #endif
  365. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  366. #ifdef CONFIG_BFIN_SIR0
  367. static struct resource bfin_sir0_resources[] = {
  368. {
  369. .start = 0xFFC00400,
  370. .end = 0xFFC004FF,
  371. .flags = IORESOURCE_MEM,
  372. },
  373. {
  374. .start = IRQ_UART0_RX,
  375. .end = IRQ_UART0_RX+1,
  376. .flags = IORESOURCE_IRQ,
  377. },
  378. {
  379. .start = CH_UART0_RX,
  380. .end = CH_UART0_RX+1,
  381. .flags = IORESOURCE_DMA,
  382. },
  383. };
  384. static struct platform_device bfin_sir0_device = {
  385. .name = "bfin_sir",
  386. .id = 0,
  387. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  388. .resource = bfin_sir0_resources,
  389. };
  390. #endif
  391. #ifdef CONFIG_BFIN_SIR1
  392. static struct resource bfin_sir1_resources[] = {
  393. {
  394. .start = 0xFFC02000,
  395. .end = 0xFFC020FF,
  396. .flags = IORESOURCE_MEM,
  397. },
  398. {
  399. .start = IRQ_UART1_RX,
  400. .end = IRQ_UART1_RX+1,
  401. .flags = IORESOURCE_IRQ,
  402. },
  403. {
  404. .start = CH_UART1_RX,
  405. .end = CH_UART1_RX+1,
  406. .flags = IORESOURCE_DMA,
  407. },
  408. };
  409. static struct platform_device bfin_sir1_device = {
  410. .name = "bfin_sir",
  411. .id = 1,
  412. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  413. .resource = bfin_sir1_resources,
  414. };
  415. #endif
  416. #endif
  417. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  418. static struct resource bfin_twi0_resource[] = {
  419. [0] = {
  420. .start = TWI0_REGBASE,
  421. .end = TWI0_REGBASE,
  422. .flags = IORESOURCE_MEM,
  423. },
  424. [1] = {
  425. .start = IRQ_TWI,
  426. .end = IRQ_TWI,
  427. .flags = IORESOURCE_IRQ,
  428. },
  429. };
  430. static struct platform_device i2c_bfin_twi_device = {
  431. .name = "i2c-bfin-twi",
  432. .id = 0,
  433. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  434. .resource = bfin_twi0_resource,
  435. };
  436. #endif
  437. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  438. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  439. static struct resource bfin_sport0_uart_resources[] = {
  440. {
  441. .start = SPORT0_TCR1,
  442. .end = SPORT0_MRCS3+4,
  443. .flags = IORESOURCE_MEM,
  444. },
  445. {
  446. .start = IRQ_SPORT0_RX,
  447. .end = IRQ_SPORT0_RX+1,
  448. .flags = IORESOURCE_IRQ,
  449. },
  450. {
  451. .start = IRQ_SPORT0_ERROR,
  452. .end = IRQ_SPORT0_ERROR,
  453. .flags = IORESOURCE_IRQ,
  454. },
  455. };
  456. static unsigned short bfin_sport0_peripherals[] = {
  457. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  458. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  459. };
  460. static struct platform_device bfin_sport0_uart_device = {
  461. .name = "bfin-sport-uart",
  462. .id = 0,
  463. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  464. .resource = bfin_sport0_uart_resources,
  465. .dev = {
  466. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  467. },
  468. };
  469. #endif
  470. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  471. static struct resource bfin_sport1_uart_resources[] = {
  472. {
  473. .start = SPORT1_TCR1,
  474. .end = SPORT1_MRCS3+4,
  475. .flags = IORESOURCE_MEM,
  476. },
  477. {
  478. .start = IRQ_SPORT1_RX,
  479. .end = IRQ_SPORT1_RX+1,
  480. .flags = IORESOURCE_IRQ,
  481. },
  482. {
  483. .start = IRQ_SPORT1_ERROR,
  484. .end = IRQ_SPORT1_ERROR,
  485. .flags = IORESOURCE_IRQ,
  486. },
  487. };
  488. static unsigned short bfin_sport1_peripherals[] = {
  489. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  490. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  491. };
  492. static struct platform_device bfin_sport1_uart_device = {
  493. .name = "bfin-sport-uart",
  494. .id = 1,
  495. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  496. .resource = bfin_sport1_uart_resources,
  497. .dev = {
  498. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  499. },
  500. };
  501. #endif
  502. #endif
  503. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  504. #include <linux/bfin_mac.h>
  505. static const unsigned short bfin_mac_peripherals[] = P_MII0;
  506. static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  507. {
  508. .addr = 1,
  509. .irq = IRQ_MAC_PHYINT,
  510. },
  511. };
  512. static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  513. .phydev_number = 1,
  514. .phydev_data = bfin_phydev_data,
  515. .phy_mode = PHY_INTERFACE_MODE_MII,
  516. .mac_peripherals = bfin_mac_peripherals,
  517. };
  518. static struct platform_device bfin_mii_bus = {
  519. .name = "bfin_mii_bus",
  520. .dev = {
  521. .platform_data = &bfin_mii_bus_data,
  522. }
  523. };
  524. static struct platform_device bfin_mac_device = {
  525. .name = "bfin_mac",
  526. .dev = {
  527. .platform_data = &bfin_mii_bus,
  528. }
  529. };
  530. #endif
  531. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  532. #define PATA_INT IRQ_PF14
  533. static struct pata_platform_info bfin_pata_platform_data = {
  534. .ioport_shift = 2,
  535. .irq_type = IRQF_TRIGGER_HIGH,
  536. };
  537. static struct resource bfin_pata_resources[] = {
  538. {
  539. .start = 0x2030C000,
  540. .end = 0x2030C01F,
  541. .flags = IORESOURCE_MEM,
  542. },
  543. {
  544. .start = 0x2030D018,
  545. .end = 0x2030D01B,
  546. .flags = IORESOURCE_MEM,
  547. },
  548. {
  549. .start = PATA_INT,
  550. .end = PATA_INT,
  551. .flags = IORESOURCE_IRQ,
  552. },
  553. };
  554. static struct platform_device bfin_pata_device = {
  555. .name = "pata_platform",
  556. .id = -1,
  557. .num_resources = ARRAY_SIZE(bfin_pata_resources),
  558. .resource = bfin_pata_resources,
  559. .dev = {
  560. .platform_data = &bfin_pata_platform_data,
  561. }
  562. };
  563. #endif
  564. static const unsigned int cclk_vlev_datasheet[] =
  565. {
  566. VRPAIR(VLEV_085, 250000000),
  567. VRPAIR(VLEV_090, 376000000),
  568. VRPAIR(VLEV_095, 426000000),
  569. VRPAIR(VLEV_100, 426000000),
  570. VRPAIR(VLEV_105, 476000000),
  571. VRPAIR(VLEV_110, 476000000),
  572. VRPAIR(VLEV_115, 476000000),
  573. VRPAIR(VLEV_120, 500000000),
  574. VRPAIR(VLEV_125, 533000000),
  575. VRPAIR(VLEV_130, 600000000),
  576. };
  577. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  578. .tuple_tab = cclk_vlev_datasheet,
  579. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  580. .vr_settling_time = 25 /* us */,
  581. };
  582. static struct platform_device bfin_dpmc = {
  583. .name = "bfin dpmc",
  584. .dev = {
  585. .platform_data = &bfin_dmpc_vreg_data,
  586. },
  587. };
  588. static struct platform_device *cm_bf537u_devices[] __initdata = {
  589. &bfin_dpmc,
  590. #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
  591. &hitachi_fb_device,
  592. #endif
  593. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  594. &rtc_device,
  595. #endif
  596. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  597. #ifdef CONFIG_SERIAL_BFIN_UART0
  598. &bfin_uart0_device,
  599. #endif
  600. #ifdef CONFIG_SERIAL_BFIN_UART1
  601. &bfin_uart1_device,
  602. #endif
  603. #endif
  604. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  605. #ifdef CONFIG_BFIN_SIR0
  606. &bfin_sir0_device,
  607. #endif
  608. #ifdef CONFIG_BFIN_SIR1
  609. &bfin_sir1_device,
  610. #endif
  611. #endif
  612. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  613. &i2c_bfin_twi_device,
  614. #endif
  615. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  616. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  617. &bfin_sport0_uart_device,
  618. #endif
  619. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  620. &bfin_sport1_uart_device,
  621. #endif
  622. #endif
  623. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  624. &isp1362_hcd_device,
  625. #endif
  626. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  627. &smc91x_device,
  628. #endif
  629. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  630. &bfin_mii_bus,
  631. &bfin_mac_device,
  632. #endif
  633. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  634. &net2272_bfin_device,
  635. #endif
  636. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  637. &bfin_spi0_device,
  638. #endif
  639. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  640. &bfin_pata_device,
  641. #endif
  642. #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
  643. &cm_flash_device,
  644. #endif
  645. };
  646. static int __init net2272_init(void)
  647. {
  648. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  649. int ret;
  650. ret = gpio_request(GPIO_PH15, driver_name);
  651. if (ret)
  652. return ret;
  653. ret = gpio_request(GPIO_PH13, "net2272");
  654. if (ret) {
  655. gpio_free(GPIO_PH15);
  656. return ret;
  657. }
  658. /* Set PH15 Low make /AMS2 work properly */
  659. gpio_direction_output(GPIO_PH15, 0);
  660. /* enable CLKBUF output */
  661. bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
  662. /* Reset the USB chip */
  663. gpio_direction_output(GPIO_PH13, 0);
  664. mdelay(2);
  665. gpio_set_value(GPIO_PH13, 1);
  666. #endif
  667. return 0;
  668. }
  669. static int __init cm_bf537u_init(void)
  670. {
  671. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  672. platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
  673. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  674. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  675. #endif
  676. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  677. irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
  678. #endif
  679. if (net2272_init())
  680. pr_warning("unable to configure net2272; it probably won't work\n");
  681. return 0;
  682. }
  683. arch_initcall(cm_bf537u_init);
  684. static struct platform_device *cm_bf537u_early_devices[] __initdata = {
  685. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  686. #ifdef CONFIG_SERIAL_BFIN_UART0
  687. &bfin_uart0_device,
  688. #endif
  689. #ifdef CONFIG_SERIAL_BFIN_UART1
  690. &bfin_uart1_device,
  691. #endif
  692. #endif
  693. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  694. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  695. &bfin_sport0_uart_device,
  696. #endif
  697. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  698. &bfin_sport1_uart_device,
  699. #endif
  700. #endif
  701. };
  702. void __init native_machine_early_platform_add_devices(void)
  703. {
  704. printk(KERN_INFO "register early platform devices\n");
  705. early_platform_add_devices(cm_bf537u_early_devices,
  706. ARRAY_SIZE(cm_bf537u_early_devices));
  707. }
  708. int bfin_get_ether_addr(char *addr)
  709. {
  710. return 1;
  711. }
  712. EXPORT_SYMBOL(bfin_get_ether_addr);