fw_common.c 23 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../base.h"
  32. #include "../rtl8192ce/reg.h"
  33. #include "../rtl8192ce/def.h"
  34. #include "fw_common.h"
  35. #include <linux/export.h>
  36. static void _rtl92c_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  37. {
  38. struct rtl_priv *rtlpriv = rtl_priv(hw);
  39. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  40. if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) {
  41. u32 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  42. if (enable)
  43. value32 |= MCUFWDL_EN;
  44. else
  45. value32 &= ~MCUFWDL_EN;
  46. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  47. } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) {
  48. u8 tmp;
  49. if (enable) {
  50. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  51. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
  52. tmp | 0x04);
  53. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  54. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
  55. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  56. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  57. } else {
  58. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  59. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  60. rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
  61. }
  62. }
  63. }
  64. static void rtl_block_fw_writeN(struct ieee80211_hw *hw, const u8 *buffer,
  65. u32 size)
  66. {
  67. struct rtl_priv *rtlpriv = rtl_priv(hw);
  68. u32 blockSize = REALTEK_USB_VENQT_MAX_BUF_SIZE - 20;
  69. u8 *bufferPtr = (u8 *) buffer;
  70. u32 i, offset, blockCount, remainSize;
  71. blockCount = size / blockSize;
  72. remainSize = size % blockSize;
  73. for (i = 0; i < blockCount; i++) {
  74. offset = i * blockSize;
  75. rtlpriv->io.writeN_sync(rtlpriv,
  76. (FW_8192C_START_ADDRESS + offset),
  77. (void *)(bufferPtr + offset),
  78. blockSize);
  79. }
  80. if (remainSize) {
  81. offset = blockCount * blockSize;
  82. rtlpriv->io.writeN_sync(rtlpriv,
  83. (FW_8192C_START_ADDRESS + offset),
  84. (void *)(bufferPtr + offset),
  85. remainSize);
  86. }
  87. }
  88. static void _rtl92c_fw_block_write(struct ieee80211_hw *hw,
  89. const u8 *buffer, u32 size)
  90. {
  91. struct rtl_priv *rtlpriv = rtl_priv(hw);
  92. u32 blockSize = sizeof(u32);
  93. u8 *bufferPtr = (u8 *) buffer;
  94. u32 *pu4BytePtr = (u32 *) buffer;
  95. u32 i, offset, blockCount, remainSize;
  96. u32 data;
  97. if (rtlpriv->io.writeN_sync) {
  98. rtl_block_fw_writeN(hw, buffer, size);
  99. return;
  100. }
  101. blockCount = size / blockSize;
  102. remainSize = size % blockSize;
  103. if (remainSize) {
  104. /* the last word is < 4 bytes - pad it with zeros */
  105. for (i = 0; i < 4 - remainSize; i++)
  106. *(bufferPtr + size + i) = 0;
  107. blockCount++;
  108. }
  109. for (i = 0; i < blockCount; i++) {
  110. offset = i * blockSize;
  111. /* for big-endian platforms, the firmware data need to be byte
  112. * swapped as it was read as a byte string and will be written
  113. * as 32-bit dwords and byte swapped when written
  114. */
  115. data = le32_to_cpu(*(__le32 *)(pu4BytePtr + i));
  116. rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
  117. data);
  118. }
  119. }
  120. static void _rtl92c_fw_page_write(struct ieee80211_hw *hw,
  121. u32 page, const u8 *buffer, u32 size)
  122. {
  123. struct rtl_priv *rtlpriv = rtl_priv(hw);
  124. u8 value8;
  125. u8 u8page = (u8) (page & 0x07);
  126. value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
  127. rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
  128. _rtl92c_fw_block_write(hw, buffer, size);
  129. }
  130. static void _rtl92c_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
  131. {
  132. u32 fwlen = *pfwlen;
  133. u8 remain = (u8) (fwlen % 4);
  134. remain = (remain == 0) ? 0 : (4 - remain);
  135. while (remain > 0) {
  136. pfwbuf[fwlen] = 0;
  137. fwlen++;
  138. remain--;
  139. }
  140. *pfwlen = fwlen;
  141. }
  142. static void _rtl92c_write_fw(struct ieee80211_hw *hw,
  143. enum version_8192c version, u8 *buffer, u32 size)
  144. {
  145. struct rtl_priv *rtlpriv = rtl_priv(hw);
  146. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  147. u8 *bufferPtr = buffer;
  148. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes\n", size);
  149. if (IS_CHIP_VER_B(version)) {
  150. u32 pageNums, remainSize;
  151. u32 page, offset;
  152. if (IS_HARDWARE_TYPE_8192CE(rtlhal))
  153. _rtl92c_fill_dummy(bufferPtr, &size);
  154. pageNums = size / FW_8192C_PAGE_SIZE;
  155. remainSize = size % FW_8192C_PAGE_SIZE;
  156. if (pageNums > 4) {
  157. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  158. "Page numbers should not greater then 4\n");
  159. }
  160. for (page = 0; page < pageNums; page++) {
  161. offset = page * FW_8192C_PAGE_SIZE;
  162. _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
  163. FW_8192C_PAGE_SIZE);
  164. }
  165. if (remainSize) {
  166. offset = pageNums * FW_8192C_PAGE_SIZE;
  167. page = pageNums;
  168. _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
  169. remainSize);
  170. }
  171. } else {
  172. _rtl92c_fw_block_write(hw, buffer, size);
  173. }
  174. }
  175. static int _rtl92c_fw_free_to_go(struct ieee80211_hw *hw)
  176. {
  177. struct rtl_priv *rtlpriv = rtl_priv(hw);
  178. u32 counter = 0;
  179. u32 value32;
  180. do {
  181. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  182. } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
  183. (!(value32 & FWDL_ChkSum_rpt)));
  184. if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
  185. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  186. "chksum report faill ! REG_MCUFWDL:0x%08x\n", value32);
  187. return -EIO;
  188. }
  189. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  190. "Checksum report OK ! REG_MCUFWDL:0x%08x\n", value32);
  191. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  192. value32 |= MCUFWDL_RDY;
  193. value32 &= ~WINTINI_RDY;
  194. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  195. counter = 0;
  196. do {
  197. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  198. if (value32 & WINTINI_RDY) {
  199. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  200. "Polling FW ready success!! REG_MCUFWDL:0x%08x\n",
  201. value32);
  202. return 0;
  203. }
  204. mdelay(FW_8192C_POLLING_DELAY);
  205. } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
  206. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  207. "Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", value32);
  208. return -EIO;
  209. }
  210. int rtl92c_download_fw(struct ieee80211_hw *hw)
  211. {
  212. struct rtl_priv *rtlpriv = rtl_priv(hw);
  213. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  214. struct rtl92c_firmware_header *pfwheader;
  215. u8 *pfwdata;
  216. u32 fwsize;
  217. enum version_8192c version = rtlhal->version;
  218. if (rtlpriv->max_fw_size == 0 || !rtlhal->pfirmware)
  219. return 1;
  220. pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
  221. pfwdata = rtlhal->pfirmware;
  222. fwsize = rtlhal->fwsize;
  223. if (IS_FW_HEADER_EXIST(pfwheader)) {
  224. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  225. "Firmware Version(%d), Signature(%#x),Size(%d)\n",
  226. le16_to_cpu(pfwheader->version),
  227. le16_to_cpu(pfwheader->signature),
  228. (uint)sizeof(struct rtl92c_firmware_header));
  229. pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
  230. fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
  231. }
  232. _rtl92c_enable_fw_download(hw, true);
  233. _rtl92c_write_fw(hw, version, pfwdata, fwsize);
  234. _rtl92c_enable_fw_download(hw, false);
  235. if (_rtl92c_fw_free_to_go(hw)) {
  236. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  237. "Firmware is not ready to run!\n");
  238. } else {
  239. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  240. "Firmware is ready to run!\n");
  241. }
  242. return 0;
  243. }
  244. EXPORT_SYMBOL(rtl92c_download_fw);
  245. static bool _rtl92c_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  246. {
  247. struct rtl_priv *rtlpriv = rtl_priv(hw);
  248. u8 val_hmetfr, val_mcutst_1;
  249. bool result = false;
  250. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  251. val_mcutst_1 = rtl_read_byte(rtlpriv, (REG_MCUTST_1 + boxnum));
  252. if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0)
  253. result = true;
  254. return result;
  255. }
  256. static void _rtl92c_fill_h2c_command(struct ieee80211_hw *hw,
  257. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  258. {
  259. struct rtl_priv *rtlpriv = rtl_priv(hw);
  260. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  261. u8 boxnum;
  262. u16 box_reg = 0, box_extreg = 0;
  263. u8 u1b_tmp;
  264. bool isfw_read = false;
  265. bool bwrite_sucess = false;
  266. u8 wait_h2c_limmit = 100;
  267. u8 wait_writeh2c_limmit = 100;
  268. u8 boxcontent[4], boxextcontent[2];
  269. u32 h2c_waitcounter = 0;
  270. unsigned long flag;
  271. u8 idx;
  272. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  273. while (true) {
  274. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  275. if (rtlhal->h2c_setinprogress) {
  276. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  277. "H2C set in progress! Wait to set..element_id(%d)\n",
  278. element_id);
  279. while (rtlhal->h2c_setinprogress) {
  280. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  281. flag);
  282. h2c_waitcounter++;
  283. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  284. "Wait 100 us (%d times)...\n",
  285. h2c_waitcounter);
  286. udelay(100);
  287. if (h2c_waitcounter > 1000)
  288. return;
  289. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  290. flag);
  291. }
  292. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  293. } else {
  294. rtlhal->h2c_setinprogress = true;
  295. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  296. break;
  297. }
  298. }
  299. while (!bwrite_sucess) {
  300. wait_writeh2c_limmit--;
  301. if (wait_writeh2c_limmit == 0) {
  302. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  303. "Write H2C fail because no trigger for FW INT!\n");
  304. break;
  305. }
  306. boxnum = rtlhal->last_hmeboxnum;
  307. switch (boxnum) {
  308. case 0:
  309. box_reg = REG_HMEBOX_0;
  310. box_extreg = REG_HMEBOX_EXT_0;
  311. break;
  312. case 1:
  313. box_reg = REG_HMEBOX_1;
  314. box_extreg = REG_HMEBOX_EXT_1;
  315. break;
  316. case 2:
  317. box_reg = REG_HMEBOX_2;
  318. box_extreg = REG_HMEBOX_EXT_2;
  319. break;
  320. case 3:
  321. box_reg = REG_HMEBOX_3;
  322. box_extreg = REG_HMEBOX_EXT_3;
  323. break;
  324. default:
  325. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  326. "switch case not processed\n");
  327. break;
  328. }
  329. isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
  330. while (!isfw_read) {
  331. wait_h2c_limmit--;
  332. if (wait_h2c_limmit == 0) {
  333. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  334. "Waiting too long for FW read clear HMEBox(%d)!\n",
  335. boxnum);
  336. break;
  337. }
  338. udelay(10);
  339. isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
  340. u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
  341. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  342. "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n",
  343. boxnum, u1b_tmp);
  344. }
  345. if (!isfw_read) {
  346. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  347. "Write H2C register BOX[%d] fail!!!!! Fw do not read\n",
  348. boxnum);
  349. break;
  350. }
  351. memset(boxcontent, 0, sizeof(boxcontent));
  352. memset(boxextcontent, 0, sizeof(boxextcontent));
  353. boxcontent[0] = element_id;
  354. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  355. "Write element_id box_reg(%4x) = %2x\n",
  356. box_reg, element_id);
  357. switch (cmd_len) {
  358. case 1:
  359. boxcontent[0] &= ~(BIT(7));
  360. memcpy((u8 *) (boxcontent) + 1,
  361. p_cmdbuffer, 1);
  362. for (idx = 0; idx < 4; idx++) {
  363. rtl_write_byte(rtlpriv, box_reg + idx,
  364. boxcontent[idx]);
  365. }
  366. break;
  367. case 2:
  368. boxcontent[0] &= ~(BIT(7));
  369. memcpy((u8 *) (boxcontent) + 1,
  370. p_cmdbuffer, 2);
  371. for (idx = 0; idx < 4; idx++) {
  372. rtl_write_byte(rtlpriv, box_reg + idx,
  373. boxcontent[idx]);
  374. }
  375. break;
  376. case 3:
  377. boxcontent[0] &= ~(BIT(7));
  378. memcpy((u8 *) (boxcontent) + 1,
  379. p_cmdbuffer, 3);
  380. for (idx = 0; idx < 4; idx++) {
  381. rtl_write_byte(rtlpriv, box_reg + idx,
  382. boxcontent[idx]);
  383. }
  384. break;
  385. case 4:
  386. boxcontent[0] |= (BIT(7));
  387. memcpy((u8 *) (boxextcontent),
  388. p_cmdbuffer, 2);
  389. memcpy((u8 *) (boxcontent) + 1,
  390. p_cmdbuffer + 2, 2);
  391. for (idx = 0; idx < 2; idx++) {
  392. rtl_write_byte(rtlpriv, box_extreg + idx,
  393. boxextcontent[idx]);
  394. }
  395. for (idx = 0; idx < 4; idx++) {
  396. rtl_write_byte(rtlpriv, box_reg + idx,
  397. boxcontent[idx]);
  398. }
  399. break;
  400. case 5:
  401. boxcontent[0] |= (BIT(7));
  402. memcpy((u8 *) (boxextcontent),
  403. p_cmdbuffer, 2);
  404. memcpy((u8 *) (boxcontent) + 1,
  405. p_cmdbuffer + 2, 3);
  406. for (idx = 0; idx < 2; idx++) {
  407. rtl_write_byte(rtlpriv, box_extreg + idx,
  408. boxextcontent[idx]);
  409. }
  410. for (idx = 0; idx < 4; idx++) {
  411. rtl_write_byte(rtlpriv, box_reg + idx,
  412. boxcontent[idx]);
  413. }
  414. break;
  415. default:
  416. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  417. "switch case not processed\n");
  418. break;
  419. }
  420. bwrite_sucess = true;
  421. rtlhal->last_hmeboxnum = boxnum + 1;
  422. if (rtlhal->last_hmeboxnum == 4)
  423. rtlhal->last_hmeboxnum = 0;
  424. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  425. "pHalData->last_hmeboxnum = %d\n",
  426. rtlhal->last_hmeboxnum);
  427. }
  428. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  429. rtlhal->h2c_setinprogress = false;
  430. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  431. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  432. }
  433. void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
  434. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  435. {
  436. u32 tmp_cmdbuf[2];
  437. memset(tmp_cmdbuf, 0, 8);
  438. memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
  439. _rtl92c_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
  440. return;
  441. }
  442. EXPORT_SYMBOL(rtl92c_fill_h2c_cmd);
  443. void rtl92c_firmware_selfreset(struct ieee80211_hw *hw)
  444. {
  445. u8 u1b_tmp;
  446. u8 delay = 100;
  447. struct rtl_priv *rtlpriv = rtl_priv(hw);
  448. rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
  449. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  450. while (u1b_tmp & BIT(2)) {
  451. delay--;
  452. if (delay == 0) {
  453. RT_ASSERT(false, "8051 reset fail\n");
  454. break;
  455. }
  456. udelay(50);
  457. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  458. }
  459. }
  460. EXPORT_SYMBOL(rtl92c_firmware_selfreset);
  461. void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  462. {
  463. struct rtl_priv *rtlpriv = rtl_priv(hw);
  464. u8 u1_h2c_set_pwrmode[3] = {0};
  465. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  466. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
  467. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
  468. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 1);
  469. SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
  470. ppsc->reg_max_lps_awakeintvl);
  471. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  472. "rtl92c_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode",
  473. u1_h2c_set_pwrmode, 3);
  474. rtl92c_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
  475. }
  476. EXPORT_SYMBOL(rtl92c_set_fw_pwrmode_cmd);
  477. static bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
  478. struct sk_buff *skb)
  479. {
  480. struct rtl_priv *rtlpriv = rtl_priv(hw);
  481. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  482. struct rtl8192_tx_ring *ring;
  483. struct rtl_tx_desc *pdesc;
  484. unsigned long flags;
  485. struct sk_buff *pskb = NULL;
  486. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  487. pskb = __skb_dequeue(&ring->queue);
  488. if (pskb)
  489. kfree_skb(pskb);
  490. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  491. pdesc = &ring->desc[0];
  492. rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
  493. __skb_queue_tail(&ring->queue, skb);
  494. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  495. rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
  496. return true;
  497. }
  498. #define BEACON_PG 0 /*->1*/
  499. #define PSPOLL_PG 2
  500. #define NULL_PG 3
  501. #define PROBERSP_PG 4 /*->5*/
  502. #define TOTAL_RESERVED_PKT_LEN 768
  503. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  504. /* page 0 beacon */
  505. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  506. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  507. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  508. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  509. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  510. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  511. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  512. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  513. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  514. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  515. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  516. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  517. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  518. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  519. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  520. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  521. /* page 1 beacon */
  522. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  523. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  524. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  525. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  526. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  527. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  528. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  529. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  530. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  531. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  532. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  533. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  534. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  535. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  536. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  537. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  538. /* page 2 ps-poll */
  539. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  540. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  541. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  542. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  543. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  544. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  545. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  546. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  547. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  548. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  549. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  550. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  551. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  552. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  553. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  554. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  555. /* page 3 null */
  556. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  557. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  558. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  559. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  560. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  561. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  562. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  563. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  564. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  565. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  566. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  567. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  568. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  569. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  570. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  571. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  572. /* page 4 probe_resp */
  573. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  574. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  575. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  576. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  577. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  578. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  579. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  580. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  581. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  582. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  583. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  584. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  585. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  586. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  587. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  588. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  589. /* page 5 probe_resp */
  590. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  591. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  592. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  593. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  594. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  595. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  596. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  597. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  598. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  599. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  600. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  601. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  602. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  603. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  604. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  605. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  606. };
  607. void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
  608. {
  609. struct rtl_priv *rtlpriv = rtl_priv(hw);
  610. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  611. struct sk_buff *skb = NULL;
  612. u32 totalpacketlen;
  613. bool rtstatus;
  614. u8 u1RsvdPageLoc[3] = {0};
  615. bool dlok = false;
  616. u8 *beacon;
  617. u8 *pspoll;
  618. u8 *nullfunc;
  619. u8 *probersp;
  620. /*---------------------------------------------------------
  621. (1) beacon
  622. ---------------------------------------------------------*/
  623. beacon = &reserved_page_packet[BEACON_PG * 128];
  624. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  625. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  626. /*-------------------------------------------------------
  627. (2) ps-poll
  628. --------------------------------------------------------*/
  629. pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  630. SET_80211_PS_POLL_AID(pspoll, (mac->assoc_id | 0xc000));
  631. SET_80211_PS_POLL_BSSID(pspoll, mac->bssid);
  632. SET_80211_PS_POLL_TA(pspoll, mac->mac_addr);
  633. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
  634. /*--------------------------------------------------------
  635. (3) null data
  636. ---------------------------------------------------------*/
  637. nullfunc = &reserved_page_packet[NULL_PG * 128];
  638. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  639. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  640. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  641. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
  642. /*---------------------------------------------------------
  643. (4) probe response
  644. ----------------------------------------------------------*/
  645. probersp = &reserved_page_packet[PROBERSP_PG * 128];
  646. SET_80211_HDR_ADDRESS1(probersp, mac->bssid);
  647. SET_80211_HDR_ADDRESS2(probersp, mac->mac_addr);
  648. SET_80211_HDR_ADDRESS3(probersp, mac->bssid);
  649. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
  650. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  651. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  652. "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL",
  653. &reserved_page_packet[0], totalpacketlen);
  654. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  655. "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL",
  656. u1RsvdPageLoc, 3);
  657. skb = dev_alloc_skb(totalpacketlen);
  658. if (!skb)
  659. return;
  660. memcpy((u8 *) skb_put(skb, totalpacketlen),
  661. &reserved_page_packet, totalpacketlen);
  662. rtstatus = _rtl92c_cmd_send_packet(hw, skb);
  663. if (rtstatus)
  664. dlok = true;
  665. if (dlok) {
  666. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  667. "Set RSVD page location to Fw\n");
  668. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  669. "H2C_RSVDPAGE", u1RsvdPageLoc, 3);
  670. rtl92c_fill_h2c_cmd(hw, H2C_RSVDPAGE,
  671. sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
  672. } else
  673. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  674. "Set RSVD page location to Fw FAIL!!!!!!\n");
  675. }
  676. EXPORT_SYMBOL(rtl92c_set_fw_rsvdpagepkt);
  677. void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  678. {
  679. u8 u1_joinbssrpt_parm[1] = {0};
  680. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  681. rtl92c_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  682. }
  683. EXPORT_SYMBOL(rtl92c_set_fw_joinbss_report_cmd);