clock-s3c2416.c 4.0 KB

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  1. /* linux/arch/arm/mach-s3c2416/clock.c
  2. *
  3. * Copyright (c) 2010 Simtec Electronics
  4. * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
  5. *
  6. * S3C2416 Clock control support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/clk.h>
  15. #include <plat/s3c2416.h>
  16. #include <plat/clock.h>
  17. #include <plat/clock-clksrc.h>
  18. #include <plat/cpu.h>
  19. #include <plat/cpu-freq.h>
  20. #include <plat/pll.h>
  21. #include <asm/mach/map.h>
  22. #include <mach/regs-clock.h>
  23. #include <mach/regs-s3c2443-clock.h>
  24. /* armdiv
  25. *
  26. * this clock is sourced from msysclk and can have a number of
  27. * divider values applied to it to then be fed into armclk.
  28. * The real clock definition is done in s3c2443-clock.c,
  29. * only the armdiv divisor table must be defined here.
  30. */
  31. static unsigned int armdiv[8] = {
  32. [0] = 1,
  33. [1] = 2,
  34. [2] = 3,
  35. [3] = 4,
  36. [5] = 6,
  37. [7] = 8,
  38. };
  39. static struct clksrc_clk hsspi_eplldiv = {
  40. .clk = {
  41. .name = "hsspi-eplldiv",
  42. .parent = &clk_esysclk.clk,
  43. .ctrlbit = (1 << 14),
  44. .enable = s3c2443_clkcon_enable_s,
  45. },
  46. .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
  47. };
  48. static struct clk *hsspi_sources[] = {
  49. [0] = &hsspi_eplldiv.clk,
  50. [1] = NULL, /* to fix */
  51. };
  52. static struct clksrc_clk hsspi_mux = {
  53. .clk = {
  54. .name = "hsspi-if",
  55. },
  56. .sources = &(struct clksrc_sources) {
  57. .sources = hsspi_sources,
  58. .nr_sources = ARRAY_SIZE(hsspi_sources),
  59. },
  60. .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
  61. };
  62. static struct clksrc_clk hsmmc_div[] = {
  63. [0] = {
  64. .clk = {
  65. .name = "hsmmc-div",
  66. .devname = "s3c-sdhci.0",
  67. .parent = &clk_esysclk.clk,
  68. },
  69. .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
  70. },
  71. [1] = {
  72. .clk = {
  73. .name = "hsmmc-div",
  74. .devname = "s3c-sdhci.1",
  75. .parent = &clk_esysclk.clk,
  76. },
  77. .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
  78. },
  79. };
  80. static struct clksrc_clk hsmmc_mux0 = {
  81. .clk = {
  82. .name = "hsmmc-if",
  83. .devname = "s3c-sdhci.0",
  84. .ctrlbit = (1 << 6),
  85. .enable = s3c2443_clkcon_enable_s,
  86. },
  87. .sources = &(struct clksrc_sources) {
  88. .nr_sources = 2,
  89. .sources = (struct clk * []) {
  90. [0] = &hsmmc_div[0].clk,
  91. [1] = NULL, /* to fix */
  92. },
  93. },
  94. .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
  95. };
  96. static struct clksrc_clk hsmmc_mux1 = {
  97. .clk = {
  98. .name = "hsmmc-if",
  99. .devname = "s3c-sdhci.1",
  100. .ctrlbit = (1 << 12),
  101. .enable = s3c2443_clkcon_enable_s,
  102. },
  103. .sources = &(struct clksrc_sources) {
  104. .nr_sources = 2,
  105. .sources = (struct clk * []) {
  106. [0] = &hsmmc_div[1].clk,
  107. [1] = NULL, /* to fix */
  108. },
  109. },
  110. .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
  111. };
  112. static struct clk hsmmc0_clk = {
  113. .name = "hsmmc",
  114. .devname = "s3c-sdhci.0",
  115. .parent = &clk_h,
  116. .enable = s3c2443_clkcon_enable_h,
  117. .ctrlbit = S3C2416_HCLKCON_HSMMC0,
  118. };
  119. static struct clksrc_clk *clksrcs[] __initdata = {
  120. &hsspi_eplldiv,
  121. &hsspi_mux,
  122. &hsmmc_div[0],
  123. &hsmmc_div[1],
  124. &hsmmc_mux0,
  125. &hsmmc_mux1,
  126. };
  127. static struct clk_lookup s3c2416_clk_lookup[] = {
  128. CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
  129. CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
  130. CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
  131. };
  132. void __init s3c2416_init_clocks(int xtal)
  133. {
  134. u32 epllcon = __raw_readl(S3C2443_EPLLCON);
  135. u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
  136. int ptr;
  137. /* s3c2416 EPLL compatible with s3c64xx */
  138. clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
  139. clk_epll.parent = &clk_epllref.clk;
  140. s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
  141. armdiv, ARRAY_SIZE(armdiv),
  142. S3C2416_CLKDIV0_ARMDIV_MASK);
  143. for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
  144. s3c_register_clksrc(clksrcs[ptr], 1);
  145. s3c24xx_register_clock(&hsmmc0_clk);
  146. clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
  147. s3c_pwmclk_init();
  148. }