bm1366.md 1.9 KB
BM1366
Prelude
Many registers described below are common with other BM13xx chips. Here we focus mainly on BM1366 as this register map has been reverse engineered from the 'bmminer' of S19XP-Hydro original Firmware from Bitmain.
Registers Map
Core Registers Map
Communication Protocol
Set Baudrate
In order to get a higher hash rate, we need to increase the communication Baudrate because at 115200bps (default baudrate) a Send Job Command with 4 midstate would take 15.2ms which could be longer than the time the full chain would take to Hash the complete Nonce space of the previous job.
BaudRate = fBase / ((BT8D + 1) * 8)
At chip reset, in Fast UART Configuration Register :
So the default BaudRate = fCLKI / ((BT8D + 1) * 8) = 115740 bps with reset values (0.47% error with target 115200 bps).
This is possible up to 3.125Mbps BaudRate with BT8D = 0.
For higher baud rates, here are the necessary steps (numeric example below is for 6.25 Mbps BaudRate):
- enabling and configuring PLL1 using PLL1 Parameter for example writing 0xC0700111 will result of a PLL3 with frequency equal to
fPLL3 = fCLKI * FBDIV / (REFDIV * POSTDIV1 * POSTDIV2) = 25MHz*112/(1*1*1) = 2.8 GHz - setting PLL1_DIV4 in Fast UART Configuration for example writing 0xTBD give a
PLL1_DIV4 = 6 - setting BCLK_SEL to 1
fBase = fPLL1 / (PLL1_DIV4 + 1) = 2.8 GHz / (6+1) = 400 MHz - setting BT8D to 7
BaudRate = fBase / ((BT8D + 1)*8) = 400 MHz / ((7+1)*8) = 6.25 MBps