asix-sigma.h 4.7 KB

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  1. /*
  2. * This file is part of the libsigrok project.
  3. *
  4. * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
  5. * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
  6. * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
  7. *
  8. * This program is free software: you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation, either version 3 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
  22. #define LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
  23. #define LOG_PREFIX "asix-sigma"
  24. enum sigma_write_register {
  25. WRITE_CLOCK_SELECT = 0,
  26. WRITE_TRIGGER_SELECT0 = 1,
  27. WRITE_TRIGGER_SELECT1 = 2,
  28. WRITE_MODE = 3,
  29. WRITE_MEMROW = 4,
  30. WRITE_POST_TRIGGER = 5,
  31. WRITE_TRIGGER_OPTION = 6,
  32. WRITE_PIN_VIEW = 7,
  33. WRITE_TEST = 15,
  34. };
  35. enum sigma_read_register {
  36. READ_ID = 0,
  37. READ_TRIGGER_POS_LOW = 1,
  38. READ_TRIGGER_POS_HIGH = 2,
  39. READ_TRIGGER_POS_UP = 3,
  40. READ_STOP_POS_LOW = 4,
  41. READ_STOP_POS_HIGH = 5,
  42. READ_STOP_POS_UP = 6,
  43. READ_MODE = 7,
  44. READ_PIN_CHANGE_LOW = 8,
  45. READ_PIN_CHANGE_HIGH = 9,
  46. READ_BLOCK_LAST_TS_LOW = 10,
  47. READ_BLOCK_LAST_TS_HIGH = 11,
  48. READ_PIN_VIEW = 12,
  49. READ_TEST = 15,
  50. };
  51. #define REG_ADDR_LOW (0x0 << 4)
  52. #define REG_ADDR_HIGH (0x1 << 4)
  53. #define REG_DATA_LOW (0x2 << 4)
  54. #define REG_DATA_HIGH_WRITE (0x3 << 4)
  55. #define REG_READ_ADDR (0x4 << 4)
  56. #define REG_DRAM_WAIT_ACK (0x5 << 4)
  57. /* Bit (1 << 4) can be low or high (double buffer / cache) */
  58. #define REG_DRAM_BLOCK (0x6 << 4)
  59. #define REG_DRAM_BLOCK_BEGIN (0x8 << 4)
  60. #define REG_DRAM_BLOCK_DATA (0xa << 4)
  61. #define LEDSEL0 6
  62. #define LEDSEL1 7
  63. #define NEXT_REG 1
  64. #define EVENTS_PER_CLUSTER 7
  65. #define CHUNK_SIZE 1024
  66. /*
  67. * The entire ASIX Sigma DRAM is an array of struct sigma_dram_line[1024];
  68. */
  69. /* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
  70. struct sigma_dram_cluster {
  71. uint8_t timestamp_lo;
  72. uint8_t timestamp_hi;
  73. struct {
  74. uint8_t sample_hi;
  75. uint8_t sample_lo;
  76. } samples[7];
  77. };
  78. /* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
  79. struct sigma_dram_line {
  80. struct sigma_dram_cluster cluster[64];
  81. };
  82. struct clockselect_50 {
  83. uint8_t async;
  84. uint8_t fraction;
  85. uint16_t disabled_channels;
  86. };
  87. /* The effect of all these are still a bit unclear. */
  88. struct triggerinout {
  89. uint8_t trgout_resistor_enable : 1;
  90. uint8_t trgout_resistor_pullup : 1;
  91. uint8_t reserved1 : 1;
  92. uint8_t trgout_bytrigger : 1;
  93. uint8_t trgout_byevent : 1;
  94. uint8_t trgout_bytriggerin : 1;
  95. uint8_t reserved2 : 2;
  96. /* Should be set same as the first two */
  97. uint8_t trgout_resistor_enable2 : 1;
  98. uint8_t trgout_resistor_pullup2 : 1;
  99. uint8_t reserved3 : 1;
  100. uint8_t trgout_long : 1;
  101. uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
  102. uint8_t trgin_negate : 1;
  103. uint8_t trgout_enable : 1;
  104. uint8_t trgin_enable : 1;
  105. };
  106. struct triggerlut {
  107. /* The actual LUTs. */
  108. uint16_t m0d[4], m1d[4], m2d[4];
  109. uint16_t m3, m3s, m4;
  110. /* Paramters should be sent as a single register write. */
  111. struct {
  112. uint8_t selc : 2;
  113. uint8_t selpresc : 6;
  114. uint8_t selinc : 2;
  115. uint8_t selres : 2;
  116. uint8_t sela : 2;
  117. uint8_t selb : 2;
  118. uint16_t cmpb;
  119. uint16_t cmpa;
  120. } params;
  121. };
  122. /* Trigger configuration */
  123. struct sigma_trigger {
  124. /* Only two channels can be used in mask. */
  125. uint16_t risingmask;
  126. uint16_t fallingmask;
  127. /* Simple trigger support (<= 50 MHz). */
  128. uint16_t simplemask;
  129. uint16_t simplevalue;
  130. /* TODO: Advanced trigger support (boolean expressions). */
  131. };
  132. /* Events for trigger operation. */
  133. enum triggerop {
  134. OP_LEVEL = 1,
  135. OP_NOT,
  136. OP_RISE,
  137. OP_FALL,
  138. OP_RISEFALL,
  139. OP_NOTRISE,
  140. OP_NOTFALL,
  141. OP_NOTRISEFALL,
  142. };
  143. /* Logical functions for trigger operation. */
  144. enum triggerfunc {
  145. FUNC_AND = 1,
  146. FUNC_NAND,
  147. FUNC_OR,
  148. FUNC_NOR,
  149. FUNC_XOR,
  150. FUNC_NXOR,
  151. };
  152. struct sigma_state {
  153. enum {
  154. SIGMA_UNINITIALIZED = 0,
  155. SIGMA_IDLE,
  156. SIGMA_CAPTURE,
  157. SIGMA_DOWNLOAD,
  158. } state;
  159. uint16_t lastts;
  160. uint16_t lastsample;
  161. };
  162. /* Private, per-device-instance driver context. */
  163. struct dev_context {
  164. struct ftdi_context ftdic;
  165. uint64_t cur_samplerate;
  166. uint64_t period_ps;
  167. uint64_t limit_msec;
  168. struct timeval start_tv;
  169. int cur_firmware;
  170. int num_channels;
  171. int cur_channels;
  172. int samples_per_event;
  173. int capture_ratio;
  174. struct sigma_trigger trigger;
  175. int use_triggers;
  176. struct sigma_state state;
  177. void *cb_data;
  178. };
  179. #endif