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CHIP-linux-l...
/
drivers
/
video
/
fbdev
/
carminefb.h

carminefb.h 2.2 KB
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  1. #ifndef CARMINE_CARMINE_H
    2. 

  2. #define CARMINE_CARMINE_H
    3. 

  3. 

  4. #define CARMINE_MEMORY_BAR	2
    5. 

  5. #define CARMINE_CONFIG_BAR	3
    6. 

  6. 

  7. #define MAX_DISPLAY	2
    8. 

  8. #define CARMINE_DISPLAY_MEM	(800 * 600 * 4)
    9. 

  9. #define CARMINE_TOTAL_DIPLAY_MEM	(CARMINE_DISPLAY_MEM * MAX_DISPLAY)
    10. 

  10. 

  11. #define CARMINE_USE_DISPLAY0	(1 << 0)
    12. 

  12. #define CARMINE_USE_DISPLAY1	(1 << 1)
    13. 

  13. 

  14. /*
    15. 

  15.  * This values work on the eval card. Custom boards may use different timings,
    16. 

  16.  * here an example :)
    17. 

  17.  */
    18. 

  18. 

  19. /* DRAM initialization values */
    20. 

  20. #ifdef CONFIG_FB_CARMINE_DRAM_EVAL
    21. 

  21. 

  22. #define CARMINE_DFLT_IP_CLOCK_ENABLE		(0x03ff)
    23. 

  23. #define CARMINE_DFLT_IP_DCTL_ADD		(0x05c3)
    24. 

  24. #define CARMINE_DFLT_IP_DCTL_MODE		(0x0121)
    25. 

  25. #define CARMINE_DFLT_IP_DCTL_EMODE		(0x8000)
    26. 

  26. #define CARMINE_DFLT_IP_DCTL_SET_TIME1		(0x4749)
    27. 

  27. #define CARMINE_DFLT_IP_DCTL_SET_TIME2		(0x2a22)
    28. 

  28. #define CARMINE_DFLT_IP_DCTL_REFRESH		(0x0042)
    29. 

  29. #define CARMINE_DFLT_IP_DCTL_STATES		(0x0003)
    30. 

  30. #define CARMINE_DFLT_IP_DCTL_RESERVE0		(0x0020)
    31. 

  31. #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH		(0x000f)
    32. 

  32. #define CARMINE_DFLT_IP_DCTL_RESERVE2		(0x0000)
    33. 

  33. #define CARMINE_DFLT_IP_DCTL_DDRIF1		(0x6646)
    34. 

  34. #define CARMINE_DFLT_IP_DCTL_DDRIF2		(0x0055)
    35. 

  35. #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST	(0x0021)
    36. 

  36. #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST	(0x0002)
    37. 

  37. #define CARMINE_DFLT_IP_DCTL_IO_CONT0		(0x0555)
    38. 

  38. #define CARMINE_DFLT_IP_DCTL_IO_CONT1		(0x0555)
    39. 

  39. #define CARMINE_DCTL_DLL_RESET			(1)
    40. 

  40. #endif
    41. 

  41. 

  42. #ifdef CONFIG_CARMINE_DRAM_CUSTOM
    43. 

  43. 

  44. #define CARMINE_DFLT_IP_CLOCK_ENABLE		(0x03ff)
    45. 

  45. #define CARMINE_DFLT_IP_DCTL_ADD		(0x03b2)
    46. 

  46. #define CARMINE_DFLT_IP_DCTL_MODE		(0x0161)
    47. 

  47. #define CARMINE_DFLT_IP_DCTL_EMODE		(0x8000)
    48. 

  48. #define CARMINE_DFLT_IP_DCTL_SET_TIME1		(0x2628)
    49. 

  49. #define CARMINE_DFLT_IP_DCTL_SET_TIME2		(0x1a09)
    50. 

  50. #define CARMINE_DFLT_IP_DCTL_REFRESH		(0x00fe)
    51. 

  51. #define CARMINE_DFLT_IP_DCTL_STATES		(0x0003)
    52. 

  52. #define CARMINE_DFLT_IP_DCTL_RESERVE0		(0x0020)
    53. 

  53. #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH		(0x000f)
    54. 

  54. #define CARMINE_DFLT_IP_DCTL_RESERVE2		(0x0000)
    55. 

  55. #define CARMINE_DFLT_IP_DCTL_DDRIF1		(0x0646)
    56. 

  56. #define CARMINE_DFLT_IP_DCTL_DDRIF2		(0x55aa)
    57. 

  57. #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST	(0x0061)
    58. 

  58. #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST	(0x0002)
    59. 

  59. #define CARMINE_DFLT_IP_DCTL_IO_CONT0		(0x0555)
    60. 

  60. #define CARMINE_DFLT_IP_DCTL_IO_CONT1		(0x0555)
    61. 

  61. #define CARMINE_DCTL_DLL_RESET			(1)
    62. 

  62. #endif
    63. 

  63. 

  64. #endif
    65. 

  65.