bfin_adv7393fb.h 8.6 KB

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  1. /*
  2. * Frame buffer driver for ADV7393/2 video encoder
  3. *
  4. * Copyright 2006-2009 Analog Devices Inc.
  5. * Licensed under the GPL-2 or late.
  6. */
  7. #ifndef __BFIN_ADV7393FB_H__
  8. #define __BFIN_ADV7393FB_H__
  9. #define BFIN_LCD_NBR_PALETTE_ENTRIES 256
  10. #ifdef CONFIG_NTSC
  11. # define VMODE 0
  12. #endif
  13. #ifdef CONFIG_PAL
  14. # define VMODE 1
  15. #endif
  16. #ifdef CONFIG_NTSC_640x480
  17. # define VMODE 2
  18. #endif
  19. #ifdef CONFIG_PAL_640x480
  20. # define VMODE 3
  21. #endif
  22. #ifdef CONFIG_NTSC_YCBCR
  23. # define VMODE 4
  24. #endif
  25. #ifdef CONFIG_PAL_YCBCR
  26. # define VMODE 5
  27. #endif
  28. #ifndef VMODE
  29. # define VMODE 1
  30. #endif
  31. #ifdef CONFIG_ADV7393_2XMEM
  32. # define VMEM 2
  33. #else
  34. # define VMEM 1
  35. #endif
  36. #if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
  37. # define DMA_CFG_VAL 0x7935 /* Set Sync Bit */
  38. # define VB_DUMMY_MEMORY_SOURCE L1_DATA_B_START
  39. #else
  40. # define DMA_CFG_VAL 0x7915
  41. # define VB_DUMMY_MEMORY_SOURCE BOOT_ROM_START
  42. #endif
  43. enum {
  44. DESTRUCT,
  45. BUILD,
  46. };
  47. enum {
  48. POWER_ON,
  49. POWER_DOWN,
  50. BLANK_ON,
  51. BLANK_OFF,
  52. };
  53. #define DRIVER_NAME "bfin-adv7393"
  54. struct adv7393fb_modes {
  55. const s8 name[25]; /* Full name */
  56. u16 xres; /* Active Horizonzal Pixels */
  57. u16 yres; /* Active Vertical Pixels */
  58. u16 bpp;
  59. u16 vmode;
  60. u16 a_lines; /* Active Lines per Field */
  61. u16 vb1_lines; /* Vertical Blanking Field 1 Lines */
  62. u16 vb2_lines; /* Vertical Blanking Field 2 Lines */
  63. u16 tot_lines; /* Total Lines per Frame */
  64. u16 boeft_blank; /* Before Odd/Even Field Transition No. of Blank Pixels */
  65. u16 aoeft_blank; /* After Odd/Even Field Transition No. of Blank Pixels */
  66. const s8 *adv7393_i2c_initd;
  67. u16 adv7393_i2c_initd_len;
  68. };
  69. static const u8 init_NTSC_TESTPATTERN[] = {
  70. 0x00, 0x1E, /* Power up all DACs and PLL */
  71. 0x01, 0x00, /* SD-Only Mode */
  72. 0x80, 0x10, /* SSAF Luma Filter Enabled, NTSC Mode */
  73. 0x82, 0xCB, /* Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS/YC output */
  74. 0x84, 0x40, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
  75. };
  76. static const u8 init_NTSC[] = {
  77. 0x00, 0x1E, /* Power up all DACs and PLL */
  78. 0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */
  79. 0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */
  80. 0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */
  81. 0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */
  82. 0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */
  83. 0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */
  84. 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
  85. 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
  86. 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
  87. 0x8F, 0x21, /* NTSC Subcarrier Frequency */
  88. 0x01, 0x00, /* SD-Only Mode */
  89. 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
  90. 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
  91. 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
  92. 0x86, 0x82,
  93. 0x8B, 0x11,
  94. 0x88, 0x20,
  95. 0x8A, 0x0d,
  96. };
  97. static const u8 init_PAL[] = {
  98. 0x00, 0x1E, /* Power up all DACs and PLL */
  99. 0xC3, 0x26, /* Program RGB->YCrCb Color Space conversion matrix */
  100. 0xC5, 0x12, /* Program RGB->YCrCb Color Space conversion matrix */
  101. 0xC2, 0x4A, /* Program RGB->YCrCb Color Space conversion matrix */
  102. 0xC6, 0x5E, /* Program RGB->YCrCb Color Space conversion matrix */
  103. 0xBD, 0x19, /* Program RGB->YCrCb Color Space conversion matrix */
  104. 0xBF, 0x42, /* Program RGB->YCrCb Color Space conversion matrix */
  105. 0x8C, 0xCB, /* PAL Subcarrier Frequency */
  106. 0x8D, 0x8A, /* PAL Subcarrier Frequency */
  107. 0x8E, 0x09, /* PAL Subcarrier Frequency */
  108. 0x8F, 0x2A, /* PAL Subcarrier Frequency */
  109. 0x01, 0x00, /* SD-Only Mode */
  110. 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
  111. 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
  112. 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
  113. 0x86, 0x82,
  114. 0x8B, 0x11,
  115. 0x88, 0x20,
  116. 0x8A, 0x0d,
  117. };
  118. static const u8 init_NTSC_YCbCr[] = {
  119. 0x00, 0x1E, /* Power up all DACs and PLL */
  120. 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
  121. 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
  122. 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
  123. 0x8F, 0x21, /* NTSC Subcarrier Frequency */
  124. 0x01, 0x00, /* SD-Only Mode */
  125. 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
  126. 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
  127. 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
  128. 0x86, 0x82,
  129. 0x8B, 0x11,
  130. 0x88, 0x08,
  131. 0x8A, 0x0d,
  132. };
  133. static const u8 init_PAL_YCbCr[] = {
  134. 0x00, 0x1E, /* Power up all DACs and PLL */
  135. 0x8C, 0xCB, /* PAL Subcarrier Frequency */
  136. 0x8D, 0x8A, /* PAL Subcarrier Frequency */
  137. 0x8E, 0x09, /* PAL Subcarrier Frequency */
  138. 0x8F, 0x2A, /* PAL Subcarrier Frequency */
  139. 0x01, 0x00, /* SD-Only Mode */
  140. 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
  141. 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
  142. 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
  143. 0x86, 0x82,
  144. 0x8B, 0x11,
  145. 0x88, 0x08,
  146. 0x8A, 0x0d,
  147. };
  148. static struct adv7393fb_modes known_modes[] = {
  149. /* NTSC 720x480 CRT */
  150. {
  151. .name = "NTSC 720x480",
  152. .xres = 720,
  153. .yres = 480,
  154. .bpp = 16,
  155. .vmode = FB_VMODE_INTERLACED,
  156. .a_lines = 240,
  157. .vb1_lines = 22,
  158. .vb2_lines = 23,
  159. .tot_lines = 525,
  160. .boeft_blank = 16,
  161. .aoeft_blank = 122,
  162. .adv7393_i2c_initd = init_NTSC,
  163. .adv7393_i2c_initd_len = sizeof(init_NTSC)
  164. },
  165. /* PAL 720x480 CRT */
  166. {
  167. .name = "PAL 720x576",
  168. .xres = 720,
  169. .yres = 576,
  170. .bpp = 16,
  171. .vmode = FB_VMODE_INTERLACED,
  172. .a_lines = 288,
  173. .vb1_lines = 24,
  174. .vb2_lines = 25,
  175. .tot_lines = 625,
  176. .boeft_blank = 12,
  177. .aoeft_blank = 132,
  178. .adv7393_i2c_initd = init_PAL,
  179. .adv7393_i2c_initd_len = sizeof(init_PAL)
  180. },
  181. /* NTSC 640x480 CRT Experimental */
  182. {
  183. .name = "NTSC 640x480",
  184. .xres = 640,
  185. .yres = 480,
  186. .bpp = 16,
  187. .vmode = FB_VMODE_INTERLACED,
  188. .a_lines = 240,
  189. .vb1_lines = 22,
  190. .vb2_lines = 23,
  191. .tot_lines = 525,
  192. .boeft_blank = 16 + 40,
  193. .aoeft_blank = 122 + 40,
  194. .adv7393_i2c_initd = init_NTSC,
  195. .adv7393_i2c_initd_len = sizeof(init_NTSC)
  196. },
  197. /* PAL 640x480 CRT Experimental */
  198. {
  199. .name = "PAL 640x480",
  200. .xres = 640,
  201. .yres = 480,
  202. .bpp = 16,
  203. .vmode = FB_VMODE_INTERLACED,
  204. .a_lines = 288 - 20,
  205. .vb1_lines = 24 + 20,
  206. .vb2_lines = 25 + 20,
  207. .tot_lines = 625,
  208. .boeft_blank = 12 + 40,
  209. .aoeft_blank = 132 + 40,
  210. .adv7393_i2c_initd = init_PAL,
  211. .adv7393_i2c_initd_len = sizeof(init_PAL)
  212. },
  213. /* NTSC 720x480 YCbCR */
  214. {
  215. .name = "NTSC 720x480 YCbCR",
  216. .xres = 720,
  217. .yres = 480,
  218. .bpp = 16,
  219. .vmode = FB_VMODE_INTERLACED,
  220. .a_lines = 240,
  221. .vb1_lines = 22,
  222. .vb2_lines = 23,
  223. .tot_lines = 525,
  224. .boeft_blank = 16,
  225. .aoeft_blank = 122,
  226. .adv7393_i2c_initd = init_NTSC_YCbCr,
  227. .adv7393_i2c_initd_len = sizeof(init_NTSC_YCbCr)
  228. },
  229. /* PAL 720x480 CRT */
  230. {
  231. .name = "PAL 720x576 YCbCR",
  232. .xres = 720,
  233. .yres = 576,
  234. .bpp = 16,
  235. .vmode = FB_VMODE_INTERLACED,
  236. .a_lines = 288,
  237. .vb1_lines = 24,
  238. .vb2_lines = 25,
  239. .tot_lines = 625,
  240. .boeft_blank = 12,
  241. .aoeft_blank = 132,
  242. .adv7393_i2c_initd = init_PAL_YCbCr,
  243. .adv7393_i2c_initd_len = sizeof(init_PAL_YCbCr)
  244. }
  245. };
  246. struct adv7393fb_regs {
  247. };
  248. struct adv7393fb_device {
  249. struct fb_info info; /* FB driver info record */
  250. struct i2c_client *client;
  251. struct dmasg *descriptor_list_head;
  252. struct dmasg *vb1;
  253. struct dmasg *av1;
  254. struct dmasg *vb2;
  255. struct dmasg *av2;
  256. dma_addr_t dma_handle;
  257. struct fb_info bfin_adv7393_fb;
  258. struct adv7393fb_modes *modes;
  259. struct adv7393fb_regs *regs; /* Registers memory map */
  260. size_t regs_len;
  261. size_t fb_len;
  262. size_t line_len;
  263. u16 open;
  264. u16 *fb_mem; /* RGB Buffer */
  265. };
  266. #define to_adv7393fb_device(_info) \
  267. (_info ? container_of(_info, struct adv7393fb_device, info) : NULL);
  268. static int bfin_adv7393_fb_open(struct fb_info *info, int user);
  269. static int bfin_adv7393_fb_release(struct fb_info *info, int user);
  270. static int bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var,
  271. struct fb_info *info);
  272. static int bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var,
  273. struct fb_info *info);
  274. static int bfin_adv7393_fb_blank(int blank, struct fb_info *info);
  275. static void bfin_config_ppi(struct adv7393fb_device *fbdev);
  276. static int bfin_config_dma(struct adv7393fb_device *fbdev);
  277. static void bfin_disable_dma(void);
  278. static void bfin_enable_ppi(void);
  279. static void bfin_disable_ppi(void);
  280. static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value);
  281. static inline int adv7393_read(struct i2c_client *client, u8 reg);
  282. static int adv7393_write_block(struct i2c_client *client, const u8 *data,
  283. unsigned int len);
  284. int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
  285. static int bfin_adv7393_fb_setcolreg(u_int, u_int, u_int, u_int,
  286. u_int, struct fb_info *info);
  287. #endif