rockchip_thermal.c 18 KB

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  1. /*
  2. * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/reset.h>
  23. #include <linux/thermal.h>
  24. /**
  25. * If the temperature over a period of time High,
  26. * the resulting TSHUT gave CRU module,let it reset the entire chip,
  27. * or via GPIO give PMIC.
  28. */
  29. enum tshut_mode {
  30. TSHUT_MODE_CRU = 0,
  31. TSHUT_MODE_GPIO,
  32. };
  33. /**
  34. * the system Temperature Sensors tshut(tshut) polarity
  35. * the bit 8 is tshut polarity.
  36. * 0: low active, 1: high active
  37. */
  38. enum tshut_polarity {
  39. TSHUT_LOW_ACTIVE = 0,
  40. TSHUT_HIGH_ACTIVE,
  41. };
  42. /**
  43. * The system has three Temperature Sensors. channel 0 is reserved,
  44. * channel 1 is for CPU, and channel 2 is for GPU.
  45. */
  46. enum sensor_id {
  47. SENSOR_CPU = 1,
  48. SENSOR_GPU,
  49. };
  50. struct rockchip_tsadc_chip {
  51. /* The hardware-controlled tshut property */
  52. long tshut_temp;
  53. enum tshut_mode tshut_mode;
  54. enum tshut_polarity tshut_polarity;
  55. /* Chip-wide methods */
  56. void (*initialize)(void __iomem *reg, enum tshut_polarity p);
  57. void (*irq_ack)(void __iomem *reg);
  58. void (*control)(void __iomem *reg, bool on);
  59. /* Per-sensor methods */
  60. int (*get_temp)(int chn, void __iomem *reg, long *temp);
  61. void (*set_tshut_temp)(int chn, void __iomem *reg, long temp);
  62. void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
  63. };
  64. struct rockchip_thermal_sensor {
  65. struct rockchip_thermal_data *thermal;
  66. struct thermal_zone_device *tzd;
  67. enum sensor_id id;
  68. };
  69. #define NUM_SENSORS 2 /* Ignore unused sensor 0 */
  70. struct rockchip_thermal_data {
  71. const struct rockchip_tsadc_chip *chip;
  72. struct platform_device *pdev;
  73. struct reset_control *reset;
  74. struct rockchip_thermal_sensor sensors[NUM_SENSORS];
  75. struct clk *clk;
  76. struct clk *pclk;
  77. void __iomem *regs;
  78. long tshut_temp;
  79. enum tshut_mode tshut_mode;
  80. enum tshut_polarity tshut_polarity;
  81. };
  82. /* TSADC V2 Sensor info define: */
  83. #define TSADCV2_AUTO_CON 0x04
  84. #define TSADCV2_INT_EN 0x08
  85. #define TSADCV2_INT_PD 0x0c
  86. #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
  87. #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
  88. #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
  89. #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
  90. #define TSADCV2_AUTO_PERIOD 0x68
  91. #define TSADCV2_AUTO_PERIOD_HT 0x6c
  92. #define TSADCV2_AUTO_EN BIT(0)
  93. #define TSADCV2_AUTO_DISABLE ~BIT(0)
  94. #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
  95. #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
  96. #define TSADCV2_AUTO_TSHUT_POLARITY_LOW ~BIT(8)
  97. #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
  98. #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
  99. #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
  100. #define TSADCV2_INT_PD_CLEAR ~BIT(8)
  101. #define TSADCV2_DATA_MASK 0xfff
  102. #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
  103. #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
  104. #define TSADCV2_AUTO_PERIOD_TIME 250 /* msec */
  105. #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* msec */
  106. struct tsadc_table {
  107. unsigned long code;
  108. long temp;
  109. };
  110. static const struct tsadc_table v2_code_table[] = {
  111. {TSADCV2_DATA_MASK, -40000},
  112. {3800, -40000},
  113. {3792, -35000},
  114. {3783, -30000},
  115. {3774, -25000},
  116. {3765, -20000},
  117. {3756, -15000},
  118. {3747, -10000},
  119. {3737, -5000},
  120. {3728, 0},
  121. {3718, 5000},
  122. {3708, 10000},
  123. {3698, 15000},
  124. {3688, 20000},
  125. {3678, 25000},
  126. {3667, 30000},
  127. {3656, 35000},
  128. {3645, 40000},
  129. {3634, 45000},
  130. {3623, 50000},
  131. {3611, 55000},
  132. {3600, 60000},
  133. {3588, 65000},
  134. {3575, 70000},
  135. {3563, 75000},
  136. {3550, 80000},
  137. {3537, 85000},
  138. {3524, 90000},
  139. {3510, 95000},
  140. {3496, 100000},
  141. {3482, 105000},
  142. {3467, 110000},
  143. {3452, 115000},
  144. {3437, 120000},
  145. {3421, 125000},
  146. {0, 125000},
  147. };
  148. static u32 rk_tsadcv2_temp_to_code(long temp)
  149. {
  150. int high, low, mid;
  151. low = 0;
  152. high = ARRAY_SIZE(v2_code_table) - 1;
  153. mid = (high + low) / 2;
  154. if (temp < v2_code_table[low].temp || temp > v2_code_table[high].temp)
  155. return 0;
  156. while (low <= high) {
  157. if (temp == v2_code_table[mid].temp)
  158. return v2_code_table[mid].code;
  159. else if (temp < v2_code_table[mid].temp)
  160. high = mid - 1;
  161. else
  162. low = mid + 1;
  163. mid = (low + high) / 2;
  164. }
  165. return 0;
  166. }
  167. static long rk_tsadcv2_code_to_temp(u32 code)
  168. {
  169. unsigned int low = 0;
  170. unsigned int high = ARRAY_SIZE(v2_code_table) - 1;
  171. unsigned int mid = (low + high) / 2;
  172. unsigned int num;
  173. unsigned long denom;
  174. /* Invalid code, return -EAGAIN */
  175. if (code > TSADCV2_DATA_MASK)
  176. return -EAGAIN;
  177. while (low <= high && mid) {
  178. if (code >= v2_code_table[mid].code &&
  179. code < v2_code_table[mid - 1].code)
  180. break;
  181. else if (code < v2_code_table[mid].code)
  182. low = mid + 1;
  183. else
  184. high = mid - 1;
  185. mid = (low + high) / 2;
  186. }
  187. /*
  188. * The 5C granularity provided by the table is too much. Let's
  189. * assume that the relationship between sensor readings and
  190. * temperature between 2 table entries is linear and interpolate
  191. * to produce less granular result.
  192. */
  193. num = v2_code_table[mid].temp - v2_code_table[mid - 1].temp;
  194. num *= v2_code_table[mid - 1].code - code;
  195. denom = v2_code_table[mid - 1].code - v2_code_table[mid].code;
  196. return v2_code_table[mid - 1].temp + (num / denom);
  197. }
  198. /**
  199. * rk_tsadcv2_initialize - initialize TASDC Controller
  200. * (1) Set TSADCV2_AUTO_PERIOD, configure the interleave between
  201. * every two accessing of TSADC in normal operation.
  202. * (2) Set TSADCV2_AUTO_PERIOD_HT, configure the interleave between
  203. * every two accessing of TSADC after the temperature is higher
  204. * than COM_SHUT or COM_INT.
  205. * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE,
  206. * if the temperature is higher than COMP_INT or COMP_SHUT for
  207. * "debounce" times, TSADC controller will generate interrupt or TSHUT.
  208. */
  209. static void rk_tsadcv2_initialize(void __iomem *regs,
  210. enum tshut_polarity tshut_polarity)
  211. {
  212. if (tshut_polarity == TSHUT_HIGH_ACTIVE)
  213. writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH),
  214. regs + TSADCV2_AUTO_CON);
  215. else
  216. writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW),
  217. regs + TSADCV2_AUTO_CON);
  218. writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
  219. writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
  220. regs + TSADCV2_HIGHT_INT_DEBOUNCE);
  221. writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
  222. regs + TSADCV2_AUTO_PERIOD_HT);
  223. writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
  224. regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
  225. }
  226. static void rk_tsadcv2_irq_ack(void __iomem *regs)
  227. {
  228. u32 val;
  229. val = readl_relaxed(regs + TSADCV2_INT_PD);
  230. writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD);
  231. }
  232. static void rk_tsadcv2_control(void __iomem *regs, bool enable)
  233. {
  234. u32 val;
  235. val = readl_relaxed(regs + TSADCV2_AUTO_CON);
  236. if (enable)
  237. val |= TSADCV2_AUTO_EN;
  238. else
  239. val &= ~TSADCV2_AUTO_EN;
  240. writel_relaxed(val, regs + TSADCV2_AUTO_CON);
  241. }
  242. static int rk_tsadcv2_get_temp(int chn, void __iomem *regs, long *temp)
  243. {
  244. u32 val;
  245. /* the A/D value of the channel last conversion need some time */
  246. val = readl_relaxed(regs + TSADCV2_DATA(chn));
  247. if (val == 0)
  248. return -EAGAIN;
  249. *temp = rk_tsadcv2_code_to_temp(val);
  250. return 0;
  251. }
  252. static void rk_tsadcv2_tshut_temp(int chn, void __iomem *regs, long temp)
  253. {
  254. u32 tshut_value, val;
  255. tshut_value = rk_tsadcv2_temp_to_code(temp);
  256. writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
  257. /* TSHUT will be valid */
  258. val = readl_relaxed(regs + TSADCV2_AUTO_CON);
  259. writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
  260. }
  261. static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
  262. enum tshut_mode mode)
  263. {
  264. u32 val;
  265. val = readl_relaxed(regs + TSADCV2_INT_EN);
  266. if (mode == TSHUT_MODE_GPIO) {
  267. val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
  268. val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
  269. } else {
  270. val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
  271. val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
  272. }
  273. writel_relaxed(val, regs + TSADCV2_INT_EN);
  274. }
  275. static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
  276. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  277. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  278. .tshut_temp = 95000,
  279. .initialize = rk_tsadcv2_initialize,
  280. .irq_ack = rk_tsadcv2_irq_ack,
  281. .control = rk_tsadcv2_control,
  282. .get_temp = rk_tsadcv2_get_temp,
  283. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  284. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  285. };
  286. static const struct of_device_id of_rockchip_thermal_match[] = {
  287. {
  288. .compatible = "rockchip,rk3288-tsadc",
  289. .data = (void *)&rk3288_tsadc_data,
  290. },
  291. { /* end */ },
  292. };
  293. MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
  294. static void
  295. rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
  296. {
  297. struct thermal_zone_device *tzd = sensor->tzd;
  298. tzd->ops->set_mode(tzd,
  299. on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
  300. }
  301. static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
  302. {
  303. struct rockchip_thermal_data *thermal = dev;
  304. int i;
  305. dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
  306. thermal->chip->irq_ack(thermal->regs);
  307. for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
  308. thermal_zone_device_update(thermal->sensors[i].tzd);
  309. return IRQ_HANDLED;
  310. }
  311. static int rockchip_thermal_get_temp(void *_sensor, long *out_temp)
  312. {
  313. struct rockchip_thermal_sensor *sensor = _sensor;
  314. struct rockchip_thermal_data *thermal = sensor->thermal;
  315. const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
  316. int retval;
  317. retval = tsadc->get_temp(sensor->id, thermal->regs, out_temp);
  318. dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %ld, retval: %d\n",
  319. sensor->id, *out_temp, retval);
  320. return retval;
  321. }
  322. static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
  323. .get_temp = rockchip_thermal_get_temp,
  324. };
  325. static int rockchip_configure_from_dt(struct device *dev,
  326. struct device_node *np,
  327. struct rockchip_thermal_data *thermal)
  328. {
  329. u32 shut_temp, tshut_mode, tshut_polarity;
  330. if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
  331. dev_warn(dev,
  332. "Missing tshut temp property, using default %ld\n",
  333. thermal->chip->tshut_temp);
  334. thermal->tshut_temp = thermal->chip->tshut_temp;
  335. } else {
  336. thermal->tshut_temp = shut_temp;
  337. }
  338. if (thermal->tshut_temp > INT_MAX) {
  339. dev_err(dev, "Invalid tshut temperature specified: %ld\n",
  340. thermal->tshut_temp);
  341. return -ERANGE;
  342. }
  343. if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
  344. dev_warn(dev,
  345. "Missing tshut mode property, using default (%s)\n",
  346. thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
  347. "gpio" : "cru");
  348. thermal->tshut_mode = thermal->chip->tshut_mode;
  349. } else {
  350. thermal->tshut_mode = tshut_mode;
  351. }
  352. if (thermal->tshut_mode > 1) {
  353. dev_err(dev, "Invalid tshut mode specified: %d\n",
  354. thermal->tshut_mode);
  355. return -EINVAL;
  356. }
  357. if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
  358. &tshut_polarity)) {
  359. dev_warn(dev,
  360. "Missing tshut-polarity property, using default (%s)\n",
  361. thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
  362. "low" : "high");
  363. thermal->tshut_polarity = thermal->chip->tshut_polarity;
  364. } else {
  365. thermal->tshut_polarity = tshut_polarity;
  366. }
  367. if (thermal->tshut_polarity > 1) {
  368. dev_err(dev, "Invalid tshut-polarity specified: %d\n",
  369. thermal->tshut_polarity);
  370. return -EINVAL;
  371. }
  372. return 0;
  373. }
  374. static int
  375. rockchip_thermal_register_sensor(struct platform_device *pdev,
  376. struct rockchip_thermal_data *thermal,
  377. struct rockchip_thermal_sensor *sensor,
  378. enum sensor_id id)
  379. {
  380. const struct rockchip_tsadc_chip *tsadc = thermal->chip;
  381. int error;
  382. tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
  383. tsadc->set_tshut_temp(id, thermal->regs, thermal->tshut_temp);
  384. sensor->thermal = thermal;
  385. sensor->id = id;
  386. sensor->tzd = thermal_zone_of_sensor_register(&pdev->dev, id, sensor,
  387. &rockchip_of_thermal_ops);
  388. if (IS_ERR(sensor->tzd)) {
  389. error = PTR_ERR(sensor->tzd);
  390. dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
  391. id, error);
  392. return error;
  393. }
  394. return 0;
  395. }
  396. /*
  397. * Reset TSADC Controller, reset all tsadc registers.
  398. */
  399. static void rockchip_thermal_reset_controller(struct reset_control *reset)
  400. {
  401. reset_control_assert(reset);
  402. usleep_range(10, 20);
  403. reset_control_deassert(reset);
  404. }
  405. static int rockchip_thermal_probe(struct platform_device *pdev)
  406. {
  407. struct device_node *np = pdev->dev.of_node;
  408. struct rockchip_thermal_data *thermal;
  409. const struct of_device_id *match;
  410. struct resource *res;
  411. int irq;
  412. int i;
  413. int error;
  414. match = of_match_node(of_rockchip_thermal_match, np);
  415. if (!match)
  416. return -ENXIO;
  417. irq = platform_get_irq(pdev, 0);
  418. if (irq < 0) {
  419. dev_err(&pdev->dev, "no irq resource?\n");
  420. return -EINVAL;
  421. }
  422. thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
  423. GFP_KERNEL);
  424. if (!thermal)
  425. return -ENOMEM;
  426. thermal->pdev = pdev;
  427. thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
  428. if (!thermal->chip)
  429. return -EINVAL;
  430. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  431. thermal->regs = devm_ioremap_resource(&pdev->dev, res);
  432. if (IS_ERR(thermal->regs))
  433. return PTR_ERR(thermal->regs);
  434. thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
  435. if (IS_ERR(thermal->reset)) {
  436. error = PTR_ERR(thermal->reset);
  437. dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
  438. return error;
  439. }
  440. thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
  441. if (IS_ERR(thermal->clk)) {
  442. error = PTR_ERR(thermal->clk);
  443. dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
  444. return error;
  445. }
  446. thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
  447. if (IS_ERR(thermal->pclk)) {
  448. error = PTR_ERR(thermal->pclk);
  449. dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
  450. error);
  451. return error;
  452. }
  453. error = clk_prepare_enable(thermal->clk);
  454. if (error) {
  455. dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
  456. error);
  457. return error;
  458. }
  459. error = clk_prepare_enable(thermal->pclk);
  460. if (error) {
  461. dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
  462. goto err_disable_clk;
  463. }
  464. rockchip_thermal_reset_controller(thermal->reset);
  465. error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
  466. if (error) {
  467. dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
  468. error);
  469. goto err_disable_pclk;
  470. }
  471. thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
  472. error = rockchip_thermal_register_sensor(pdev, thermal,
  473. &thermal->sensors[0],
  474. SENSOR_CPU);
  475. if (error) {
  476. dev_err(&pdev->dev,
  477. "failed to register CPU thermal sensor: %d\n", error);
  478. goto err_disable_pclk;
  479. }
  480. error = rockchip_thermal_register_sensor(pdev, thermal,
  481. &thermal->sensors[1],
  482. SENSOR_GPU);
  483. if (error) {
  484. dev_err(&pdev->dev,
  485. "failed to register GPU thermal sensor: %d\n", error);
  486. goto err_unregister_cpu_sensor;
  487. }
  488. error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  489. &rockchip_thermal_alarm_irq_thread,
  490. IRQF_ONESHOT,
  491. "rockchip_thermal", thermal);
  492. if (error) {
  493. dev_err(&pdev->dev,
  494. "failed to request tsadc irq: %d\n", error);
  495. goto err_unregister_gpu_sensor;
  496. }
  497. thermal->chip->control(thermal->regs, true);
  498. for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
  499. rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
  500. platform_set_drvdata(pdev, thermal);
  501. return 0;
  502. err_unregister_gpu_sensor:
  503. thermal_zone_of_sensor_unregister(&pdev->dev, thermal->sensors[1].tzd);
  504. err_unregister_cpu_sensor:
  505. thermal_zone_of_sensor_unregister(&pdev->dev, thermal->sensors[0].tzd);
  506. err_disable_pclk:
  507. clk_disable_unprepare(thermal->pclk);
  508. err_disable_clk:
  509. clk_disable_unprepare(thermal->clk);
  510. return error;
  511. }
  512. static int rockchip_thermal_remove(struct platform_device *pdev)
  513. {
  514. struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
  515. int i;
  516. for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++) {
  517. struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
  518. rockchip_thermal_toggle_sensor(sensor, false);
  519. thermal_zone_of_sensor_unregister(&pdev->dev, sensor->tzd);
  520. }
  521. thermal->chip->control(thermal->regs, false);
  522. clk_disable_unprepare(thermal->pclk);
  523. clk_disable_unprepare(thermal->clk);
  524. return 0;
  525. }
  526. static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
  527. {
  528. struct platform_device *pdev = to_platform_device(dev);
  529. struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
  530. int i;
  531. for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
  532. rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
  533. thermal->chip->control(thermal->regs, false);
  534. clk_disable(thermal->pclk);
  535. clk_disable(thermal->clk);
  536. return 0;
  537. }
  538. static int __maybe_unused rockchip_thermal_resume(struct device *dev)
  539. {
  540. struct platform_device *pdev = to_platform_device(dev);
  541. struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
  542. int i;
  543. int error;
  544. error = clk_enable(thermal->clk);
  545. if (error)
  546. return error;
  547. error = clk_enable(thermal->pclk);
  548. if (error)
  549. return error;
  550. rockchip_thermal_reset_controller(thermal->reset);
  551. thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
  552. for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++) {
  553. enum sensor_id id = thermal->sensors[i].id;
  554. thermal->chip->set_tshut_mode(id, thermal->regs,
  555. thermal->tshut_mode);
  556. thermal->chip->set_tshut_temp(id, thermal->regs,
  557. thermal->tshut_temp);
  558. }
  559. thermal->chip->control(thermal->regs, true);
  560. for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
  561. rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
  562. return 0;
  563. }
  564. static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
  565. rockchip_thermal_suspend, rockchip_thermal_resume);
  566. static struct platform_driver rockchip_thermal_driver = {
  567. .driver = {
  568. .name = "rockchip-thermal",
  569. .pm = &rockchip_thermal_pm_ops,
  570. .of_match_table = of_rockchip_thermal_match,
  571. },
  572. .probe = rockchip_thermal_probe,
  573. .remove = rockchip_thermal_remove,
  574. };
  575. module_platform_driver(rockchip_thermal_driver);
  576. MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
  577. MODULE_AUTHOR("Rockchip, Inc.");
  578. MODULE_LICENSE("GPL v2");
  579. MODULE_ALIAS("platform:rockchip-thermal");