ufshcd.c 147 KB

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  1. /*
  2. * Universal Flash Storage Host controller driver Core
  3. *
  4. * This code is based on drivers/scsi/ufs/ufshcd.c
  5. * Copyright (C) 2011-2013 Samsung India Software Operations
  6. * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  7. *
  8. * Authors:
  9. * Santosh Yaraganavi <santosh.sy@samsung.com>
  10. * Vinayak Holikatti <h.vinayak@samsung.com>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version 2
  15. * of the License, or (at your option) any later version.
  16. * See the COPYING file in the top-level directory or visit
  17. * <http://www.gnu.org/licenses/gpl-2.0.html>
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * This program is provided "AS IS" and "WITH ALL FAULTS" and
  25. * without warranty of any kind. You are solely responsible for
  26. * determining the appropriateness of using and distributing
  27. * the program and assume all risks associated with your exercise
  28. * of rights with respect to the program, including but not limited
  29. * to infringement of third party rights, the risks and costs of
  30. * program errors, damage to or loss of data, programs or equipment,
  31. * and unavailability or interruption of operations. Under no
  32. * circumstances will the contributor of this Program be liable for
  33. * any damages of any kind arising from your use or distribution of
  34. * this program.
  35. *
  36. * The Linux Foundation chooses to take subject only to the GPLv2
  37. * license terms, and distributes only under these terms.
  38. */
  39. #include <linux/async.h>
  40. #include <linux/devfreq.h>
  41. #include "ufshcd.h"
  42. #include "unipro.h"
  43. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  44. UTP_TASK_REQ_COMPL |\
  45. UFSHCD_ERROR_MASK)
  46. /* UIC command timeout, unit: ms */
  47. #define UIC_CMD_TIMEOUT 500
  48. /* NOP OUT retries waiting for NOP IN response */
  49. #define NOP_OUT_RETRIES 10
  50. /* Timeout after 30 msecs if NOP OUT hangs without response */
  51. #define NOP_OUT_TIMEOUT 30 /* msecs */
  52. /* Query request retries */
  53. #define QUERY_REQ_RETRIES 10
  54. /* Query request timeout */
  55. #define QUERY_REQ_TIMEOUT 30 /* msec */
  56. /* Task management command timeout */
  57. #define TM_CMD_TIMEOUT 100 /* msecs */
  58. /* maximum number of link-startup retries */
  59. #define DME_LINKSTARTUP_RETRIES 3
  60. /* maximum number of reset retries before giving up */
  61. #define MAX_HOST_RESET_RETRIES 5
  62. /* Expose the flag value from utp_upiu_query.value */
  63. #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  64. /* Interrupt aggregation default timeout, unit: 40us */
  65. #define INT_AGGR_DEF_TO 0x02
  66. #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
  67. ({ \
  68. int _ret; \
  69. if (_on) \
  70. _ret = ufshcd_enable_vreg(_dev, _vreg); \
  71. else \
  72. _ret = ufshcd_disable_vreg(_dev, _vreg); \
  73. _ret; \
  74. })
  75. static u32 ufs_query_desc_max_size[] = {
  76. QUERY_DESC_DEVICE_MAX_SIZE,
  77. QUERY_DESC_CONFIGURAION_MAX_SIZE,
  78. QUERY_DESC_UNIT_MAX_SIZE,
  79. QUERY_DESC_RFU_MAX_SIZE,
  80. QUERY_DESC_INTERCONNECT_MAX_SIZE,
  81. QUERY_DESC_STRING_MAX_SIZE,
  82. QUERY_DESC_RFU_MAX_SIZE,
  83. QUERY_DESC_GEOMETRY_MAZ_SIZE,
  84. QUERY_DESC_POWER_MAX_SIZE,
  85. QUERY_DESC_RFU_MAX_SIZE,
  86. };
  87. enum {
  88. UFSHCD_MAX_CHANNEL = 0,
  89. UFSHCD_MAX_ID = 1,
  90. UFSHCD_CMD_PER_LUN = 32,
  91. UFSHCD_CAN_QUEUE = 32,
  92. };
  93. /* UFSHCD states */
  94. enum {
  95. UFSHCD_STATE_RESET,
  96. UFSHCD_STATE_ERROR,
  97. UFSHCD_STATE_OPERATIONAL,
  98. };
  99. /* UFSHCD error handling flags */
  100. enum {
  101. UFSHCD_EH_IN_PROGRESS = (1 << 0),
  102. };
  103. /* UFSHCD UIC layer error flags */
  104. enum {
  105. UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
  106. UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
  107. UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
  108. UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
  109. };
  110. /* Interrupt configuration options */
  111. enum {
  112. UFSHCD_INT_DISABLE,
  113. UFSHCD_INT_ENABLE,
  114. UFSHCD_INT_CLEAR,
  115. };
  116. #define ufshcd_set_eh_in_progress(h) \
  117. (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
  118. #define ufshcd_eh_in_progress(h) \
  119. (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
  120. #define ufshcd_clear_eh_in_progress(h) \
  121. (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
  122. #define ufshcd_set_ufs_dev_active(h) \
  123. ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
  124. #define ufshcd_set_ufs_dev_sleep(h) \
  125. ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
  126. #define ufshcd_set_ufs_dev_poweroff(h) \
  127. ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
  128. #define ufshcd_is_ufs_dev_active(h) \
  129. ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
  130. #define ufshcd_is_ufs_dev_sleep(h) \
  131. ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
  132. #define ufshcd_is_ufs_dev_poweroff(h) \
  133. ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
  134. static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
  135. {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  136. {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  137. {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  138. {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  139. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  140. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
  141. };
  142. static inline enum ufs_dev_pwr_mode
  143. ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
  144. {
  145. return ufs_pm_lvl_states[lvl].dev_state;
  146. }
  147. static inline enum uic_link_state
  148. ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
  149. {
  150. return ufs_pm_lvl_states[lvl].link_state;
  151. }
  152. static void ufshcd_tmc_handler(struct ufs_hba *hba);
  153. static void ufshcd_async_scan(void *data, async_cookie_t cookie);
  154. static int ufshcd_reset_and_restore(struct ufs_hba *hba);
  155. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
  156. static void ufshcd_hba_exit(struct ufs_hba *hba);
  157. static int ufshcd_probe_hba(struct ufs_hba *hba);
  158. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  159. bool skip_ref_clk);
  160. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
  161. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
  162. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
  163. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
  164. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
  165. static irqreturn_t ufshcd_intr(int irq, void *__hba);
  166. static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  167. struct ufs_pa_layer_attr *desired_pwr_mode);
  168. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  169. struct ufs_pa_layer_attr *pwr_mode);
  170. static inline int ufshcd_enable_irq(struct ufs_hba *hba)
  171. {
  172. int ret = 0;
  173. if (!hba->is_irq_enabled) {
  174. ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
  175. hba);
  176. if (ret)
  177. dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
  178. __func__, ret);
  179. hba->is_irq_enabled = true;
  180. }
  181. return ret;
  182. }
  183. static inline void ufshcd_disable_irq(struct ufs_hba *hba)
  184. {
  185. if (hba->is_irq_enabled) {
  186. free_irq(hba->irq, hba);
  187. hba->is_irq_enabled = false;
  188. }
  189. }
  190. /*
  191. * ufshcd_wait_for_register - wait for register value to change
  192. * @hba - per-adapter interface
  193. * @reg - mmio register offset
  194. * @mask - mask to apply to read register value
  195. * @val - wait condition
  196. * @interval_us - polling interval in microsecs
  197. * @timeout_ms - timeout in millisecs
  198. *
  199. * Returns -ETIMEDOUT on error, zero on success
  200. */
  201. static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  202. u32 val, unsigned long interval_us, unsigned long timeout_ms)
  203. {
  204. int err = 0;
  205. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  206. /* ignore bits that we don't intend to wait on */
  207. val = val & mask;
  208. while ((ufshcd_readl(hba, reg) & mask) != val) {
  209. /* wakeup within 50us of expiry */
  210. usleep_range(interval_us, interval_us + 50);
  211. if (time_after(jiffies, timeout)) {
  212. if ((ufshcd_readl(hba, reg) & mask) != val)
  213. err = -ETIMEDOUT;
  214. break;
  215. }
  216. }
  217. return err;
  218. }
  219. /**
  220. * ufshcd_get_intr_mask - Get the interrupt bit mask
  221. * @hba - Pointer to adapter instance
  222. *
  223. * Returns interrupt bit mask per version
  224. */
  225. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  226. {
  227. if (hba->ufs_version == UFSHCI_VERSION_10)
  228. return INTERRUPT_MASK_ALL_VER_10;
  229. else
  230. return INTERRUPT_MASK_ALL_VER_11;
  231. }
  232. /**
  233. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  234. * @hba - Pointer to adapter instance
  235. *
  236. * Returns UFSHCI version supported by the controller
  237. */
  238. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  239. {
  240. if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) {
  241. if (hba->vops && hba->vops->get_ufs_hci_version)
  242. return hba->vops->get_ufs_hci_version(hba);
  243. }
  244. return ufshcd_readl(hba, REG_UFS_VERSION);
  245. }
  246. /**
  247. * ufshcd_is_device_present - Check if any device connected to
  248. * the host controller
  249. * @hba: pointer to adapter instance
  250. *
  251. * Returns 1 if device present, 0 if no device detected
  252. */
  253. static inline int ufshcd_is_device_present(struct ufs_hba *hba)
  254. {
  255. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
  256. DEVICE_PRESENT) ? 1 : 0;
  257. }
  258. /**
  259. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  260. * @lrb: pointer to local command reference block
  261. *
  262. * This function is used to get the OCS field from UTRD
  263. * Returns the OCS field in the UTRD
  264. */
  265. static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
  266. {
  267. return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
  268. }
  269. /**
  270. * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
  271. * @task_req_descp: pointer to utp_task_req_desc structure
  272. *
  273. * This function is used to get the OCS field from UTMRD
  274. * Returns the OCS field in the UTMRD
  275. */
  276. static inline int
  277. ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
  278. {
  279. return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
  280. }
  281. /**
  282. * ufshcd_get_tm_free_slot - get a free slot for task management request
  283. * @hba: per adapter instance
  284. * @free_slot: pointer to variable with available slot value
  285. *
  286. * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
  287. * Returns 0 if free slot is not available, else return 1 with tag value
  288. * in @free_slot.
  289. */
  290. static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
  291. {
  292. int tag;
  293. bool ret = false;
  294. if (!free_slot)
  295. goto out;
  296. do {
  297. tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
  298. if (tag >= hba->nutmrs)
  299. goto out;
  300. } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
  301. *free_slot = tag;
  302. ret = true;
  303. out:
  304. return ret;
  305. }
  306. static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
  307. {
  308. clear_bit_unlock(slot, &hba->tm_slots_in_use);
  309. }
  310. /**
  311. * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
  312. * @hba: per adapter instance
  313. * @pos: position of the bit to be cleared
  314. */
  315. static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
  316. {
  317. ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  318. }
  319. /**
  320. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  321. * @reg: Register value of host controller status
  322. *
  323. * Returns integer, 0 on Success and positive value if failed
  324. */
  325. static inline int ufshcd_get_lists_status(u32 reg)
  326. {
  327. /*
  328. * The mask 0xFF is for the following HCS register bits
  329. * Bit Description
  330. * 0 Device Present
  331. * 1 UTRLRDY
  332. * 2 UTMRLRDY
  333. * 3 UCRDY
  334. * 4 HEI
  335. * 5 DEI
  336. * 6-7 reserved
  337. */
  338. return (((reg) & (0xFF)) >> 1) ^ (0x07);
  339. }
  340. /**
  341. * ufshcd_get_uic_cmd_result - Get the UIC command result
  342. * @hba: Pointer to adapter instance
  343. *
  344. * This function gets the result of UIC command completion
  345. * Returns 0 on success, non zero value on error
  346. */
  347. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  348. {
  349. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  350. MASK_UIC_COMMAND_RESULT;
  351. }
  352. /**
  353. * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
  354. * @hba: Pointer to adapter instance
  355. *
  356. * This function gets UIC command argument3
  357. * Returns 0 on success, non zero value on error
  358. */
  359. static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
  360. {
  361. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
  362. }
  363. /**
  364. * ufshcd_get_req_rsp - returns the TR response transaction type
  365. * @ucd_rsp_ptr: pointer to response UPIU
  366. */
  367. static inline int
  368. ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  369. {
  370. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  371. }
  372. /**
  373. * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
  374. * @ucd_rsp_ptr: pointer to response UPIU
  375. *
  376. * This function gets the response status and scsi_status from response UPIU
  377. * Returns the response result code.
  378. */
  379. static inline int
  380. ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  381. {
  382. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  383. }
  384. /*
  385. * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
  386. * from response UPIU
  387. * @ucd_rsp_ptr: pointer to response UPIU
  388. *
  389. * Return the data segment length.
  390. */
  391. static inline unsigned int
  392. ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
  393. {
  394. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  395. MASK_RSP_UPIU_DATA_SEG_LEN;
  396. }
  397. /**
  398. * ufshcd_is_exception_event - Check if the device raised an exception event
  399. * @ucd_rsp_ptr: pointer to response UPIU
  400. *
  401. * The function checks if the device raised an exception event indicated in
  402. * the Device Information field of response UPIU.
  403. *
  404. * Returns true if exception is raised, false otherwise.
  405. */
  406. static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
  407. {
  408. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  409. MASK_RSP_EXCEPTION_EVENT ? true : false;
  410. }
  411. /**
  412. * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
  413. * @hba: per adapter instance
  414. */
  415. static inline void
  416. ufshcd_reset_intr_aggr(struct ufs_hba *hba)
  417. {
  418. ufshcd_writel(hba, INT_AGGR_ENABLE |
  419. INT_AGGR_COUNTER_AND_TIMER_RESET,
  420. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  421. }
  422. /**
  423. * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
  424. * @hba: per adapter instance
  425. * @cnt: Interrupt aggregation counter threshold
  426. * @tmout: Interrupt aggregation timeout value
  427. */
  428. static inline void
  429. ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
  430. {
  431. ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
  432. INT_AGGR_COUNTER_THLD_VAL(cnt) |
  433. INT_AGGR_TIMEOUT_VAL(tmout),
  434. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  435. }
  436. /**
  437. * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
  438. * @hba: per adapter instance
  439. */
  440. static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
  441. {
  442. ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  443. }
  444. /**
  445. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  446. * When run-stop registers are set to 1, it indicates the
  447. * host controller that it can process the requests
  448. * @hba: per adapter instance
  449. */
  450. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  451. {
  452. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  453. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  454. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  455. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  456. }
  457. /**
  458. * ufshcd_hba_start - Start controller initialization sequence
  459. * @hba: per adapter instance
  460. */
  461. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  462. {
  463. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  464. }
  465. /**
  466. * ufshcd_is_hba_active - Get controller state
  467. * @hba: per adapter instance
  468. *
  469. * Returns zero if controller is active, 1 otherwise
  470. */
  471. static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
  472. {
  473. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
  474. }
  475. static void ufshcd_ungate_work(struct work_struct *work)
  476. {
  477. int ret;
  478. unsigned long flags;
  479. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  480. clk_gating.ungate_work);
  481. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  482. spin_lock_irqsave(hba->host->host_lock, flags);
  483. if (hba->clk_gating.state == CLKS_ON) {
  484. spin_unlock_irqrestore(hba->host->host_lock, flags);
  485. goto unblock_reqs;
  486. }
  487. spin_unlock_irqrestore(hba->host->host_lock, flags);
  488. ufshcd_setup_clocks(hba, true);
  489. /* Exit from hibern8 */
  490. if (ufshcd_can_hibern8_during_gating(hba)) {
  491. /* Prevent gating in this path */
  492. hba->clk_gating.is_suspended = true;
  493. if (ufshcd_is_link_hibern8(hba)) {
  494. ret = ufshcd_uic_hibern8_exit(hba);
  495. if (ret)
  496. dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
  497. __func__, ret);
  498. else
  499. ufshcd_set_link_active(hba);
  500. }
  501. hba->clk_gating.is_suspended = false;
  502. }
  503. unblock_reqs:
  504. if (ufshcd_is_clkscaling_enabled(hba))
  505. devfreq_resume_device(hba->devfreq);
  506. scsi_unblock_requests(hba->host);
  507. }
  508. /**
  509. * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
  510. * Also, exit from hibern8 mode and set the link as active.
  511. * @hba: per adapter instance
  512. * @async: This indicates whether caller should ungate clocks asynchronously.
  513. */
  514. int ufshcd_hold(struct ufs_hba *hba, bool async)
  515. {
  516. int rc = 0;
  517. unsigned long flags;
  518. if (!ufshcd_is_clkgating_allowed(hba))
  519. goto out;
  520. spin_lock_irqsave(hba->host->host_lock, flags);
  521. hba->clk_gating.active_reqs++;
  522. start:
  523. switch (hba->clk_gating.state) {
  524. case CLKS_ON:
  525. break;
  526. case REQ_CLKS_OFF:
  527. if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
  528. hba->clk_gating.state = CLKS_ON;
  529. break;
  530. }
  531. /*
  532. * If we here, it means gating work is either done or
  533. * currently running. Hence, fall through to cancel gating
  534. * work and to enable clocks.
  535. */
  536. case CLKS_OFF:
  537. scsi_block_requests(hba->host);
  538. hba->clk_gating.state = REQ_CLKS_ON;
  539. schedule_work(&hba->clk_gating.ungate_work);
  540. /*
  541. * fall through to check if we should wait for this
  542. * work to be done or not.
  543. */
  544. case REQ_CLKS_ON:
  545. if (async) {
  546. rc = -EAGAIN;
  547. hba->clk_gating.active_reqs--;
  548. break;
  549. }
  550. spin_unlock_irqrestore(hba->host->host_lock, flags);
  551. flush_work(&hba->clk_gating.ungate_work);
  552. /* Make sure state is CLKS_ON before returning */
  553. spin_lock_irqsave(hba->host->host_lock, flags);
  554. goto start;
  555. default:
  556. dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
  557. __func__, hba->clk_gating.state);
  558. break;
  559. }
  560. spin_unlock_irqrestore(hba->host->host_lock, flags);
  561. out:
  562. return rc;
  563. }
  564. static void ufshcd_gate_work(struct work_struct *work)
  565. {
  566. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  567. clk_gating.gate_work.work);
  568. unsigned long flags;
  569. spin_lock_irqsave(hba->host->host_lock, flags);
  570. if (hba->clk_gating.is_suspended) {
  571. hba->clk_gating.state = CLKS_ON;
  572. goto rel_lock;
  573. }
  574. if (hba->clk_gating.active_reqs
  575. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  576. || hba->lrb_in_use || hba->outstanding_tasks
  577. || hba->active_uic_cmd || hba->uic_async_done)
  578. goto rel_lock;
  579. spin_unlock_irqrestore(hba->host->host_lock, flags);
  580. /* put the link into hibern8 mode before turning off clocks */
  581. if (ufshcd_can_hibern8_during_gating(hba)) {
  582. if (ufshcd_uic_hibern8_enter(hba)) {
  583. hba->clk_gating.state = CLKS_ON;
  584. goto out;
  585. }
  586. ufshcd_set_link_hibern8(hba);
  587. }
  588. if (ufshcd_is_clkscaling_enabled(hba)) {
  589. devfreq_suspend_device(hba->devfreq);
  590. hba->clk_scaling.window_start_t = 0;
  591. }
  592. if (!ufshcd_is_link_active(hba))
  593. ufshcd_setup_clocks(hba, false);
  594. else
  595. /* If link is active, device ref_clk can't be switched off */
  596. __ufshcd_setup_clocks(hba, false, true);
  597. /*
  598. * In case you are here to cancel this work the gating state
  599. * would be marked as REQ_CLKS_ON. In this case keep the state
  600. * as REQ_CLKS_ON which would anyway imply that clocks are off
  601. * and a request to turn them on is pending. By doing this way,
  602. * we keep the state machine in tact and this would ultimately
  603. * prevent from doing cancel work multiple times when there are
  604. * new requests arriving before the current cancel work is done.
  605. */
  606. spin_lock_irqsave(hba->host->host_lock, flags);
  607. if (hba->clk_gating.state == REQ_CLKS_OFF)
  608. hba->clk_gating.state = CLKS_OFF;
  609. rel_lock:
  610. spin_unlock_irqrestore(hba->host->host_lock, flags);
  611. out:
  612. return;
  613. }
  614. /* host lock must be held before calling this variant */
  615. static void __ufshcd_release(struct ufs_hba *hba)
  616. {
  617. if (!ufshcd_is_clkgating_allowed(hba))
  618. return;
  619. hba->clk_gating.active_reqs--;
  620. if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
  621. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  622. || hba->lrb_in_use || hba->outstanding_tasks
  623. || hba->active_uic_cmd || hba->uic_async_done)
  624. return;
  625. hba->clk_gating.state = REQ_CLKS_OFF;
  626. schedule_delayed_work(&hba->clk_gating.gate_work,
  627. msecs_to_jiffies(hba->clk_gating.delay_ms));
  628. }
  629. void ufshcd_release(struct ufs_hba *hba)
  630. {
  631. unsigned long flags;
  632. spin_lock_irqsave(hba->host->host_lock, flags);
  633. __ufshcd_release(hba);
  634. spin_unlock_irqrestore(hba->host->host_lock, flags);
  635. }
  636. static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
  637. struct device_attribute *attr, char *buf)
  638. {
  639. struct ufs_hba *hba = dev_get_drvdata(dev);
  640. return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
  641. }
  642. static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
  643. struct device_attribute *attr, const char *buf, size_t count)
  644. {
  645. struct ufs_hba *hba = dev_get_drvdata(dev);
  646. unsigned long flags, value;
  647. if (kstrtoul(buf, 0, &value))
  648. return -EINVAL;
  649. spin_lock_irqsave(hba->host->host_lock, flags);
  650. hba->clk_gating.delay_ms = value;
  651. spin_unlock_irqrestore(hba->host->host_lock, flags);
  652. return count;
  653. }
  654. static void ufshcd_init_clk_gating(struct ufs_hba *hba)
  655. {
  656. if (!ufshcd_is_clkgating_allowed(hba))
  657. return;
  658. hba->clk_gating.delay_ms = 150;
  659. INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
  660. INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
  661. hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
  662. hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
  663. sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
  664. hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
  665. hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
  666. if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
  667. dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
  668. }
  669. static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
  670. {
  671. if (!ufshcd_is_clkgating_allowed(hba))
  672. return;
  673. device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
  674. cancel_work_sync(&hba->clk_gating.ungate_work);
  675. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  676. }
  677. /* Must be called with host lock acquired */
  678. static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
  679. {
  680. if (!ufshcd_is_clkscaling_enabled(hba))
  681. return;
  682. if (!hba->clk_scaling.is_busy_started) {
  683. hba->clk_scaling.busy_start_t = ktime_get();
  684. hba->clk_scaling.is_busy_started = true;
  685. }
  686. }
  687. static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
  688. {
  689. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  690. if (!ufshcd_is_clkscaling_enabled(hba))
  691. return;
  692. if (!hba->outstanding_reqs && scaling->is_busy_started) {
  693. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  694. scaling->busy_start_t));
  695. scaling->busy_start_t = ktime_set(0, 0);
  696. scaling->is_busy_started = false;
  697. }
  698. }
  699. /**
  700. * ufshcd_send_command - Send SCSI or device management commands
  701. * @hba: per adapter instance
  702. * @task_tag: Task tag of the command
  703. */
  704. static inline
  705. void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  706. {
  707. ufshcd_clk_scaling_start_busy(hba);
  708. __set_bit(task_tag, &hba->outstanding_reqs);
  709. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  710. }
  711. /**
  712. * ufshcd_copy_sense_data - Copy sense data in case of check condition
  713. * @lrb - pointer to local reference block
  714. */
  715. static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
  716. {
  717. int len;
  718. if (lrbp->sense_buffer &&
  719. ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
  720. len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
  721. memcpy(lrbp->sense_buffer,
  722. lrbp->ucd_rsp_ptr->sr.sense_data,
  723. min_t(int, len, SCSI_SENSE_BUFFERSIZE));
  724. }
  725. }
  726. /**
  727. * ufshcd_copy_query_response() - Copy the Query Response and the data
  728. * descriptor
  729. * @hba: per adapter instance
  730. * @lrb - pointer to local reference block
  731. */
  732. static
  733. int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  734. {
  735. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  736. memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
  737. /* Get the descriptor */
  738. if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
  739. u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
  740. GENERAL_UPIU_REQUEST_SIZE;
  741. u16 resp_len;
  742. u16 buf_len;
  743. /* data segment length */
  744. resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
  745. MASK_QUERY_DATA_SEG_LEN;
  746. buf_len = be16_to_cpu(
  747. hba->dev_cmd.query.request.upiu_req.length);
  748. if (likely(buf_len >= resp_len)) {
  749. memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
  750. } else {
  751. dev_warn(hba->dev,
  752. "%s: Response size is bigger than buffer",
  753. __func__);
  754. return -EINVAL;
  755. }
  756. }
  757. return 0;
  758. }
  759. /**
  760. * ufshcd_hba_capabilities - Read controller capabilities
  761. * @hba: per adapter instance
  762. */
  763. static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
  764. {
  765. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  766. /* nutrs and nutmrs are 0 based values */
  767. hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
  768. hba->nutmrs =
  769. ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
  770. }
  771. /**
  772. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  773. * to accept UIC commands
  774. * @hba: per adapter instance
  775. * Return true on success, else false
  776. */
  777. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  778. {
  779. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  780. return true;
  781. else
  782. return false;
  783. }
  784. /**
  785. * ufshcd_get_upmcrs - Get the power mode change request status
  786. * @hba: Pointer to adapter instance
  787. *
  788. * This function gets the UPMCRS field of HCS register
  789. * Returns value of UPMCRS field
  790. */
  791. static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
  792. {
  793. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
  794. }
  795. /**
  796. * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
  797. * @hba: per adapter instance
  798. * @uic_cmd: UIC command
  799. *
  800. * Mutex must be held.
  801. */
  802. static inline void
  803. ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  804. {
  805. WARN_ON(hba->active_uic_cmd);
  806. hba->active_uic_cmd = uic_cmd;
  807. /* Write Args */
  808. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  809. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  810. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  811. /* Write UIC Cmd */
  812. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  813. REG_UIC_COMMAND);
  814. }
  815. /**
  816. * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
  817. * @hba: per adapter instance
  818. * @uic_command: UIC command
  819. *
  820. * Must be called with mutex held.
  821. * Returns 0 only if success.
  822. */
  823. static int
  824. ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  825. {
  826. int ret;
  827. unsigned long flags;
  828. if (wait_for_completion_timeout(&uic_cmd->done,
  829. msecs_to_jiffies(UIC_CMD_TIMEOUT)))
  830. ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
  831. else
  832. ret = -ETIMEDOUT;
  833. spin_lock_irqsave(hba->host->host_lock, flags);
  834. hba->active_uic_cmd = NULL;
  835. spin_unlock_irqrestore(hba->host->host_lock, flags);
  836. return ret;
  837. }
  838. /**
  839. * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  840. * @hba: per adapter instance
  841. * @uic_cmd: UIC command
  842. *
  843. * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
  844. * with mutex held and host_lock locked.
  845. * Returns 0 only if success.
  846. */
  847. static int
  848. __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  849. {
  850. if (!ufshcd_ready_for_uic_cmd(hba)) {
  851. dev_err(hba->dev,
  852. "Controller not ready to accept UIC commands\n");
  853. return -EIO;
  854. }
  855. init_completion(&uic_cmd->done);
  856. ufshcd_dispatch_uic_cmd(hba, uic_cmd);
  857. return 0;
  858. }
  859. /**
  860. * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  861. * @hba: per adapter instance
  862. * @uic_cmd: UIC command
  863. *
  864. * Returns 0 only if success.
  865. */
  866. static int
  867. ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  868. {
  869. int ret;
  870. unsigned long flags;
  871. ufshcd_hold(hba, false);
  872. mutex_lock(&hba->uic_cmd_mutex);
  873. ufshcd_add_delay_before_dme_cmd(hba);
  874. spin_lock_irqsave(hba->host->host_lock, flags);
  875. ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
  876. spin_unlock_irqrestore(hba->host->host_lock, flags);
  877. if (!ret)
  878. ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
  879. mutex_unlock(&hba->uic_cmd_mutex);
  880. ufshcd_release(hba);
  881. return ret;
  882. }
  883. /**
  884. * ufshcd_map_sg - Map scatter-gather list to prdt
  885. * @lrbp - pointer to local reference block
  886. *
  887. * Returns 0 in case of success, non-zero value in case of failure
  888. */
  889. static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
  890. {
  891. struct ufshcd_sg_entry *prd_table;
  892. struct scatterlist *sg;
  893. struct scsi_cmnd *cmd;
  894. int sg_segments;
  895. int i;
  896. cmd = lrbp->cmd;
  897. sg_segments = scsi_dma_map(cmd);
  898. if (sg_segments < 0)
  899. return sg_segments;
  900. if (sg_segments) {
  901. lrbp->utr_descriptor_ptr->prd_table_length =
  902. cpu_to_le16((u16) (sg_segments));
  903. prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
  904. scsi_for_each_sg(cmd, sg, sg_segments, i) {
  905. prd_table[i].size =
  906. cpu_to_le32(((u32) sg_dma_len(sg))-1);
  907. prd_table[i].base_addr =
  908. cpu_to_le32(lower_32_bits(sg->dma_address));
  909. prd_table[i].upper_addr =
  910. cpu_to_le32(upper_32_bits(sg->dma_address));
  911. }
  912. } else {
  913. lrbp->utr_descriptor_ptr->prd_table_length = 0;
  914. }
  915. return 0;
  916. }
  917. /**
  918. * ufshcd_enable_intr - enable interrupts
  919. * @hba: per adapter instance
  920. * @intrs: interrupt bits
  921. */
  922. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  923. {
  924. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  925. if (hba->ufs_version == UFSHCI_VERSION_10) {
  926. u32 rw;
  927. rw = set & INTERRUPT_MASK_RW_VER_10;
  928. set = rw | ((set ^ intrs) & intrs);
  929. } else {
  930. set |= intrs;
  931. }
  932. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  933. }
  934. /**
  935. * ufshcd_disable_intr - disable interrupts
  936. * @hba: per adapter instance
  937. * @intrs: interrupt bits
  938. */
  939. static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
  940. {
  941. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  942. if (hba->ufs_version == UFSHCI_VERSION_10) {
  943. u32 rw;
  944. rw = (set & INTERRUPT_MASK_RW_VER_10) &
  945. ~(intrs & INTERRUPT_MASK_RW_VER_10);
  946. set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
  947. } else {
  948. set &= ~intrs;
  949. }
  950. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  951. }
  952. /**
  953. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  954. * descriptor according to request
  955. * @lrbp: pointer to local reference block
  956. * @upiu_flags: flags required in the header
  957. * @cmd_dir: requests data direction
  958. */
  959. static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
  960. u32 *upiu_flags, enum dma_data_direction cmd_dir)
  961. {
  962. struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
  963. u32 data_direction;
  964. u32 dword_0;
  965. if (cmd_dir == DMA_FROM_DEVICE) {
  966. data_direction = UTP_DEVICE_TO_HOST;
  967. *upiu_flags = UPIU_CMD_FLAGS_READ;
  968. } else if (cmd_dir == DMA_TO_DEVICE) {
  969. data_direction = UTP_HOST_TO_DEVICE;
  970. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  971. } else {
  972. data_direction = UTP_NO_DATA_TRANSFER;
  973. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  974. }
  975. dword_0 = data_direction | (lrbp->command_type
  976. << UPIU_COMMAND_TYPE_OFFSET);
  977. if (lrbp->intr_cmd)
  978. dword_0 |= UTP_REQ_DESC_INT_CMD;
  979. /* Transfer request descriptor header fields */
  980. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  981. /*
  982. * assigning invalid value for command status. Controller
  983. * updates OCS on command completion, with the command
  984. * status
  985. */
  986. req_desc->header.dword_2 =
  987. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  988. }
  989. /**
  990. * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
  991. * for scsi commands
  992. * @lrbp - local reference block pointer
  993. * @upiu_flags - flags
  994. */
  995. static
  996. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
  997. {
  998. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  999. /* command descriptor fields */
  1000. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1001. UPIU_TRANSACTION_COMMAND, upiu_flags,
  1002. lrbp->lun, lrbp->task_tag);
  1003. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1004. UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  1005. /* Total EHS length and Data segment length will be zero */
  1006. ucd_req_ptr->header.dword_2 = 0;
  1007. ucd_req_ptr->sc.exp_data_transfer_len =
  1008. cpu_to_be32(lrbp->cmd->sdb.length);
  1009. memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
  1010. (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
  1011. }
  1012. /**
  1013. * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
  1014. * for query requsts
  1015. * @hba: UFS hba
  1016. * @lrbp: local reference block pointer
  1017. * @upiu_flags: flags
  1018. */
  1019. static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
  1020. struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1021. {
  1022. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1023. struct ufs_query *query = &hba->dev_cmd.query;
  1024. u16 len = be16_to_cpu(query->request.upiu_req.length);
  1025. u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
  1026. /* Query request header */
  1027. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1028. UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
  1029. lrbp->lun, lrbp->task_tag);
  1030. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1031. 0, query->request.query_func, 0, 0);
  1032. /* Data segment length */
  1033. ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
  1034. 0, 0, len >> 8, (u8)len);
  1035. /* Copy the Query Request buffer as is */
  1036. memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
  1037. QUERY_OSF_SIZE);
  1038. /* Copy the Descriptor */
  1039. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  1040. memcpy(descp, query->descriptor, len);
  1041. }
  1042. static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
  1043. {
  1044. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1045. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  1046. /* command descriptor fields */
  1047. ucd_req_ptr->header.dword_0 =
  1048. UPIU_HEADER_DWORD(
  1049. UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
  1050. }
  1051. /**
  1052. * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
  1053. * @hba - per adapter instance
  1054. * @lrb - pointer to local reference block
  1055. */
  1056. static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1057. {
  1058. u32 upiu_flags;
  1059. int ret = 0;
  1060. switch (lrbp->command_type) {
  1061. case UTP_CMD_TYPE_SCSI:
  1062. if (likely(lrbp->cmd)) {
  1063. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
  1064. lrbp->cmd->sc_data_direction);
  1065. ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
  1066. } else {
  1067. ret = -EINVAL;
  1068. }
  1069. break;
  1070. case UTP_CMD_TYPE_DEV_MANAGE:
  1071. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
  1072. if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
  1073. ufshcd_prepare_utp_query_req_upiu(
  1074. hba, lrbp, upiu_flags);
  1075. else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
  1076. ufshcd_prepare_utp_nop_upiu(lrbp);
  1077. else
  1078. ret = -EINVAL;
  1079. break;
  1080. case UTP_CMD_TYPE_UFS:
  1081. /* For UFS native command implementation */
  1082. ret = -ENOTSUPP;
  1083. dev_err(hba->dev, "%s: UFS native command are not supported\n",
  1084. __func__);
  1085. break;
  1086. default:
  1087. ret = -ENOTSUPP;
  1088. dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
  1089. __func__, lrbp->command_type);
  1090. break;
  1091. } /* end of switch */
  1092. return ret;
  1093. }
  1094. /*
  1095. * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
  1096. * @scsi_lun: scsi LUN id
  1097. *
  1098. * Returns UPIU LUN id
  1099. */
  1100. static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
  1101. {
  1102. if (scsi_is_wlun(scsi_lun))
  1103. return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
  1104. | UFS_UPIU_WLUN_ID;
  1105. else
  1106. return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
  1107. }
  1108. /**
  1109. * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
  1110. * @scsi_lun: UPIU W-LUN id
  1111. *
  1112. * Returns SCSI W-LUN id
  1113. */
  1114. static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
  1115. {
  1116. return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
  1117. }
  1118. /**
  1119. * ufshcd_queuecommand - main entry point for SCSI requests
  1120. * @cmd: command from SCSI Midlayer
  1121. * @done: call back function
  1122. *
  1123. * Returns 0 for success, non-zero in case of failure
  1124. */
  1125. static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  1126. {
  1127. struct ufshcd_lrb *lrbp;
  1128. struct ufs_hba *hba;
  1129. unsigned long flags;
  1130. int tag;
  1131. int err = 0;
  1132. hba = shost_priv(host);
  1133. tag = cmd->request->tag;
  1134. spin_lock_irqsave(hba->host->host_lock, flags);
  1135. switch (hba->ufshcd_state) {
  1136. case UFSHCD_STATE_OPERATIONAL:
  1137. break;
  1138. case UFSHCD_STATE_RESET:
  1139. err = SCSI_MLQUEUE_HOST_BUSY;
  1140. goto out_unlock;
  1141. case UFSHCD_STATE_ERROR:
  1142. set_host_byte(cmd, DID_ERROR);
  1143. cmd->scsi_done(cmd);
  1144. goto out_unlock;
  1145. default:
  1146. dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
  1147. __func__, hba->ufshcd_state);
  1148. set_host_byte(cmd, DID_BAD_TARGET);
  1149. cmd->scsi_done(cmd);
  1150. goto out_unlock;
  1151. }
  1152. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1153. /* acquire the tag to make sure device cmds don't use it */
  1154. if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
  1155. /*
  1156. * Dev manage command in progress, requeue the command.
  1157. * Requeuing the command helps in cases where the request *may*
  1158. * find different tag instead of waiting for dev manage command
  1159. * completion.
  1160. */
  1161. err = SCSI_MLQUEUE_HOST_BUSY;
  1162. goto out;
  1163. }
  1164. err = ufshcd_hold(hba, true);
  1165. if (err) {
  1166. err = SCSI_MLQUEUE_HOST_BUSY;
  1167. clear_bit_unlock(tag, &hba->lrb_in_use);
  1168. goto out;
  1169. }
  1170. WARN_ON(hba->clk_gating.state != CLKS_ON);
  1171. lrbp = &hba->lrb[tag];
  1172. WARN_ON(lrbp->cmd);
  1173. lrbp->cmd = cmd;
  1174. lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  1175. lrbp->sense_buffer = cmd->sense_buffer;
  1176. lrbp->task_tag = tag;
  1177. lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
  1178. lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
  1179. lrbp->command_type = UTP_CMD_TYPE_SCSI;
  1180. /* form UPIU before issuing the command */
  1181. ufshcd_compose_upiu(hba, lrbp);
  1182. err = ufshcd_map_sg(lrbp);
  1183. if (err) {
  1184. lrbp->cmd = NULL;
  1185. clear_bit_unlock(tag, &hba->lrb_in_use);
  1186. goto out;
  1187. }
  1188. /* issue command to the controller */
  1189. spin_lock_irqsave(hba->host->host_lock, flags);
  1190. ufshcd_send_command(hba, tag);
  1191. out_unlock:
  1192. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1193. out:
  1194. return err;
  1195. }
  1196. static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
  1197. struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
  1198. {
  1199. lrbp->cmd = NULL;
  1200. lrbp->sense_bufflen = 0;
  1201. lrbp->sense_buffer = NULL;
  1202. lrbp->task_tag = tag;
  1203. lrbp->lun = 0; /* device management cmd is not specific to any LUN */
  1204. lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
  1205. lrbp->intr_cmd = true; /* No interrupt aggregation */
  1206. hba->dev_cmd.type = cmd_type;
  1207. return ufshcd_compose_upiu(hba, lrbp);
  1208. }
  1209. static int
  1210. ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
  1211. {
  1212. int err = 0;
  1213. unsigned long flags;
  1214. u32 mask = 1 << tag;
  1215. /* clear outstanding transaction before retry */
  1216. spin_lock_irqsave(hba->host->host_lock, flags);
  1217. ufshcd_utrl_clear(hba, tag);
  1218. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1219. /*
  1220. * wait for for h/w to clear corresponding bit in door-bell.
  1221. * max. wait is 1 sec.
  1222. */
  1223. err = ufshcd_wait_for_register(hba,
  1224. REG_UTP_TRANSFER_REQ_DOOR_BELL,
  1225. mask, ~mask, 1000, 1000);
  1226. return err;
  1227. }
  1228. static int
  1229. ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1230. {
  1231. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  1232. /* Get the UPIU response */
  1233. query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
  1234. UPIU_RSP_CODE_OFFSET;
  1235. return query_res->response;
  1236. }
  1237. /**
  1238. * ufshcd_dev_cmd_completion() - handles device management command responses
  1239. * @hba: per adapter instance
  1240. * @lrbp: pointer to local reference block
  1241. */
  1242. static int
  1243. ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1244. {
  1245. int resp;
  1246. int err = 0;
  1247. resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  1248. switch (resp) {
  1249. case UPIU_TRANSACTION_NOP_IN:
  1250. if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
  1251. err = -EINVAL;
  1252. dev_err(hba->dev, "%s: unexpected response %x\n",
  1253. __func__, resp);
  1254. }
  1255. break;
  1256. case UPIU_TRANSACTION_QUERY_RSP:
  1257. err = ufshcd_check_query_response(hba, lrbp);
  1258. if (!err)
  1259. err = ufshcd_copy_query_response(hba, lrbp);
  1260. break;
  1261. case UPIU_TRANSACTION_REJECT_UPIU:
  1262. /* TODO: handle Reject UPIU Response */
  1263. err = -EPERM;
  1264. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  1265. __func__);
  1266. break;
  1267. default:
  1268. err = -EINVAL;
  1269. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  1270. __func__, resp);
  1271. break;
  1272. }
  1273. return err;
  1274. }
  1275. static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
  1276. struct ufshcd_lrb *lrbp, int max_timeout)
  1277. {
  1278. int err = 0;
  1279. unsigned long time_left;
  1280. unsigned long flags;
  1281. time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
  1282. msecs_to_jiffies(max_timeout));
  1283. spin_lock_irqsave(hba->host->host_lock, flags);
  1284. hba->dev_cmd.complete = NULL;
  1285. if (likely(time_left)) {
  1286. err = ufshcd_get_tr_ocs(lrbp);
  1287. if (!err)
  1288. err = ufshcd_dev_cmd_completion(hba, lrbp);
  1289. }
  1290. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1291. if (!time_left) {
  1292. err = -ETIMEDOUT;
  1293. if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
  1294. /* sucessfully cleared the command, retry if needed */
  1295. err = -EAGAIN;
  1296. }
  1297. return err;
  1298. }
  1299. /**
  1300. * ufshcd_get_dev_cmd_tag - Get device management command tag
  1301. * @hba: per-adapter instance
  1302. * @tag: pointer to variable with available slot value
  1303. *
  1304. * Get a free slot and lock it until device management command
  1305. * completes.
  1306. *
  1307. * Returns false if free slot is unavailable for locking, else
  1308. * return true with tag value in @tag.
  1309. */
  1310. static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
  1311. {
  1312. int tag;
  1313. bool ret = false;
  1314. unsigned long tmp;
  1315. if (!tag_out)
  1316. goto out;
  1317. do {
  1318. tmp = ~hba->lrb_in_use;
  1319. tag = find_last_bit(&tmp, hba->nutrs);
  1320. if (tag >= hba->nutrs)
  1321. goto out;
  1322. } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
  1323. *tag_out = tag;
  1324. ret = true;
  1325. out:
  1326. return ret;
  1327. }
  1328. static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
  1329. {
  1330. clear_bit_unlock(tag, &hba->lrb_in_use);
  1331. }
  1332. /**
  1333. * ufshcd_exec_dev_cmd - API for sending device management requests
  1334. * @hba - UFS hba
  1335. * @cmd_type - specifies the type (NOP, Query...)
  1336. * @timeout - time in seconds
  1337. *
  1338. * NOTE: Since there is only one available tag for device management commands,
  1339. * it is expected you hold the hba->dev_cmd.lock mutex.
  1340. */
  1341. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
  1342. enum dev_cmd_type cmd_type, int timeout)
  1343. {
  1344. struct ufshcd_lrb *lrbp;
  1345. int err;
  1346. int tag;
  1347. struct completion wait;
  1348. unsigned long flags;
  1349. /*
  1350. * Get free slot, sleep if slots are unavailable.
  1351. * Even though we use wait_event() which sleeps indefinitely,
  1352. * the maximum wait time is bounded by SCSI request timeout.
  1353. */
  1354. wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
  1355. init_completion(&wait);
  1356. lrbp = &hba->lrb[tag];
  1357. WARN_ON(lrbp->cmd);
  1358. err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
  1359. if (unlikely(err))
  1360. goto out_put_tag;
  1361. hba->dev_cmd.complete = &wait;
  1362. spin_lock_irqsave(hba->host->host_lock, flags);
  1363. ufshcd_send_command(hba, tag);
  1364. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1365. err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
  1366. out_put_tag:
  1367. ufshcd_put_dev_cmd_tag(hba, tag);
  1368. wake_up(&hba->dev_cmd.tag_wq);
  1369. return err;
  1370. }
  1371. /**
  1372. * ufshcd_init_query() - init the query response and request parameters
  1373. * @hba: per-adapter instance
  1374. * @request: address of the request pointer to be initialized
  1375. * @response: address of the response pointer to be initialized
  1376. * @opcode: operation to perform
  1377. * @idn: flag idn to access
  1378. * @index: LU number to access
  1379. * @selector: query/flag/descriptor further identification
  1380. */
  1381. static inline void ufshcd_init_query(struct ufs_hba *hba,
  1382. struct ufs_query_req **request, struct ufs_query_res **response,
  1383. enum query_opcode opcode, u8 idn, u8 index, u8 selector)
  1384. {
  1385. *request = &hba->dev_cmd.query.request;
  1386. *response = &hba->dev_cmd.query.response;
  1387. memset(*request, 0, sizeof(struct ufs_query_req));
  1388. memset(*response, 0, sizeof(struct ufs_query_res));
  1389. (*request)->upiu_req.opcode = opcode;
  1390. (*request)->upiu_req.idn = idn;
  1391. (*request)->upiu_req.index = index;
  1392. (*request)->upiu_req.selector = selector;
  1393. }
  1394. /**
  1395. * ufshcd_query_flag() - API function for sending flag query requests
  1396. * hba: per-adapter instance
  1397. * query_opcode: flag query to perform
  1398. * idn: flag idn to access
  1399. * flag_res: the flag value after the query request completes
  1400. *
  1401. * Returns 0 for success, non-zero in case of failure
  1402. */
  1403. static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
  1404. enum flag_idn idn, bool *flag_res)
  1405. {
  1406. struct ufs_query_req *request = NULL;
  1407. struct ufs_query_res *response = NULL;
  1408. int err, index = 0, selector = 0;
  1409. BUG_ON(!hba);
  1410. ufshcd_hold(hba, false);
  1411. mutex_lock(&hba->dev_cmd.lock);
  1412. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1413. selector);
  1414. switch (opcode) {
  1415. case UPIU_QUERY_OPCODE_SET_FLAG:
  1416. case UPIU_QUERY_OPCODE_CLEAR_FLAG:
  1417. case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
  1418. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1419. break;
  1420. case UPIU_QUERY_OPCODE_READ_FLAG:
  1421. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1422. if (!flag_res) {
  1423. /* No dummy reads */
  1424. dev_err(hba->dev, "%s: Invalid argument for read request\n",
  1425. __func__);
  1426. err = -EINVAL;
  1427. goto out_unlock;
  1428. }
  1429. break;
  1430. default:
  1431. dev_err(hba->dev,
  1432. "%s: Expected query flag opcode but got = %d\n",
  1433. __func__, opcode);
  1434. err = -EINVAL;
  1435. goto out_unlock;
  1436. }
  1437. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1438. if (err) {
  1439. dev_err(hba->dev,
  1440. "%s: Sending flag query for idn %d failed, err = %d\n",
  1441. __func__, idn, err);
  1442. goto out_unlock;
  1443. }
  1444. if (flag_res)
  1445. *flag_res = (be32_to_cpu(response->upiu_res.value) &
  1446. MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
  1447. out_unlock:
  1448. mutex_unlock(&hba->dev_cmd.lock);
  1449. ufshcd_release(hba);
  1450. return err;
  1451. }
  1452. /**
  1453. * ufshcd_query_attr - API function for sending attribute requests
  1454. * hba: per-adapter instance
  1455. * opcode: attribute opcode
  1456. * idn: attribute idn to access
  1457. * index: index field
  1458. * selector: selector field
  1459. * attr_val: the attribute value after the query request completes
  1460. *
  1461. * Returns 0 for success, non-zero in case of failure
  1462. */
  1463. static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
  1464. enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
  1465. {
  1466. struct ufs_query_req *request = NULL;
  1467. struct ufs_query_res *response = NULL;
  1468. int err;
  1469. BUG_ON(!hba);
  1470. ufshcd_hold(hba, false);
  1471. if (!attr_val) {
  1472. dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
  1473. __func__, opcode);
  1474. err = -EINVAL;
  1475. goto out;
  1476. }
  1477. mutex_lock(&hba->dev_cmd.lock);
  1478. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1479. selector);
  1480. switch (opcode) {
  1481. case UPIU_QUERY_OPCODE_WRITE_ATTR:
  1482. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1483. request->upiu_req.value = cpu_to_be32(*attr_val);
  1484. break;
  1485. case UPIU_QUERY_OPCODE_READ_ATTR:
  1486. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1487. break;
  1488. default:
  1489. dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
  1490. __func__, opcode);
  1491. err = -EINVAL;
  1492. goto out_unlock;
  1493. }
  1494. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1495. if (err) {
  1496. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
  1497. __func__, opcode, idn, err);
  1498. goto out_unlock;
  1499. }
  1500. *attr_val = be32_to_cpu(response->upiu_res.value);
  1501. out_unlock:
  1502. mutex_unlock(&hba->dev_cmd.lock);
  1503. out:
  1504. ufshcd_release(hba);
  1505. return err;
  1506. }
  1507. /**
  1508. * ufshcd_query_descriptor - API function for sending descriptor requests
  1509. * hba: per-adapter instance
  1510. * opcode: attribute opcode
  1511. * idn: attribute idn to access
  1512. * index: index field
  1513. * selector: selector field
  1514. * desc_buf: the buffer that contains the descriptor
  1515. * buf_len: length parameter passed to the device
  1516. *
  1517. * Returns 0 for success, non-zero in case of failure.
  1518. * The buf_len parameter will contain, on return, the length parameter
  1519. * received on the response.
  1520. */
  1521. static int ufshcd_query_descriptor(struct ufs_hba *hba,
  1522. enum query_opcode opcode, enum desc_idn idn, u8 index,
  1523. u8 selector, u8 *desc_buf, int *buf_len)
  1524. {
  1525. struct ufs_query_req *request = NULL;
  1526. struct ufs_query_res *response = NULL;
  1527. int err;
  1528. BUG_ON(!hba);
  1529. ufshcd_hold(hba, false);
  1530. if (!desc_buf) {
  1531. dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
  1532. __func__, opcode);
  1533. err = -EINVAL;
  1534. goto out;
  1535. }
  1536. if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
  1537. dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
  1538. __func__, *buf_len);
  1539. err = -EINVAL;
  1540. goto out;
  1541. }
  1542. mutex_lock(&hba->dev_cmd.lock);
  1543. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1544. selector);
  1545. hba->dev_cmd.query.descriptor = desc_buf;
  1546. request->upiu_req.length = cpu_to_be16(*buf_len);
  1547. switch (opcode) {
  1548. case UPIU_QUERY_OPCODE_WRITE_DESC:
  1549. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1550. break;
  1551. case UPIU_QUERY_OPCODE_READ_DESC:
  1552. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1553. break;
  1554. default:
  1555. dev_err(hba->dev,
  1556. "%s: Expected query descriptor opcode but got = 0x%.2x\n",
  1557. __func__, opcode);
  1558. err = -EINVAL;
  1559. goto out_unlock;
  1560. }
  1561. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1562. if (err) {
  1563. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
  1564. __func__, opcode, idn, err);
  1565. goto out_unlock;
  1566. }
  1567. hba->dev_cmd.query.descriptor = NULL;
  1568. *buf_len = be16_to_cpu(response->upiu_res.length);
  1569. out_unlock:
  1570. mutex_unlock(&hba->dev_cmd.lock);
  1571. out:
  1572. ufshcd_release(hba);
  1573. return err;
  1574. }
  1575. /**
  1576. * ufshcd_read_desc_param - read the specified descriptor parameter
  1577. * @hba: Pointer to adapter instance
  1578. * @desc_id: descriptor idn value
  1579. * @desc_index: descriptor index
  1580. * @param_offset: offset of the parameter to read
  1581. * @param_read_buf: pointer to buffer where parameter would be read
  1582. * @param_size: sizeof(param_read_buf)
  1583. *
  1584. * Return 0 in case of success, non-zero otherwise
  1585. */
  1586. static int ufshcd_read_desc_param(struct ufs_hba *hba,
  1587. enum desc_idn desc_id,
  1588. int desc_index,
  1589. u32 param_offset,
  1590. u8 *param_read_buf,
  1591. u32 param_size)
  1592. {
  1593. int ret;
  1594. u8 *desc_buf;
  1595. u32 buff_len;
  1596. bool is_kmalloc = true;
  1597. /* safety checks */
  1598. if (desc_id >= QUERY_DESC_IDN_MAX)
  1599. return -EINVAL;
  1600. buff_len = ufs_query_desc_max_size[desc_id];
  1601. if ((param_offset + param_size) > buff_len)
  1602. return -EINVAL;
  1603. if (!param_offset && (param_size == buff_len)) {
  1604. /* memory space already available to hold full descriptor */
  1605. desc_buf = param_read_buf;
  1606. is_kmalloc = false;
  1607. } else {
  1608. /* allocate memory to hold full descriptor */
  1609. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  1610. if (!desc_buf)
  1611. return -ENOMEM;
  1612. }
  1613. ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
  1614. desc_id, desc_index, 0, desc_buf,
  1615. &buff_len);
  1616. if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
  1617. (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
  1618. ufs_query_desc_max_size[desc_id])
  1619. || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
  1620. dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
  1621. __func__, desc_id, param_offset, buff_len, ret);
  1622. if (!ret)
  1623. ret = -EINVAL;
  1624. goto out;
  1625. }
  1626. if (is_kmalloc)
  1627. memcpy(param_read_buf, &desc_buf[param_offset], param_size);
  1628. out:
  1629. if (is_kmalloc)
  1630. kfree(desc_buf);
  1631. return ret;
  1632. }
  1633. static inline int ufshcd_read_desc(struct ufs_hba *hba,
  1634. enum desc_idn desc_id,
  1635. int desc_index,
  1636. u8 *buf,
  1637. u32 size)
  1638. {
  1639. return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
  1640. }
  1641. static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
  1642. u8 *buf,
  1643. u32 size)
  1644. {
  1645. return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
  1646. }
  1647. /**
  1648. * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
  1649. * @hba: Pointer to adapter instance
  1650. * @lun: lun id
  1651. * @param_offset: offset of the parameter to read
  1652. * @param_read_buf: pointer to buffer where parameter would be read
  1653. * @param_size: sizeof(param_read_buf)
  1654. *
  1655. * Return 0 in case of success, non-zero otherwise
  1656. */
  1657. static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
  1658. int lun,
  1659. enum unit_desc_param param_offset,
  1660. u8 *param_read_buf,
  1661. u32 param_size)
  1662. {
  1663. /*
  1664. * Unit descriptors are only available for general purpose LUs (LUN id
  1665. * from 0 to 7) and RPMB Well known LU.
  1666. */
  1667. if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
  1668. return -EOPNOTSUPP;
  1669. return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
  1670. param_offset, param_read_buf, param_size);
  1671. }
  1672. /**
  1673. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  1674. * @hba: per adapter instance
  1675. *
  1676. * 1. Allocate DMA memory for Command Descriptor array
  1677. * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
  1678. * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
  1679. * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
  1680. * (UTMRDL)
  1681. * 4. Allocate memory for local reference block(lrb).
  1682. *
  1683. * Returns 0 for success, non-zero in case of failure
  1684. */
  1685. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  1686. {
  1687. size_t utmrdl_size, utrdl_size, ucdl_size;
  1688. /* Allocate memory for UTP command descriptors */
  1689. ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  1690. hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
  1691. ucdl_size,
  1692. &hba->ucdl_dma_addr,
  1693. GFP_KERNEL);
  1694. /*
  1695. * UFSHCI requires UTP command descriptor to be 128 byte aligned.
  1696. * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
  1697. * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
  1698. * be aligned to 128 bytes as well
  1699. */
  1700. if (!hba->ucdl_base_addr ||
  1701. WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
  1702. dev_err(hba->dev,
  1703. "Command Descriptor Memory allocation failed\n");
  1704. goto out;
  1705. }
  1706. /*
  1707. * Allocate memory for UTP Transfer descriptors
  1708. * UFSHCI requires 1024 byte alignment of UTRD
  1709. */
  1710. utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  1711. hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
  1712. utrdl_size,
  1713. &hba->utrdl_dma_addr,
  1714. GFP_KERNEL);
  1715. if (!hba->utrdl_base_addr ||
  1716. WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
  1717. dev_err(hba->dev,
  1718. "Transfer Descriptor Memory allocation failed\n");
  1719. goto out;
  1720. }
  1721. /*
  1722. * Allocate memory for UTP Task Management descriptors
  1723. * UFSHCI requires 1024 byte alignment of UTMRD
  1724. */
  1725. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  1726. hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
  1727. utmrdl_size,
  1728. &hba->utmrdl_dma_addr,
  1729. GFP_KERNEL);
  1730. if (!hba->utmrdl_base_addr ||
  1731. WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
  1732. dev_err(hba->dev,
  1733. "Task Management Descriptor Memory allocation failed\n");
  1734. goto out;
  1735. }
  1736. /* Allocate memory for local reference block */
  1737. hba->lrb = devm_kzalloc(hba->dev,
  1738. hba->nutrs * sizeof(struct ufshcd_lrb),
  1739. GFP_KERNEL);
  1740. if (!hba->lrb) {
  1741. dev_err(hba->dev, "LRB Memory allocation failed\n");
  1742. goto out;
  1743. }
  1744. return 0;
  1745. out:
  1746. return -ENOMEM;
  1747. }
  1748. /**
  1749. * ufshcd_host_memory_configure - configure local reference block with
  1750. * memory offsets
  1751. * @hba: per adapter instance
  1752. *
  1753. * Configure Host memory space
  1754. * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
  1755. * address.
  1756. * 2. Update each UTRD with Response UPIU offset, Response UPIU length
  1757. * and PRDT offset.
  1758. * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
  1759. * into local reference block.
  1760. */
  1761. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  1762. {
  1763. struct utp_transfer_cmd_desc *cmd_descp;
  1764. struct utp_transfer_req_desc *utrdlp;
  1765. dma_addr_t cmd_desc_dma_addr;
  1766. dma_addr_t cmd_desc_element_addr;
  1767. u16 response_offset;
  1768. u16 prdt_offset;
  1769. int cmd_desc_size;
  1770. int i;
  1771. utrdlp = hba->utrdl_base_addr;
  1772. cmd_descp = hba->ucdl_base_addr;
  1773. response_offset =
  1774. offsetof(struct utp_transfer_cmd_desc, response_upiu);
  1775. prdt_offset =
  1776. offsetof(struct utp_transfer_cmd_desc, prd_table);
  1777. cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
  1778. cmd_desc_dma_addr = hba->ucdl_dma_addr;
  1779. for (i = 0; i < hba->nutrs; i++) {
  1780. /* Configure UTRD with command descriptor base address */
  1781. cmd_desc_element_addr =
  1782. (cmd_desc_dma_addr + (cmd_desc_size * i));
  1783. utrdlp[i].command_desc_base_addr_lo =
  1784. cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
  1785. utrdlp[i].command_desc_base_addr_hi =
  1786. cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
  1787. /* Response upiu and prdt offset should be in double words */
  1788. utrdlp[i].response_upiu_offset =
  1789. cpu_to_le16((response_offset >> 2));
  1790. utrdlp[i].prd_table_offset =
  1791. cpu_to_le16((prdt_offset >> 2));
  1792. utrdlp[i].response_upiu_length =
  1793. cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  1794. hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
  1795. hba->lrb[i].ucd_req_ptr =
  1796. (struct utp_upiu_req *)(cmd_descp + i);
  1797. hba->lrb[i].ucd_rsp_ptr =
  1798. (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
  1799. hba->lrb[i].ucd_prdt_ptr =
  1800. (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
  1801. }
  1802. }
  1803. /**
  1804. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  1805. * @hba: per adapter instance
  1806. *
  1807. * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
  1808. * in order to initialize the Unipro link startup procedure.
  1809. * Once the Unipro links are up, the device connected to the controller
  1810. * is detected.
  1811. *
  1812. * Returns 0 on success, non-zero value on failure
  1813. */
  1814. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  1815. {
  1816. struct uic_command uic_cmd = {0};
  1817. int ret;
  1818. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  1819. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  1820. if (ret)
  1821. dev_err(hba->dev,
  1822. "dme-link-startup: error code %d\n", ret);
  1823. return ret;
  1824. }
  1825. static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
  1826. {
  1827. #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
  1828. unsigned long min_sleep_time_us;
  1829. if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
  1830. return;
  1831. /*
  1832. * last_dme_cmd_tstamp will be 0 only for 1st call to
  1833. * this function
  1834. */
  1835. if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
  1836. min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
  1837. } else {
  1838. unsigned long delta =
  1839. (unsigned long) ktime_to_us(
  1840. ktime_sub(ktime_get(),
  1841. hba->last_dme_cmd_tstamp));
  1842. if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
  1843. min_sleep_time_us =
  1844. MIN_DELAY_BEFORE_DME_CMDS_US - delta;
  1845. else
  1846. return; /* no more delay required */
  1847. }
  1848. /* allow sleep for extra 50us if needed */
  1849. usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
  1850. }
  1851. /**
  1852. * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
  1853. * @hba: per adapter instance
  1854. * @attr_sel: uic command argument1
  1855. * @attr_set: attribute set type as uic command argument2
  1856. * @mib_val: setting value as uic command argument3
  1857. * @peer: indicate whether peer or local
  1858. *
  1859. * Returns 0 on success, non-zero value on failure
  1860. */
  1861. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
  1862. u8 attr_set, u32 mib_val, u8 peer)
  1863. {
  1864. struct uic_command uic_cmd = {0};
  1865. static const char *const action[] = {
  1866. "dme-set",
  1867. "dme-peer-set"
  1868. };
  1869. const char *set = action[!!peer];
  1870. int ret;
  1871. uic_cmd.command = peer ?
  1872. UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
  1873. uic_cmd.argument1 = attr_sel;
  1874. uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
  1875. uic_cmd.argument3 = mib_val;
  1876. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  1877. if (ret)
  1878. dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
  1879. set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
  1880. return ret;
  1881. }
  1882. EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
  1883. /**
  1884. * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
  1885. * @hba: per adapter instance
  1886. * @attr_sel: uic command argument1
  1887. * @mib_val: the value of the attribute as returned by the UIC command
  1888. * @peer: indicate whether peer or local
  1889. *
  1890. * Returns 0 on success, non-zero value on failure
  1891. */
  1892. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  1893. u32 *mib_val, u8 peer)
  1894. {
  1895. struct uic_command uic_cmd = {0};
  1896. static const char *const action[] = {
  1897. "dme-get",
  1898. "dme-peer-get"
  1899. };
  1900. const char *get = action[!!peer];
  1901. int ret;
  1902. struct ufs_pa_layer_attr orig_pwr_info;
  1903. struct ufs_pa_layer_attr temp_pwr_info;
  1904. bool pwr_mode_change = false;
  1905. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
  1906. orig_pwr_info = hba->pwr_info;
  1907. temp_pwr_info = orig_pwr_info;
  1908. if (orig_pwr_info.pwr_tx == FAST_MODE ||
  1909. orig_pwr_info.pwr_rx == FAST_MODE) {
  1910. temp_pwr_info.pwr_tx = FASTAUTO_MODE;
  1911. temp_pwr_info.pwr_rx = FASTAUTO_MODE;
  1912. pwr_mode_change = true;
  1913. } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
  1914. orig_pwr_info.pwr_rx == SLOW_MODE) {
  1915. temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
  1916. temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
  1917. pwr_mode_change = true;
  1918. }
  1919. if (pwr_mode_change) {
  1920. ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
  1921. if (ret)
  1922. goto out;
  1923. }
  1924. }
  1925. uic_cmd.command = peer ?
  1926. UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
  1927. uic_cmd.argument1 = attr_sel;
  1928. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  1929. if (ret) {
  1930. dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
  1931. get, UIC_GET_ATTR_ID(attr_sel), ret);
  1932. goto out;
  1933. }
  1934. if (mib_val)
  1935. *mib_val = uic_cmd.argument3;
  1936. if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
  1937. && pwr_mode_change)
  1938. ufshcd_change_power_mode(hba, &orig_pwr_info);
  1939. out:
  1940. return ret;
  1941. }
  1942. EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
  1943. /**
  1944. * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  1945. * state) and waits for it to take effect.
  1946. *
  1947. * @hba: per adapter instance
  1948. * @cmd: UIC command to execute
  1949. *
  1950. * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
  1951. * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
  1952. * and device UniPro link and hence it's final completion would be indicated by
  1953. * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
  1954. * addition to normal UIC command completion Status (UCCS). This function only
  1955. * returns after the relevant status bits indicate the completion.
  1956. *
  1957. * Returns 0 on success, non-zero value on failure
  1958. */
  1959. static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
  1960. {
  1961. struct completion uic_async_done;
  1962. unsigned long flags;
  1963. u8 status;
  1964. int ret;
  1965. mutex_lock(&hba->uic_cmd_mutex);
  1966. init_completion(&uic_async_done);
  1967. ufshcd_add_delay_before_dme_cmd(hba);
  1968. spin_lock_irqsave(hba->host->host_lock, flags);
  1969. hba->uic_async_done = &uic_async_done;
  1970. ret = __ufshcd_send_uic_cmd(hba, cmd);
  1971. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1972. if (ret) {
  1973. dev_err(hba->dev,
  1974. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  1975. cmd->command, cmd->argument3, ret);
  1976. goto out;
  1977. }
  1978. ret = ufshcd_wait_for_uic_cmd(hba, cmd);
  1979. if (ret) {
  1980. dev_err(hba->dev,
  1981. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  1982. cmd->command, cmd->argument3, ret);
  1983. goto out;
  1984. }
  1985. if (!wait_for_completion_timeout(hba->uic_async_done,
  1986. msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
  1987. dev_err(hba->dev,
  1988. "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
  1989. cmd->command, cmd->argument3);
  1990. ret = -ETIMEDOUT;
  1991. goto out;
  1992. }
  1993. status = ufshcd_get_upmcrs(hba);
  1994. if (status != PWR_LOCAL) {
  1995. dev_err(hba->dev,
  1996. "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n",
  1997. cmd->command, status);
  1998. ret = (status != PWR_OK) ? status : -1;
  1999. }
  2000. out:
  2001. spin_lock_irqsave(hba->host->host_lock, flags);
  2002. hba->uic_async_done = NULL;
  2003. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2004. mutex_unlock(&hba->uic_cmd_mutex);
  2005. return ret;
  2006. }
  2007. /**
  2008. * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
  2009. * using DME_SET primitives.
  2010. * @hba: per adapter instance
  2011. * @mode: powr mode value
  2012. *
  2013. * Returns 0 on success, non-zero value on failure
  2014. */
  2015. static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
  2016. {
  2017. struct uic_command uic_cmd = {0};
  2018. int ret;
  2019. if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
  2020. ret = ufshcd_dme_set(hba,
  2021. UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
  2022. if (ret) {
  2023. dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
  2024. __func__, ret);
  2025. goto out;
  2026. }
  2027. }
  2028. uic_cmd.command = UIC_CMD_DME_SET;
  2029. uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
  2030. uic_cmd.argument3 = mode;
  2031. ufshcd_hold(hba, false);
  2032. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  2033. ufshcd_release(hba);
  2034. out:
  2035. return ret;
  2036. }
  2037. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  2038. {
  2039. struct uic_command uic_cmd = {0};
  2040. uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
  2041. return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  2042. }
  2043. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
  2044. {
  2045. struct uic_command uic_cmd = {0};
  2046. int ret;
  2047. uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
  2048. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  2049. if (ret) {
  2050. ufshcd_set_link_off(hba);
  2051. ret = ufshcd_host_reset_and_restore(hba);
  2052. }
  2053. return ret;
  2054. }
  2055. /**
  2056. * ufshcd_init_pwr_info - setting the POR (power on reset)
  2057. * values in hba power info
  2058. * @hba: per-adapter instance
  2059. */
  2060. static void ufshcd_init_pwr_info(struct ufs_hba *hba)
  2061. {
  2062. hba->pwr_info.gear_rx = UFS_PWM_G1;
  2063. hba->pwr_info.gear_tx = UFS_PWM_G1;
  2064. hba->pwr_info.lane_rx = 1;
  2065. hba->pwr_info.lane_tx = 1;
  2066. hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
  2067. hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
  2068. hba->pwr_info.hs_rate = 0;
  2069. }
  2070. /**
  2071. * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
  2072. * @hba: per-adapter instance
  2073. */
  2074. static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
  2075. {
  2076. struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
  2077. if (hba->max_pwr_info.is_valid)
  2078. return 0;
  2079. pwr_info->pwr_tx = FASTAUTO_MODE;
  2080. pwr_info->pwr_rx = FASTAUTO_MODE;
  2081. pwr_info->hs_rate = PA_HS_MODE_B;
  2082. /* Get the connected lane count */
  2083. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
  2084. &pwr_info->lane_rx);
  2085. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  2086. &pwr_info->lane_tx);
  2087. if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
  2088. dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
  2089. __func__,
  2090. pwr_info->lane_rx,
  2091. pwr_info->lane_tx);
  2092. return -EINVAL;
  2093. }
  2094. /*
  2095. * First, get the maximum gears of HS speed.
  2096. * If a zero value, it means there is no HSGEAR capability.
  2097. * Then, get the maximum gears of PWM speed.
  2098. */
  2099. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
  2100. if (!pwr_info->gear_rx) {
  2101. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  2102. &pwr_info->gear_rx);
  2103. if (!pwr_info->gear_rx) {
  2104. dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
  2105. __func__, pwr_info->gear_rx);
  2106. return -EINVAL;
  2107. }
  2108. pwr_info->pwr_rx = SLOWAUTO_MODE;
  2109. }
  2110. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
  2111. &pwr_info->gear_tx);
  2112. if (!pwr_info->gear_tx) {
  2113. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  2114. &pwr_info->gear_tx);
  2115. if (!pwr_info->gear_tx) {
  2116. dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
  2117. __func__, pwr_info->gear_tx);
  2118. return -EINVAL;
  2119. }
  2120. pwr_info->pwr_tx = SLOWAUTO_MODE;
  2121. }
  2122. hba->max_pwr_info.is_valid = true;
  2123. return 0;
  2124. }
  2125. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  2126. struct ufs_pa_layer_attr *pwr_mode)
  2127. {
  2128. int ret;
  2129. /* if already configured to the requested pwr_mode */
  2130. if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
  2131. pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
  2132. pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
  2133. pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
  2134. pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
  2135. pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
  2136. pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
  2137. dev_dbg(hba->dev, "%s: power already configured\n", __func__);
  2138. return 0;
  2139. }
  2140. /*
  2141. * Configure attributes for power mode change with below.
  2142. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
  2143. * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
  2144. * - PA_HSSERIES
  2145. */
  2146. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
  2147. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
  2148. pwr_mode->lane_rx);
  2149. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  2150. pwr_mode->pwr_rx == FAST_MODE)
  2151. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
  2152. else
  2153. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
  2154. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
  2155. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
  2156. pwr_mode->lane_tx);
  2157. if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
  2158. pwr_mode->pwr_tx == FAST_MODE)
  2159. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
  2160. else
  2161. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
  2162. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  2163. pwr_mode->pwr_tx == FASTAUTO_MODE ||
  2164. pwr_mode->pwr_rx == FAST_MODE ||
  2165. pwr_mode->pwr_tx == FAST_MODE)
  2166. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
  2167. pwr_mode->hs_rate);
  2168. ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
  2169. | pwr_mode->pwr_tx);
  2170. if (ret) {
  2171. dev_err(hba->dev,
  2172. "%s: power mode change failed %d\n", __func__, ret);
  2173. } else {
  2174. if (hba->vops && hba->vops->pwr_change_notify)
  2175. hba->vops->pwr_change_notify(hba,
  2176. POST_CHANGE, NULL, pwr_mode);
  2177. memcpy(&hba->pwr_info, pwr_mode,
  2178. sizeof(struct ufs_pa_layer_attr));
  2179. }
  2180. return ret;
  2181. }
  2182. /**
  2183. * ufshcd_config_pwr_mode - configure a new power mode
  2184. * @hba: per-adapter instance
  2185. * @desired_pwr_mode: desired power configuration
  2186. */
  2187. static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  2188. struct ufs_pa_layer_attr *desired_pwr_mode)
  2189. {
  2190. struct ufs_pa_layer_attr final_params = { 0 };
  2191. int ret;
  2192. if (hba->vops && hba->vops->pwr_change_notify)
  2193. hba->vops->pwr_change_notify(hba,
  2194. PRE_CHANGE, desired_pwr_mode, &final_params);
  2195. else
  2196. memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
  2197. ret = ufshcd_change_power_mode(hba, &final_params);
  2198. return ret;
  2199. }
  2200. /**
  2201. * ufshcd_complete_dev_init() - checks device readiness
  2202. * hba: per-adapter instance
  2203. *
  2204. * Set fDeviceInit flag and poll until device toggles it.
  2205. */
  2206. static int ufshcd_complete_dev_init(struct ufs_hba *hba)
  2207. {
  2208. int i, retries, err = 0;
  2209. bool flag_res = 1;
  2210. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2211. /* Set the fDeviceInit flag */
  2212. err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  2213. QUERY_FLAG_IDN_FDEVICEINIT, NULL);
  2214. if (!err || err == -ETIMEDOUT)
  2215. break;
  2216. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  2217. }
  2218. if (err) {
  2219. dev_err(hba->dev,
  2220. "%s setting fDeviceInit flag failed with error %d\n",
  2221. __func__, err);
  2222. goto out;
  2223. }
  2224. /* poll for max. 100 iterations for fDeviceInit flag to clear */
  2225. for (i = 0; i < 100 && !err && flag_res; i++) {
  2226. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2227. err = ufshcd_query_flag(hba,
  2228. UPIU_QUERY_OPCODE_READ_FLAG,
  2229. QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
  2230. if (!err || err == -ETIMEDOUT)
  2231. break;
  2232. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
  2233. err);
  2234. }
  2235. }
  2236. if (err)
  2237. dev_err(hba->dev,
  2238. "%s reading fDeviceInit flag failed with error %d\n",
  2239. __func__, err);
  2240. else if (flag_res)
  2241. dev_err(hba->dev,
  2242. "%s fDeviceInit was not cleared by the device\n",
  2243. __func__);
  2244. out:
  2245. return err;
  2246. }
  2247. /**
  2248. * ufshcd_make_hba_operational - Make UFS controller operational
  2249. * @hba: per adapter instance
  2250. *
  2251. * To bring UFS host controller to operational state,
  2252. * 1. Enable required interrupts
  2253. * 2. Configure interrupt aggregation
  2254. * 3. Program UTRL and UTMRL base addres
  2255. * 4. Configure run-stop-registers
  2256. *
  2257. * Returns 0 on success, non-zero value on failure
  2258. */
  2259. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  2260. {
  2261. int err = 0;
  2262. u32 reg;
  2263. /* Enable required interrupts */
  2264. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  2265. /* Configure interrupt aggregation */
  2266. if (ufshcd_is_intr_aggr_allowed(hba))
  2267. ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
  2268. else
  2269. ufshcd_disable_intr_aggr(hba);
  2270. /* Configure UTRL and UTMRL base address registers */
  2271. ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
  2272. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  2273. ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
  2274. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  2275. ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
  2276. REG_UTP_TASK_REQ_LIST_BASE_L);
  2277. ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
  2278. REG_UTP_TASK_REQ_LIST_BASE_H);
  2279. /*
  2280. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  2281. * DEI, HEI bits must be 0
  2282. */
  2283. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  2284. if (!(ufshcd_get_lists_status(reg))) {
  2285. ufshcd_enable_run_stop_reg(hba);
  2286. } else {
  2287. dev_err(hba->dev,
  2288. "Host controller not ready to process requests");
  2289. err = -EIO;
  2290. goto out;
  2291. }
  2292. out:
  2293. return err;
  2294. }
  2295. /**
  2296. * ufshcd_hba_enable - initialize the controller
  2297. * @hba: per adapter instance
  2298. *
  2299. * The controller resets itself and controller firmware initialization
  2300. * sequence kicks off. When controller is ready it will set
  2301. * the Host Controller Enable bit to 1.
  2302. *
  2303. * Returns 0 on success, non-zero value on failure
  2304. */
  2305. static int ufshcd_hba_enable(struct ufs_hba *hba)
  2306. {
  2307. int retry;
  2308. /*
  2309. * msleep of 1 and 5 used in this function might result in msleep(20),
  2310. * but it was necessary to send the UFS FPGA to reset mode during
  2311. * development and testing of this driver. msleep can be changed to
  2312. * mdelay and retry count can be reduced based on the controller.
  2313. */
  2314. if (!ufshcd_is_hba_active(hba)) {
  2315. /* change controller state to "reset state" */
  2316. ufshcd_hba_stop(hba);
  2317. /*
  2318. * This delay is based on the testing done with UFS host
  2319. * controller FPGA. The delay can be changed based on the
  2320. * host controller used.
  2321. */
  2322. msleep(5);
  2323. }
  2324. /* UniPro link is disabled at this point */
  2325. ufshcd_set_link_off(hba);
  2326. if (hba->vops && hba->vops->hce_enable_notify)
  2327. hba->vops->hce_enable_notify(hba, PRE_CHANGE);
  2328. /* start controller initialization sequence */
  2329. ufshcd_hba_start(hba);
  2330. /*
  2331. * To initialize a UFS host controller HCE bit must be set to 1.
  2332. * During initialization the HCE bit value changes from 1->0->1.
  2333. * When the host controller completes initialization sequence
  2334. * it sets the value of HCE bit to 1. The same HCE bit is read back
  2335. * to check if the controller has completed initialization sequence.
  2336. * So without this delay the value HCE = 1, set in the previous
  2337. * instruction might be read back.
  2338. * This delay can be changed based on the controller.
  2339. */
  2340. msleep(1);
  2341. /* wait for the host controller to complete initialization */
  2342. retry = 10;
  2343. while (ufshcd_is_hba_active(hba)) {
  2344. if (retry) {
  2345. retry--;
  2346. } else {
  2347. dev_err(hba->dev,
  2348. "Controller enable failed\n");
  2349. return -EIO;
  2350. }
  2351. msleep(5);
  2352. }
  2353. /* enable UIC related interrupts */
  2354. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  2355. if (hba->vops && hba->vops->hce_enable_notify)
  2356. hba->vops->hce_enable_notify(hba, POST_CHANGE);
  2357. return 0;
  2358. }
  2359. static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
  2360. {
  2361. int tx_lanes, i, err = 0;
  2362. if (!peer)
  2363. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  2364. &tx_lanes);
  2365. else
  2366. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  2367. &tx_lanes);
  2368. for (i = 0; i < tx_lanes; i++) {
  2369. if (!peer)
  2370. err = ufshcd_dme_set(hba,
  2371. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  2372. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  2373. 0);
  2374. else
  2375. err = ufshcd_dme_peer_set(hba,
  2376. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  2377. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  2378. 0);
  2379. if (err) {
  2380. dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
  2381. __func__, peer, i, err);
  2382. break;
  2383. }
  2384. }
  2385. return err;
  2386. }
  2387. static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
  2388. {
  2389. return ufshcd_disable_tx_lcc(hba, true);
  2390. }
  2391. /**
  2392. * ufshcd_link_startup - Initialize unipro link startup
  2393. * @hba: per adapter instance
  2394. *
  2395. * Returns 0 for success, non-zero in case of failure
  2396. */
  2397. static int ufshcd_link_startup(struct ufs_hba *hba)
  2398. {
  2399. int ret;
  2400. int retries = DME_LINKSTARTUP_RETRIES;
  2401. do {
  2402. if (hba->vops && hba->vops->link_startup_notify)
  2403. hba->vops->link_startup_notify(hba, PRE_CHANGE);
  2404. ret = ufshcd_dme_link_startup(hba);
  2405. /* check if device is detected by inter-connect layer */
  2406. if (!ret && !ufshcd_is_device_present(hba)) {
  2407. dev_err(hba->dev, "%s: Device not present\n", __func__);
  2408. ret = -ENXIO;
  2409. goto out;
  2410. }
  2411. /*
  2412. * DME link lost indication is only received when link is up,
  2413. * but we can't be sure if the link is up until link startup
  2414. * succeeds. So reset the local Uni-Pro and try again.
  2415. */
  2416. if (ret && ufshcd_hba_enable(hba))
  2417. goto out;
  2418. } while (ret && retries--);
  2419. if (ret)
  2420. /* failed to get the link up... retire */
  2421. goto out;
  2422. if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
  2423. ret = ufshcd_disable_device_tx_lcc(hba);
  2424. if (ret)
  2425. goto out;
  2426. }
  2427. /* Include any host controller configuration via UIC commands */
  2428. if (hba->vops && hba->vops->link_startup_notify) {
  2429. ret = hba->vops->link_startup_notify(hba, POST_CHANGE);
  2430. if (ret)
  2431. goto out;
  2432. }
  2433. ret = ufshcd_make_hba_operational(hba);
  2434. out:
  2435. if (ret)
  2436. dev_err(hba->dev, "link startup failed %d\n", ret);
  2437. return ret;
  2438. }
  2439. /**
  2440. * ufshcd_verify_dev_init() - Verify device initialization
  2441. * @hba: per-adapter instance
  2442. *
  2443. * Send NOP OUT UPIU and wait for NOP IN response to check whether the
  2444. * device Transport Protocol (UTP) layer is ready after a reset.
  2445. * If the UTP layer at the device side is not initialized, it may
  2446. * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
  2447. * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
  2448. */
  2449. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  2450. {
  2451. int err = 0;
  2452. int retries;
  2453. ufshcd_hold(hba, false);
  2454. mutex_lock(&hba->dev_cmd.lock);
  2455. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  2456. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  2457. NOP_OUT_TIMEOUT);
  2458. if (!err || err == -ETIMEDOUT)
  2459. break;
  2460. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  2461. }
  2462. mutex_unlock(&hba->dev_cmd.lock);
  2463. ufshcd_release(hba);
  2464. if (err)
  2465. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  2466. return err;
  2467. }
  2468. /**
  2469. * ufshcd_set_queue_depth - set lun queue depth
  2470. * @sdev: pointer to SCSI device
  2471. *
  2472. * Read bLUQueueDepth value and activate scsi tagged command
  2473. * queueing. For WLUN, queue depth is set to 1. For best-effort
  2474. * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
  2475. * value that host can queue.
  2476. */
  2477. static void ufshcd_set_queue_depth(struct scsi_device *sdev)
  2478. {
  2479. int ret = 0;
  2480. u8 lun_qdepth;
  2481. struct ufs_hba *hba;
  2482. hba = shost_priv(sdev->host);
  2483. lun_qdepth = hba->nutrs;
  2484. ret = ufshcd_read_unit_desc_param(hba,
  2485. ufshcd_scsi_to_upiu_lun(sdev->lun),
  2486. UNIT_DESC_PARAM_LU_Q_DEPTH,
  2487. &lun_qdepth,
  2488. sizeof(lun_qdepth));
  2489. /* Some WLUN doesn't support unit descriptor */
  2490. if (ret == -EOPNOTSUPP)
  2491. lun_qdepth = 1;
  2492. else if (!lun_qdepth)
  2493. /* eventually, we can figure out the real queue depth */
  2494. lun_qdepth = hba->nutrs;
  2495. else
  2496. lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
  2497. dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
  2498. __func__, lun_qdepth);
  2499. scsi_change_queue_depth(sdev, lun_qdepth);
  2500. }
  2501. /*
  2502. * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
  2503. * @hba: per-adapter instance
  2504. * @lun: UFS device lun id
  2505. * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
  2506. *
  2507. * Returns 0 in case of success and b_lu_write_protect status would be returned
  2508. * @b_lu_write_protect parameter.
  2509. * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
  2510. * Returns -EINVAL in case of invalid parameters passed to this function.
  2511. */
  2512. static int ufshcd_get_lu_wp(struct ufs_hba *hba,
  2513. u8 lun,
  2514. u8 *b_lu_write_protect)
  2515. {
  2516. int ret;
  2517. if (!b_lu_write_protect)
  2518. ret = -EINVAL;
  2519. /*
  2520. * According to UFS device spec, RPMB LU can't be write
  2521. * protected so skip reading bLUWriteProtect parameter for
  2522. * it. For other W-LUs, UNIT DESCRIPTOR is not available.
  2523. */
  2524. else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
  2525. ret = -ENOTSUPP;
  2526. else
  2527. ret = ufshcd_read_unit_desc_param(hba,
  2528. lun,
  2529. UNIT_DESC_PARAM_LU_WR_PROTECT,
  2530. b_lu_write_protect,
  2531. sizeof(*b_lu_write_protect));
  2532. return ret;
  2533. }
  2534. /**
  2535. * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
  2536. * status
  2537. * @hba: per-adapter instance
  2538. * @sdev: pointer to SCSI device
  2539. *
  2540. */
  2541. static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
  2542. struct scsi_device *sdev)
  2543. {
  2544. if (hba->dev_info.f_power_on_wp_en &&
  2545. !hba->dev_info.is_lu_power_on_wp) {
  2546. u8 b_lu_write_protect;
  2547. if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
  2548. &b_lu_write_protect) &&
  2549. (b_lu_write_protect == UFS_LU_POWER_ON_WP))
  2550. hba->dev_info.is_lu_power_on_wp = true;
  2551. }
  2552. }
  2553. /**
  2554. * ufshcd_slave_alloc - handle initial SCSI device configurations
  2555. * @sdev: pointer to SCSI device
  2556. *
  2557. * Returns success
  2558. */
  2559. static int ufshcd_slave_alloc(struct scsi_device *sdev)
  2560. {
  2561. struct ufs_hba *hba;
  2562. hba = shost_priv(sdev->host);
  2563. /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
  2564. sdev->use_10_for_ms = 1;
  2565. /* allow SCSI layer to restart the device in case of errors */
  2566. sdev->allow_restart = 1;
  2567. /* REPORT SUPPORTED OPERATION CODES is not supported */
  2568. sdev->no_report_opcodes = 1;
  2569. ufshcd_set_queue_depth(sdev);
  2570. ufshcd_get_lu_power_on_wp_status(hba, sdev);
  2571. return 0;
  2572. }
  2573. /**
  2574. * ufshcd_change_queue_depth - change queue depth
  2575. * @sdev: pointer to SCSI device
  2576. * @depth: required depth to set
  2577. *
  2578. * Change queue depth and make sure the max. limits are not crossed.
  2579. */
  2580. static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
  2581. {
  2582. struct ufs_hba *hba = shost_priv(sdev->host);
  2583. if (depth > hba->nutrs)
  2584. depth = hba->nutrs;
  2585. return scsi_change_queue_depth(sdev, depth);
  2586. }
  2587. /**
  2588. * ufshcd_slave_configure - adjust SCSI device configurations
  2589. * @sdev: pointer to SCSI device
  2590. */
  2591. static int ufshcd_slave_configure(struct scsi_device *sdev)
  2592. {
  2593. struct request_queue *q = sdev->request_queue;
  2594. blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
  2595. blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
  2596. return 0;
  2597. }
  2598. /**
  2599. * ufshcd_slave_destroy - remove SCSI device configurations
  2600. * @sdev: pointer to SCSI device
  2601. */
  2602. static void ufshcd_slave_destroy(struct scsi_device *sdev)
  2603. {
  2604. struct ufs_hba *hba;
  2605. hba = shost_priv(sdev->host);
  2606. /* Drop the reference as it won't be needed anymore */
  2607. if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
  2608. unsigned long flags;
  2609. spin_lock_irqsave(hba->host->host_lock, flags);
  2610. hba->sdev_ufs_device = NULL;
  2611. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2612. }
  2613. }
  2614. /**
  2615. * ufshcd_task_req_compl - handle task management request completion
  2616. * @hba: per adapter instance
  2617. * @index: index of the completed request
  2618. * @resp: task management service response
  2619. *
  2620. * Returns non-zero value on error, zero on success
  2621. */
  2622. static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
  2623. {
  2624. struct utp_task_req_desc *task_req_descp;
  2625. struct utp_upiu_task_rsp *task_rsp_upiup;
  2626. unsigned long flags;
  2627. int ocs_value;
  2628. int task_result;
  2629. spin_lock_irqsave(hba->host->host_lock, flags);
  2630. /* Clear completed tasks from outstanding_tasks */
  2631. __clear_bit(index, &hba->outstanding_tasks);
  2632. task_req_descp = hba->utmrdl_base_addr;
  2633. ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
  2634. if (ocs_value == OCS_SUCCESS) {
  2635. task_rsp_upiup = (struct utp_upiu_task_rsp *)
  2636. task_req_descp[index].task_rsp_upiu;
  2637. task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
  2638. task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
  2639. if (resp)
  2640. *resp = (u8)task_result;
  2641. } else {
  2642. dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
  2643. __func__, ocs_value);
  2644. }
  2645. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2646. return ocs_value;
  2647. }
  2648. /**
  2649. * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
  2650. * @lrb: pointer to local reference block of completed command
  2651. * @scsi_status: SCSI command status
  2652. *
  2653. * Returns value base on SCSI command status
  2654. */
  2655. static inline int
  2656. ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
  2657. {
  2658. int result = 0;
  2659. switch (scsi_status) {
  2660. case SAM_STAT_CHECK_CONDITION:
  2661. ufshcd_copy_sense_data(lrbp);
  2662. case SAM_STAT_GOOD:
  2663. result |= DID_OK << 16 |
  2664. COMMAND_COMPLETE << 8 |
  2665. scsi_status;
  2666. break;
  2667. case SAM_STAT_TASK_SET_FULL:
  2668. case SAM_STAT_BUSY:
  2669. case SAM_STAT_TASK_ABORTED:
  2670. ufshcd_copy_sense_data(lrbp);
  2671. result |= scsi_status;
  2672. break;
  2673. default:
  2674. result |= DID_ERROR << 16;
  2675. break;
  2676. } /* end of switch */
  2677. return result;
  2678. }
  2679. /**
  2680. * ufshcd_transfer_rsp_status - Get overall status of the response
  2681. * @hba: per adapter instance
  2682. * @lrb: pointer to local reference block of completed command
  2683. *
  2684. * Returns result of the command to notify SCSI midlayer
  2685. */
  2686. static inline int
  2687. ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2688. {
  2689. int result = 0;
  2690. int scsi_status;
  2691. int ocs;
  2692. /* overall command status of utrd */
  2693. ocs = ufshcd_get_tr_ocs(lrbp);
  2694. switch (ocs) {
  2695. case OCS_SUCCESS:
  2696. result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  2697. switch (result) {
  2698. case UPIU_TRANSACTION_RESPONSE:
  2699. /*
  2700. * get the response UPIU result to extract
  2701. * the SCSI command status
  2702. */
  2703. result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
  2704. /*
  2705. * get the result based on SCSI status response
  2706. * to notify the SCSI midlayer of the command status
  2707. */
  2708. scsi_status = result & MASK_SCSI_STATUS;
  2709. result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
  2710. if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
  2711. schedule_work(&hba->eeh_work);
  2712. break;
  2713. case UPIU_TRANSACTION_REJECT_UPIU:
  2714. /* TODO: handle Reject UPIU Response */
  2715. result = DID_ERROR << 16;
  2716. dev_err(hba->dev,
  2717. "Reject UPIU not fully implemented\n");
  2718. break;
  2719. default:
  2720. result = DID_ERROR << 16;
  2721. dev_err(hba->dev,
  2722. "Unexpected request response code = %x\n",
  2723. result);
  2724. break;
  2725. }
  2726. break;
  2727. case OCS_ABORTED:
  2728. result |= DID_ABORT << 16;
  2729. break;
  2730. case OCS_INVALID_COMMAND_STATUS:
  2731. result |= DID_REQUEUE << 16;
  2732. break;
  2733. case OCS_INVALID_CMD_TABLE_ATTR:
  2734. case OCS_INVALID_PRDT_ATTR:
  2735. case OCS_MISMATCH_DATA_BUF_SIZE:
  2736. case OCS_MISMATCH_RESP_UPIU_SIZE:
  2737. case OCS_PEER_COMM_FAILURE:
  2738. case OCS_FATAL_ERROR:
  2739. default:
  2740. result |= DID_ERROR << 16;
  2741. dev_err(hba->dev,
  2742. "OCS error from controller = %x\n", ocs);
  2743. break;
  2744. } /* end of switch */
  2745. return result;
  2746. }
  2747. /**
  2748. * ufshcd_uic_cmd_compl - handle completion of uic command
  2749. * @hba: per adapter instance
  2750. * @intr_status: interrupt status generated by the controller
  2751. */
  2752. static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
  2753. {
  2754. if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
  2755. hba->active_uic_cmd->argument2 |=
  2756. ufshcd_get_uic_cmd_result(hba);
  2757. hba->active_uic_cmd->argument3 =
  2758. ufshcd_get_dme_attr_val(hba);
  2759. complete(&hba->active_uic_cmd->done);
  2760. }
  2761. if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
  2762. complete(hba->uic_async_done);
  2763. }
  2764. /**
  2765. * ufshcd_transfer_req_compl - handle SCSI and query command completion
  2766. * @hba: per adapter instance
  2767. */
  2768. static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
  2769. {
  2770. struct ufshcd_lrb *lrbp;
  2771. struct scsi_cmnd *cmd;
  2772. unsigned long completed_reqs;
  2773. u32 tr_doorbell;
  2774. int result;
  2775. int index;
  2776. /* Resetting interrupt aggregation counters first and reading the
  2777. * DOOR_BELL afterward allows us to handle all the completed requests.
  2778. * In order to prevent other interrupts starvation the DB is read once
  2779. * after reset. The down side of this solution is the possibility of
  2780. * false interrupt if device completes another request after resetting
  2781. * aggregation and before reading the DB.
  2782. */
  2783. if (ufshcd_is_intr_aggr_allowed(hba))
  2784. ufshcd_reset_intr_aggr(hba);
  2785. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  2786. completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
  2787. for_each_set_bit(index, &completed_reqs, hba->nutrs) {
  2788. lrbp = &hba->lrb[index];
  2789. cmd = lrbp->cmd;
  2790. if (cmd) {
  2791. result = ufshcd_transfer_rsp_status(hba, lrbp);
  2792. scsi_dma_unmap(cmd);
  2793. cmd->result = result;
  2794. /* Mark completed command as NULL in LRB */
  2795. lrbp->cmd = NULL;
  2796. clear_bit_unlock(index, &hba->lrb_in_use);
  2797. /* Do not touch lrbp after scsi done */
  2798. cmd->scsi_done(cmd);
  2799. __ufshcd_release(hba);
  2800. } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
  2801. if (hba->dev_cmd.complete)
  2802. complete(hba->dev_cmd.complete);
  2803. }
  2804. }
  2805. /* clear corresponding bits of completed commands */
  2806. hba->outstanding_reqs ^= completed_reqs;
  2807. ufshcd_clk_scaling_update_busy(hba);
  2808. /* we might have free'd some tags above */
  2809. wake_up(&hba->dev_cmd.tag_wq);
  2810. }
  2811. /**
  2812. * ufshcd_disable_ee - disable exception event
  2813. * @hba: per-adapter instance
  2814. * @mask: exception event to disable
  2815. *
  2816. * Disables exception event in the device so that the EVENT_ALERT
  2817. * bit is not set.
  2818. *
  2819. * Returns zero on success, non-zero error value on failure.
  2820. */
  2821. static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
  2822. {
  2823. int err = 0;
  2824. u32 val;
  2825. if (!(hba->ee_ctrl_mask & mask))
  2826. goto out;
  2827. val = hba->ee_ctrl_mask & ~mask;
  2828. val &= 0xFFFF; /* 2 bytes */
  2829. err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  2830. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  2831. if (!err)
  2832. hba->ee_ctrl_mask &= ~mask;
  2833. out:
  2834. return err;
  2835. }
  2836. /**
  2837. * ufshcd_enable_ee - enable exception event
  2838. * @hba: per-adapter instance
  2839. * @mask: exception event to enable
  2840. *
  2841. * Enable corresponding exception event in the device to allow
  2842. * device to alert host in critical scenarios.
  2843. *
  2844. * Returns zero on success, non-zero error value on failure.
  2845. */
  2846. static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
  2847. {
  2848. int err = 0;
  2849. u32 val;
  2850. if (hba->ee_ctrl_mask & mask)
  2851. goto out;
  2852. val = hba->ee_ctrl_mask | mask;
  2853. val &= 0xFFFF; /* 2 bytes */
  2854. err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  2855. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  2856. if (!err)
  2857. hba->ee_ctrl_mask |= mask;
  2858. out:
  2859. return err;
  2860. }
  2861. /**
  2862. * ufshcd_enable_auto_bkops - Allow device managed BKOPS
  2863. * @hba: per-adapter instance
  2864. *
  2865. * Allow device to manage background operations on its own. Enabling
  2866. * this might lead to inconsistent latencies during normal data transfers
  2867. * as the device is allowed to manage its own way of handling background
  2868. * operations.
  2869. *
  2870. * Returns zero on success, non-zero on failure.
  2871. */
  2872. static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
  2873. {
  2874. int err = 0;
  2875. if (hba->auto_bkops_enabled)
  2876. goto out;
  2877. err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  2878. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  2879. if (err) {
  2880. dev_err(hba->dev, "%s: failed to enable bkops %d\n",
  2881. __func__, err);
  2882. goto out;
  2883. }
  2884. hba->auto_bkops_enabled = true;
  2885. /* No need of URGENT_BKOPS exception from the device */
  2886. err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  2887. if (err)
  2888. dev_err(hba->dev, "%s: failed to disable exception event %d\n",
  2889. __func__, err);
  2890. out:
  2891. return err;
  2892. }
  2893. /**
  2894. * ufshcd_disable_auto_bkops - block device in doing background operations
  2895. * @hba: per-adapter instance
  2896. *
  2897. * Disabling background operations improves command response latency but
  2898. * has drawback of device moving into critical state where the device is
  2899. * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
  2900. * host is idle so that BKOPS are managed effectively without any negative
  2901. * impacts.
  2902. *
  2903. * Returns zero on success, non-zero on failure.
  2904. */
  2905. static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
  2906. {
  2907. int err = 0;
  2908. if (!hba->auto_bkops_enabled)
  2909. goto out;
  2910. /*
  2911. * If host assisted BKOPs is to be enabled, make sure
  2912. * urgent bkops exception is allowed.
  2913. */
  2914. err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
  2915. if (err) {
  2916. dev_err(hba->dev, "%s: failed to enable exception event %d\n",
  2917. __func__, err);
  2918. goto out;
  2919. }
  2920. err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
  2921. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  2922. if (err) {
  2923. dev_err(hba->dev, "%s: failed to disable bkops %d\n",
  2924. __func__, err);
  2925. ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  2926. goto out;
  2927. }
  2928. hba->auto_bkops_enabled = false;
  2929. out:
  2930. return err;
  2931. }
  2932. /**
  2933. * ufshcd_force_reset_auto_bkops - force enable of auto bkops
  2934. * @hba: per adapter instance
  2935. *
  2936. * After a device reset the device may toggle the BKOPS_EN flag
  2937. * to default value. The s/w tracking variables should be updated
  2938. * as well. Do this by forcing enable of auto bkops.
  2939. */
  2940. static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
  2941. {
  2942. hba->auto_bkops_enabled = false;
  2943. hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
  2944. ufshcd_enable_auto_bkops(hba);
  2945. }
  2946. static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
  2947. {
  2948. return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  2949. QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
  2950. }
  2951. /**
  2952. * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
  2953. * @hba: per-adapter instance
  2954. * @status: bkops_status value
  2955. *
  2956. * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
  2957. * flag in the device to permit background operations if the device
  2958. * bkops_status is greater than or equal to "status" argument passed to
  2959. * this function, disable otherwise.
  2960. *
  2961. * Returns 0 for success, non-zero in case of failure.
  2962. *
  2963. * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
  2964. * to know whether auto bkops is enabled or disabled after this function
  2965. * returns control to it.
  2966. */
  2967. static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
  2968. enum bkops_status status)
  2969. {
  2970. int err;
  2971. u32 curr_status = 0;
  2972. err = ufshcd_get_bkops_status(hba, &curr_status);
  2973. if (err) {
  2974. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  2975. __func__, err);
  2976. goto out;
  2977. } else if (curr_status > BKOPS_STATUS_MAX) {
  2978. dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
  2979. __func__, curr_status);
  2980. err = -EINVAL;
  2981. goto out;
  2982. }
  2983. if (curr_status >= status)
  2984. err = ufshcd_enable_auto_bkops(hba);
  2985. else
  2986. err = ufshcd_disable_auto_bkops(hba);
  2987. out:
  2988. return err;
  2989. }
  2990. /**
  2991. * ufshcd_urgent_bkops - handle urgent bkops exception event
  2992. * @hba: per-adapter instance
  2993. *
  2994. * Enable fBackgroundOpsEn flag in the device to permit background
  2995. * operations.
  2996. *
  2997. * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
  2998. * and negative error value for any other failure.
  2999. */
  3000. static int ufshcd_urgent_bkops(struct ufs_hba *hba)
  3001. {
  3002. return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT);
  3003. }
  3004. static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
  3005. {
  3006. return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  3007. QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
  3008. }
  3009. /**
  3010. * ufshcd_exception_event_handler - handle exceptions raised by device
  3011. * @work: pointer to work data
  3012. *
  3013. * Read bExceptionEventStatus attribute from the device and handle the
  3014. * exception event accordingly.
  3015. */
  3016. static void ufshcd_exception_event_handler(struct work_struct *work)
  3017. {
  3018. struct ufs_hba *hba;
  3019. int err;
  3020. u32 status = 0;
  3021. hba = container_of(work, struct ufs_hba, eeh_work);
  3022. pm_runtime_get_sync(hba->dev);
  3023. err = ufshcd_get_ee_status(hba, &status);
  3024. if (err) {
  3025. dev_err(hba->dev, "%s: failed to get exception status %d\n",
  3026. __func__, err);
  3027. goto out;
  3028. }
  3029. status &= hba->ee_ctrl_mask;
  3030. if (status & MASK_EE_URGENT_BKOPS) {
  3031. err = ufshcd_urgent_bkops(hba);
  3032. if (err < 0)
  3033. dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
  3034. __func__, err);
  3035. }
  3036. out:
  3037. pm_runtime_put_sync(hba->dev);
  3038. return;
  3039. }
  3040. /**
  3041. * ufshcd_err_handler - handle UFS errors that require s/w attention
  3042. * @work: pointer to work structure
  3043. */
  3044. static void ufshcd_err_handler(struct work_struct *work)
  3045. {
  3046. struct ufs_hba *hba;
  3047. unsigned long flags;
  3048. u32 err_xfer = 0;
  3049. u32 err_tm = 0;
  3050. int err = 0;
  3051. int tag;
  3052. hba = container_of(work, struct ufs_hba, eh_work);
  3053. pm_runtime_get_sync(hba->dev);
  3054. ufshcd_hold(hba, false);
  3055. spin_lock_irqsave(hba->host->host_lock, flags);
  3056. if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
  3057. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3058. goto out;
  3059. }
  3060. hba->ufshcd_state = UFSHCD_STATE_RESET;
  3061. ufshcd_set_eh_in_progress(hba);
  3062. /* Complete requests that have door-bell cleared by h/w */
  3063. ufshcd_transfer_req_compl(hba);
  3064. ufshcd_tmc_handler(hba);
  3065. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3066. /* Clear pending transfer requests */
  3067. for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
  3068. if (ufshcd_clear_cmd(hba, tag))
  3069. err_xfer |= 1 << tag;
  3070. /* Clear pending task management requests */
  3071. for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
  3072. if (ufshcd_clear_tm_cmd(hba, tag))
  3073. err_tm |= 1 << tag;
  3074. /* Complete the requests that are cleared by s/w */
  3075. spin_lock_irqsave(hba->host->host_lock, flags);
  3076. ufshcd_transfer_req_compl(hba);
  3077. ufshcd_tmc_handler(hba);
  3078. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3079. /* Fatal errors need reset */
  3080. if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
  3081. ((hba->saved_err & UIC_ERROR) &&
  3082. (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
  3083. err = ufshcd_reset_and_restore(hba);
  3084. if (err) {
  3085. dev_err(hba->dev, "%s: reset and restore failed\n",
  3086. __func__);
  3087. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3088. }
  3089. /*
  3090. * Inform scsi mid-layer that we did reset and allow to handle
  3091. * Unit Attention properly.
  3092. */
  3093. scsi_report_bus_reset(hba->host, 0);
  3094. hba->saved_err = 0;
  3095. hba->saved_uic_err = 0;
  3096. }
  3097. ufshcd_clear_eh_in_progress(hba);
  3098. out:
  3099. scsi_unblock_requests(hba->host);
  3100. ufshcd_release(hba);
  3101. pm_runtime_put_sync(hba->dev);
  3102. }
  3103. /**
  3104. * ufshcd_update_uic_error - check and set fatal UIC error flags.
  3105. * @hba: per-adapter instance
  3106. */
  3107. static void ufshcd_update_uic_error(struct ufs_hba *hba)
  3108. {
  3109. u32 reg;
  3110. /* PA_INIT_ERROR is fatal and needs UIC reset */
  3111. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
  3112. if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
  3113. hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
  3114. /* UIC NL/TL/DME errors needs software retry */
  3115. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
  3116. if (reg)
  3117. hba->uic_error |= UFSHCD_UIC_NL_ERROR;
  3118. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
  3119. if (reg)
  3120. hba->uic_error |= UFSHCD_UIC_TL_ERROR;
  3121. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
  3122. if (reg)
  3123. hba->uic_error |= UFSHCD_UIC_DME_ERROR;
  3124. dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
  3125. __func__, hba->uic_error);
  3126. }
  3127. /**
  3128. * ufshcd_check_errors - Check for errors that need s/w attention
  3129. * @hba: per-adapter instance
  3130. */
  3131. static void ufshcd_check_errors(struct ufs_hba *hba)
  3132. {
  3133. bool queue_eh_work = false;
  3134. if (hba->errors & INT_FATAL_ERRORS)
  3135. queue_eh_work = true;
  3136. if (hba->errors & UIC_ERROR) {
  3137. hba->uic_error = 0;
  3138. ufshcd_update_uic_error(hba);
  3139. if (hba->uic_error)
  3140. queue_eh_work = true;
  3141. }
  3142. if (queue_eh_work) {
  3143. /* handle fatal errors only when link is functional */
  3144. if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
  3145. /* block commands from scsi mid-layer */
  3146. scsi_block_requests(hba->host);
  3147. /* transfer error masks to sticky bits */
  3148. hba->saved_err |= hba->errors;
  3149. hba->saved_uic_err |= hba->uic_error;
  3150. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3151. schedule_work(&hba->eh_work);
  3152. }
  3153. }
  3154. /*
  3155. * if (!queue_eh_work) -
  3156. * Other errors are either non-fatal where host recovers
  3157. * itself without s/w intervention or errors that will be
  3158. * handled by the SCSI core layer.
  3159. */
  3160. }
  3161. /**
  3162. * ufshcd_tmc_handler - handle task management function completion
  3163. * @hba: per adapter instance
  3164. */
  3165. static void ufshcd_tmc_handler(struct ufs_hba *hba)
  3166. {
  3167. u32 tm_doorbell;
  3168. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  3169. hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
  3170. wake_up(&hba->tm_wq);
  3171. }
  3172. /**
  3173. * ufshcd_sl_intr - Interrupt service routine
  3174. * @hba: per adapter instance
  3175. * @intr_status: contains interrupts generated by the controller
  3176. */
  3177. static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
  3178. {
  3179. hba->errors = UFSHCD_ERROR_MASK & intr_status;
  3180. if (hba->errors)
  3181. ufshcd_check_errors(hba);
  3182. if (intr_status & UFSHCD_UIC_MASK)
  3183. ufshcd_uic_cmd_compl(hba, intr_status);
  3184. if (intr_status & UTP_TASK_REQ_COMPL)
  3185. ufshcd_tmc_handler(hba);
  3186. if (intr_status & UTP_TRANSFER_REQ_COMPL)
  3187. ufshcd_transfer_req_compl(hba);
  3188. }
  3189. /**
  3190. * ufshcd_intr - Main interrupt service routine
  3191. * @irq: irq number
  3192. * @__hba: pointer to adapter instance
  3193. *
  3194. * Returns IRQ_HANDLED - If interrupt is valid
  3195. * IRQ_NONE - If invalid interrupt
  3196. */
  3197. static irqreturn_t ufshcd_intr(int irq, void *__hba)
  3198. {
  3199. u32 intr_status;
  3200. irqreturn_t retval = IRQ_NONE;
  3201. struct ufs_hba *hba = __hba;
  3202. spin_lock(hba->host->host_lock);
  3203. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  3204. if (intr_status) {
  3205. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  3206. ufshcd_sl_intr(hba, intr_status);
  3207. retval = IRQ_HANDLED;
  3208. }
  3209. spin_unlock(hba->host->host_lock);
  3210. return retval;
  3211. }
  3212. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
  3213. {
  3214. int err = 0;
  3215. u32 mask = 1 << tag;
  3216. unsigned long flags;
  3217. if (!test_bit(tag, &hba->outstanding_tasks))
  3218. goto out;
  3219. spin_lock_irqsave(hba->host->host_lock, flags);
  3220. ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
  3221. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3222. /* poll for max. 1 sec to clear door bell register by h/w */
  3223. err = ufshcd_wait_for_register(hba,
  3224. REG_UTP_TASK_REQ_DOOR_BELL,
  3225. mask, 0, 1000, 1000);
  3226. out:
  3227. return err;
  3228. }
  3229. /**
  3230. * ufshcd_issue_tm_cmd - issues task management commands to controller
  3231. * @hba: per adapter instance
  3232. * @lun_id: LUN ID to which TM command is sent
  3233. * @task_id: task ID to which the TM command is applicable
  3234. * @tm_function: task management function opcode
  3235. * @tm_response: task management service response return value
  3236. *
  3237. * Returns non-zero value on error, zero on success.
  3238. */
  3239. static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
  3240. u8 tm_function, u8 *tm_response)
  3241. {
  3242. struct utp_task_req_desc *task_req_descp;
  3243. struct utp_upiu_task_req *task_req_upiup;
  3244. struct Scsi_Host *host;
  3245. unsigned long flags;
  3246. int free_slot;
  3247. int err;
  3248. int task_tag;
  3249. host = hba->host;
  3250. /*
  3251. * Get free slot, sleep if slots are unavailable.
  3252. * Even though we use wait_event() which sleeps indefinitely,
  3253. * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
  3254. */
  3255. wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
  3256. ufshcd_hold(hba, false);
  3257. spin_lock_irqsave(host->host_lock, flags);
  3258. task_req_descp = hba->utmrdl_base_addr;
  3259. task_req_descp += free_slot;
  3260. /* Configure task request descriptor */
  3261. task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
  3262. task_req_descp->header.dword_2 =
  3263. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  3264. /* Configure task request UPIU */
  3265. task_req_upiup =
  3266. (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
  3267. task_tag = hba->nutrs + free_slot;
  3268. task_req_upiup->header.dword_0 =
  3269. UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
  3270. lun_id, task_tag);
  3271. task_req_upiup->header.dword_1 =
  3272. UPIU_HEADER_DWORD(0, tm_function, 0, 0);
  3273. /*
  3274. * The host shall provide the same value for LUN field in the basic
  3275. * header and for Input Parameter.
  3276. */
  3277. task_req_upiup->input_param1 = cpu_to_be32(lun_id);
  3278. task_req_upiup->input_param2 = cpu_to_be32(task_id);
  3279. /* send command to the controller */
  3280. __set_bit(free_slot, &hba->outstanding_tasks);
  3281. ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
  3282. spin_unlock_irqrestore(host->host_lock, flags);
  3283. /* wait until the task management command is completed */
  3284. err = wait_event_timeout(hba->tm_wq,
  3285. test_bit(free_slot, &hba->tm_condition),
  3286. msecs_to_jiffies(TM_CMD_TIMEOUT));
  3287. if (!err) {
  3288. dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
  3289. __func__, tm_function);
  3290. if (ufshcd_clear_tm_cmd(hba, free_slot))
  3291. dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
  3292. __func__, free_slot);
  3293. err = -ETIMEDOUT;
  3294. } else {
  3295. err = ufshcd_task_req_compl(hba, free_slot, tm_response);
  3296. }
  3297. clear_bit(free_slot, &hba->tm_condition);
  3298. ufshcd_put_tm_slot(hba, free_slot);
  3299. wake_up(&hba->tm_tag_wq);
  3300. ufshcd_release(hba);
  3301. return err;
  3302. }
  3303. /**
  3304. * ufshcd_eh_device_reset_handler - device reset handler registered to
  3305. * scsi layer.
  3306. * @cmd: SCSI command pointer
  3307. *
  3308. * Returns SUCCESS/FAILED
  3309. */
  3310. static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
  3311. {
  3312. struct Scsi_Host *host;
  3313. struct ufs_hba *hba;
  3314. unsigned int tag;
  3315. u32 pos;
  3316. int err;
  3317. u8 resp = 0xF;
  3318. struct ufshcd_lrb *lrbp;
  3319. unsigned long flags;
  3320. host = cmd->device->host;
  3321. hba = shost_priv(host);
  3322. tag = cmd->request->tag;
  3323. lrbp = &hba->lrb[tag];
  3324. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
  3325. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3326. if (!err)
  3327. err = resp;
  3328. goto out;
  3329. }
  3330. /* clear the commands that were pending for corresponding LUN */
  3331. for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
  3332. if (hba->lrb[pos].lun == lrbp->lun) {
  3333. err = ufshcd_clear_cmd(hba, pos);
  3334. if (err)
  3335. break;
  3336. }
  3337. }
  3338. spin_lock_irqsave(host->host_lock, flags);
  3339. ufshcd_transfer_req_compl(hba);
  3340. spin_unlock_irqrestore(host->host_lock, flags);
  3341. out:
  3342. if (!err) {
  3343. err = SUCCESS;
  3344. } else {
  3345. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  3346. err = FAILED;
  3347. }
  3348. return err;
  3349. }
  3350. /**
  3351. * ufshcd_abort - abort a specific command
  3352. * @cmd: SCSI command pointer
  3353. *
  3354. * Abort the pending command in device by sending UFS_ABORT_TASK task management
  3355. * command, and in host controller by clearing the door-bell register. There can
  3356. * be race between controller sending the command to the device while abort is
  3357. * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
  3358. * really issued and then try to abort it.
  3359. *
  3360. * Returns SUCCESS/FAILED
  3361. */
  3362. static int ufshcd_abort(struct scsi_cmnd *cmd)
  3363. {
  3364. struct Scsi_Host *host;
  3365. struct ufs_hba *hba;
  3366. unsigned long flags;
  3367. unsigned int tag;
  3368. int err = 0;
  3369. int poll_cnt;
  3370. u8 resp = 0xF;
  3371. struct ufshcd_lrb *lrbp;
  3372. u32 reg;
  3373. host = cmd->device->host;
  3374. hba = shost_priv(host);
  3375. tag = cmd->request->tag;
  3376. ufshcd_hold(hba, false);
  3377. /* If command is already aborted/completed, return SUCCESS */
  3378. if (!(test_bit(tag, &hba->outstanding_reqs)))
  3379. goto out;
  3380. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  3381. if (!(reg & (1 << tag))) {
  3382. dev_err(hba->dev,
  3383. "%s: cmd was completed, but without a notifying intr, tag = %d",
  3384. __func__, tag);
  3385. }
  3386. lrbp = &hba->lrb[tag];
  3387. for (poll_cnt = 100; poll_cnt; poll_cnt--) {
  3388. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  3389. UFS_QUERY_TASK, &resp);
  3390. if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
  3391. /* cmd pending in the device */
  3392. break;
  3393. } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3394. /*
  3395. * cmd not pending in the device, check if it is
  3396. * in transition.
  3397. */
  3398. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  3399. if (reg & (1 << tag)) {
  3400. /* sleep for max. 200us to stabilize */
  3401. usleep_range(100, 200);
  3402. continue;
  3403. }
  3404. /* command completed already */
  3405. goto out;
  3406. } else {
  3407. if (!err)
  3408. err = resp; /* service response error */
  3409. goto out;
  3410. }
  3411. }
  3412. if (!poll_cnt) {
  3413. err = -EBUSY;
  3414. goto out;
  3415. }
  3416. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  3417. UFS_ABORT_TASK, &resp);
  3418. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3419. if (!err)
  3420. err = resp; /* service response error */
  3421. goto out;
  3422. }
  3423. err = ufshcd_clear_cmd(hba, tag);
  3424. if (err)
  3425. goto out;
  3426. scsi_dma_unmap(cmd);
  3427. spin_lock_irqsave(host->host_lock, flags);
  3428. __clear_bit(tag, &hba->outstanding_reqs);
  3429. hba->lrb[tag].cmd = NULL;
  3430. spin_unlock_irqrestore(host->host_lock, flags);
  3431. clear_bit_unlock(tag, &hba->lrb_in_use);
  3432. wake_up(&hba->dev_cmd.tag_wq);
  3433. out:
  3434. if (!err) {
  3435. err = SUCCESS;
  3436. } else {
  3437. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  3438. err = FAILED;
  3439. }
  3440. /*
  3441. * This ufshcd_release() corresponds to the original scsi cmd that got
  3442. * aborted here (as we won't get any IRQ for it).
  3443. */
  3444. ufshcd_release(hba);
  3445. return err;
  3446. }
  3447. /**
  3448. * ufshcd_host_reset_and_restore - reset and restore host controller
  3449. * @hba: per-adapter instance
  3450. *
  3451. * Note that host controller reset may issue DME_RESET to
  3452. * local and remote (device) Uni-Pro stack and the attributes
  3453. * are reset to default state.
  3454. *
  3455. * Returns zero on success, non-zero on failure
  3456. */
  3457. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
  3458. {
  3459. int err;
  3460. unsigned long flags;
  3461. /* Reset the host controller */
  3462. spin_lock_irqsave(hba->host->host_lock, flags);
  3463. ufshcd_hba_stop(hba);
  3464. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3465. err = ufshcd_hba_enable(hba);
  3466. if (err)
  3467. goto out;
  3468. /* Establish the link again and restore the device */
  3469. err = ufshcd_probe_hba(hba);
  3470. if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
  3471. err = -EIO;
  3472. out:
  3473. if (err)
  3474. dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
  3475. return err;
  3476. }
  3477. /**
  3478. * ufshcd_reset_and_restore - reset and re-initialize host/device
  3479. * @hba: per-adapter instance
  3480. *
  3481. * Reset and recover device, host and re-establish link. This
  3482. * is helpful to recover the communication in fatal error conditions.
  3483. *
  3484. * Returns zero on success, non-zero on failure
  3485. */
  3486. static int ufshcd_reset_and_restore(struct ufs_hba *hba)
  3487. {
  3488. int err = 0;
  3489. unsigned long flags;
  3490. int retries = MAX_HOST_RESET_RETRIES;
  3491. do {
  3492. err = ufshcd_host_reset_and_restore(hba);
  3493. } while (err && --retries);
  3494. /*
  3495. * After reset the door-bell might be cleared, complete
  3496. * outstanding requests in s/w here.
  3497. */
  3498. spin_lock_irqsave(hba->host->host_lock, flags);
  3499. ufshcd_transfer_req_compl(hba);
  3500. ufshcd_tmc_handler(hba);
  3501. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3502. return err;
  3503. }
  3504. /**
  3505. * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
  3506. * @cmd - SCSI command pointer
  3507. *
  3508. * Returns SUCCESS/FAILED
  3509. */
  3510. static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
  3511. {
  3512. int err;
  3513. unsigned long flags;
  3514. struct ufs_hba *hba;
  3515. hba = shost_priv(cmd->device->host);
  3516. ufshcd_hold(hba, false);
  3517. /*
  3518. * Check if there is any race with fatal error handling.
  3519. * If so, wait for it to complete. Even though fatal error
  3520. * handling does reset and restore in some cases, don't assume
  3521. * anything out of it. We are just avoiding race here.
  3522. */
  3523. do {
  3524. spin_lock_irqsave(hba->host->host_lock, flags);
  3525. if (!(work_pending(&hba->eh_work) ||
  3526. hba->ufshcd_state == UFSHCD_STATE_RESET))
  3527. break;
  3528. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3529. dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
  3530. flush_work(&hba->eh_work);
  3531. } while (1);
  3532. hba->ufshcd_state = UFSHCD_STATE_RESET;
  3533. ufshcd_set_eh_in_progress(hba);
  3534. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3535. err = ufshcd_reset_and_restore(hba);
  3536. spin_lock_irqsave(hba->host->host_lock, flags);
  3537. if (!err) {
  3538. err = SUCCESS;
  3539. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  3540. } else {
  3541. err = FAILED;
  3542. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3543. }
  3544. ufshcd_clear_eh_in_progress(hba);
  3545. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3546. ufshcd_release(hba);
  3547. return err;
  3548. }
  3549. /**
  3550. * ufshcd_get_max_icc_level - calculate the ICC level
  3551. * @sup_curr_uA: max. current supported by the regulator
  3552. * @start_scan: row at the desc table to start scan from
  3553. * @buff: power descriptor buffer
  3554. *
  3555. * Returns calculated max ICC level for specific regulator
  3556. */
  3557. static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
  3558. {
  3559. int i;
  3560. int curr_uA;
  3561. u16 data;
  3562. u16 unit;
  3563. for (i = start_scan; i >= 0; i--) {
  3564. data = be16_to_cpu(*((u16 *)(buff + 2*i)));
  3565. unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
  3566. ATTR_ICC_LVL_UNIT_OFFSET;
  3567. curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
  3568. switch (unit) {
  3569. case UFSHCD_NANO_AMP:
  3570. curr_uA = curr_uA / 1000;
  3571. break;
  3572. case UFSHCD_MILI_AMP:
  3573. curr_uA = curr_uA * 1000;
  3574. break;
  3575. case UFSHCD_AMP:
  3576. curr_uA = curr_uA * 1000 * 1000;
  3577. break;
  3578. case UFSHCD_MICRO_AMP:
  3579. default:
  3580. break;
  3581. }
  3582. if (sup_curr_uA >= curr_uA)
  3583. break;
  3584. }
  3585. if (i < 0) {
  3586. i = 0;
  3587. pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
  3588. }
  3589. return (u32)i;
  3590. }
  3591. /**
  3592. * ufshcd_calc_icc_level - calculate the max ICC level
  3593. * In case regulators are not initialized we'll return 0
  3594. * @hba: per-adapter instance
  3595. * @desc_buf: power descriptor buffer to extract ICC levels from.
  3596. * @len: length of desc_buff
  3597. *
  3598. * Returns calculated ICC level
  3599. */
  3600. static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
  3601. u8 *desc_buf, int len)
  3602. {
  3603. u32 icc_level = 0;
  3604. if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
  3605. !hba->vreg_info.vccq2) {
  3606. dev_err(hba->dev,
  3607. "%s: Regulator capability was not set, actvIccLevel=%d",
  3608. __func__, icc_level);
  3609. goto out;
  3610. }
  3611. if (hba->vreg_info.vcc)
  3612. icc_level = ufshcd_get_max_icc_level(
  3613. hba->vreg_info.vcc->max_uA,
  3614. POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
  3615. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
  3616. if (hba->vreg_info.vccq)
  3617. icc_level = ufshcd_get_max_icc_level(
  3618. hba->vreg_info.vccq->max_uA,
  3619. icc_level,
  3620. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
  3621. if (hba->vreg_info.vccq2)
  3622. icc_level = ufshcd_get_max_icc_level(
  3623. hba->vreg_info.vccq2->max_uA,
  3624. icc_level,
  3625. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
  3626. out:
  3627. return icc_level;
  3628. }
  3629. static void ufshcd_init_icc_levels(struct ufs_hba *hba)
  3630. {
  3631. int ret;
  3632. int buff_len = QUERY_DESC_POWER_MAX_SIZE;
  3633. u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
  3634. ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
  3635. if (ret) {
  3636. dev_err(hba->dev,
  3637. "%s: Failed reading power descriptor.len = %d ret = %d",
  3638. __func__, buff_len, ret);
  3639. return;
  3640. }
  3641. hba->init_prefetch_data.icc_level =
  3642. ufshcd_find_max_sup_active_icc_level(hba,
  3643. desc_buf, buff_len);
  3644. dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
  3645. __func__, hba->init_prefetch_data.icc_level);
  3646. ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  3647. QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
  3648. &hba->init_prefetch_data.icc_level);
  3649. if (ret)
  3650. dev_err(hba->dev,
  3651. "%s: Failed configuring bActiveICCLevel = %d ret = %d",
  3652. __func__, hba->init_prefetch_data.icc_level , ret);
  3653. }
  3654. /**
  3655. * ufshcd_scsi_add_wlus - Adds required W-LUs
  3656. * @hba: per-adapter instance
  3657. *
  3658. * UFS device specification requires the UFS devices to support 4 well known
  3659. * logical units:
  3660. * "REPORT_LUNS" (address: 01h)
  3661. * "UFS Device" (address: 50h)
  3662. * "RPMB" (address: 44h)
  3663. * "BOOT" (address: 30h)
  3664. * UFS device's power management needs to be controlled by "POWER CONDITION"
  3665. * field of SSU (START STOP UNIT) command. But this "power condition" field
  3666. * will take effect only when its sent to "UFS device" well known logical unit
  3667. * hence we require the scsi_device instance to represent this logical unit in
  3668. * order for the UFS host driver to send the SSU command for power management.
  3669. * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
  3670. * Block) LU so user space process can control this LU. User space may also
  3671. * want to have access to BOOT LU.
  3672. * This function adds scsi device instances for each of all well known LUs
  3673. * (except "REPORT LUNS" LU).
  3674. *
  3675. * Returns zero on success (all required W-LUs are added successfully),
  3676. * non-zero error value on failure (if failed to add any of the required W-LU).
  3677. */
  3678. static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
  3679. {
  3680. int ret = 0;
  3681. struct scsi_device *sdev_rpmb;
  3682. struct scsi_device *sdev_boot;
  3683. hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
  3684. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
  3685. if (IS_ERR(hba->sdev_ufs_device)) {
  3686. ret = PTR_ERR(hba->sdev_ufs_device);
  3687. hba->sdev_ufs_device = NULL;
  3688. goto out;
  3689. }
  3690. scsi_device_put(hba->sdev_ufs_device);
  3691. sdev_boot = __scsi_add_device(hba->host, 0, 0,
  3692. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
  3693. if (IS_ERR(sdev_boot)) {
  3694. ret = PTR_ERR(sdev_boot);
  3695. goto remove_sdev_ufs_device;
  3696. }
  3697. scsi_device_put(sdev_boot);
  3698. sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
  3699. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
  3700. if (IS_ERR(sdev_rpmb)) {
  3701. ret = PTR_ERR(sdev_rpmb);
  3702. goto remove_sdev_boot;
  3703. }
  3704. scsi_device_put(sdev_rpmb);
  3705. goto out;
  3706. remove_sdev_boot:
  3707. scsi_remove_device(sdev_boot);
  3708. remove_sdev_ufs_device:
  3709. scsi_remove_device(hba->sdev_ufs_device);
  3710. out:
  3711. return ret;
  3712. }
  3713. /**
  3714. * ufshcd_probe_hba - probe hba to detect device and initialize
  3715. * @hba: per-adapter instance
  3716. *
  3717. * Execute link-startup and verify device initialization
  3718. */
  3719. static int ufshcd_probe_hba(struct ufs_hba *hba)
  3720. {
  3721. int ret;
  3722. ret = ufshcd_link_startup(hba);
  3723. if (ret)
  3724. goto out;
  3725. ufshcd_init_pwr_info(hba);
  3726. /* UniPro link is active now */
  3727. ufshcd_set_link_active(hba);
  3728. ret = ufshcd_verify_dev_init(hba);
  3729. if (ret)
  3730. goto out;
  3731. ret = ufshcd_complete_dev_init(hba);
  3732. if (ret)
  3733. goto out;
  3734. /* UFS device is also active now */
  3735. ufshcd_set_ufs_dev_active(hba);
  3736. ufshcd_force_reset_auto_bkops(hba);
  3737. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  3738. hba->wlun_dev_clr_ua = true;
  3739. if (ufshcd_get_max_pwr_mode(hba)) {
  3740. dev_err(hba->dev,
  3741. "%s: Failed getting max supported power mode\n",
  3742. __func__);
  3743. } else {
  3744. ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
  3745. if (ret)
  3746. dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
  3747. __func__, ret);
  3748. }
  3749. /*
  3750. * If we are in error handling context or in power management callbacks
  3751. * context, no need to scan the host
  3752. */
  3753. if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  3754. bool flag;
  3755. /* clear any previous UFS device information */
  3756. memset(&hba->dev_info, 0, sizeof(hba->dev_info));
  3757. if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  3758. QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
  3759. hba->dev_info.f_power_on_wp_en = flag;
  3760. if (!hba->is_init_prefetch)
  3761. ufshcd_init_icc_levels(hba);
  3762. /* Add required well known logical units to scsi mid layer */
  3763. if (ufshcd_scsi_add_wlus(hba))
  3764. goto out;
  3765. scsi_scan_host(hba->host);
  3766. pm_runtime_put_sync(hba->dev);
  3767. }
  3768. if (!hba->is_init_prefetch)
  3769. hba->is_init_prefetch = true;
  3770. /* Resume devfreq after UFS device is detected */
  3771. if (ufshcd_is_clkscaling_enabled(hba))
  3772. devfreq_resume_device(hba->devfreq);
  3773. out:
  3774. /*
  3775. * If we failed to initialize the device or the device is not
  3776. * present, turn off the power/clocks etc.
  3777. */
  3778. if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  3779. pm_runtime_put_sync(hba->dev);
  3780. ufshcd_hba_exit(hba);
  3781. }
  3782. return ret;
  3783. }
  3784. /**
  3785. * ufshcd_async_scan - asynchronous execution for probing hba
  3786. * @data: data pointer to pass to this function
  3787. * @cookie: cookie data
  3788. */
  3789. static void ufshcd_async_scan(void *data, async_cookie_t cookie)
  3790. {
  3791. struct ufs_hba *hba = (struct ufs_hba *)data;
  3792. ufshcd_probe_hba(hba);
  3793. }
  3794. static struct scsi_host_template ufshcd_driver_template = {
  3795. .module = THIS_MODULE,
  3796. .name = UFSHCD,
  3797. .proc_name = UFSHCD,
  3798. .queuecommand = ufshcd_queuecommand,
  3799. .slave_alloc = ufshcd_slave_alloc,
  3800. .slave_configure = ufshcd_slave_configure,
  3801. .slave_destroy = ufshcd_slave_destroy,
  3802. .change_queue_depth = ufshcd_change_queue_depth,
  3803. .eh_abort_handler = ufshcd_abort,
  3804. .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
  3805. .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
  3806. .this_id = -1,
  3807. .sg_tablesize = SG_ALL,
  3808. .cmd_per_lun = UFSHCD_CMD_PER_LUN,
  3809. .can_queue = UFSHCD_CAN_QUEUE,
  3810. .max_host_blocked = 1,
  3811. .use_blk_tags = 1,
  3812. .track_queue_depth = 1,
  3813. };
  3814. static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
  3815. int ua)
  3816. {
  3817. int ret;
  3818. if (!vreg)
  3819. return 0;
  3820. ret = regulator_set_load(vreg->reg, ua);
  3821. if (ret < 0) {
  3822. dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
  3823. __func__, vreg->name, ua, ret);
  3824. }
  3825. return ret;
  3826. }
  3827. static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
  3828. struct ufs_vreg *vreg)
  3829. {
  3830. return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
  3831. }
  3832. static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
  3833. struct ufs_vreg *vreg)
  3834. {
  3835. return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
  3836. }
  3837. static int ufshcd_config_vreg(struct device *dev,
  3838. struct ufs_vreg *vreg, bool on)
  3839. {
  3840. int ret = 0;
  3841. struct regulator *reg = vreg->reg;
  3842. const char *name = vreg->name;
  3843. int min_uV, uA_load;
  3844. BUG_ON(!vreg);
  3845. if (regulator_count_voltages(reg) > 0) {
  3846. min_uV = on ? vreg->min_uV : 0;
  3847. ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
  3848. if (ret) {
  3849. dev_err(dev, "%s: %s set voltage failed, err=%d\n",
  3850. __func__, name, ret);
  3851. goto out;
  3852. }
  3853. uA_load = on ? vreg->max_uA : 0;
  3854. ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
  3855. if (ret)
  3856. goto out;
  3857. }
  3858. out:
  3859. return ret;
  3860. }
  3861. static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
  3862. {
  3863. int ret = 0;
  3864. if (!vreg || vreg->enabled)
  3865. goto out;
  3866. ret = ufshcd_config_vreg(dev, vreg, true);
  3867. if (!ret)
  3868. ret = regulator_enable(vreg->reg);
  3869. if (!ret)
  3870. vreg->enabled = true;
  3871. else
  3872. dev_err(dev, "%s: %s enable failed, err=%d\n",
  3873. __func__, vreg->name, ret);
  3874. out:
  3875. return ret;
  3876. }
  3877. static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
  3878. {
  3879. int ret = 0;
  3880. if (!vreg || !vreg->enabled)
  3881. goto out;
  3882. ret = regulator_disable(vreg->reg);
  3883. if (!ret) {
  3884. /* ignore errors on applying disable config */
  3885. ufshcd_config_vreg(dev, vreg, false);
  3886. vreg->enabled = false;
  3887. } else {
  3888. dev_err(dev, "%s: %s disable failed, err=%d\n",
  3889. __func__, vreg->name, ret);
  3890. }
  3891. out:
  3892. return ret;
  3893. }
  3894. static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
  3895. {
  3896. int ret = 0;
  3897. struct device *dev = hba->dev;
  3898. struct ufs_vreg_info *info = &hba->vreg_info;
  3899. if (!info)
  3900. goto out;
  3901. ret = ufshcd_toggle_vreg(dev, info->vcc, on);
  3902. if (ret)
  3903. goto out;
  3904. ret = ufshcd_toggle_vreg(dev, info->vccq, on);
  3905. if (ret)
  3906. goto out;
  3907. ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
  3908. if (ret)
  3909. goto out;
  3910. out:
  3911. if (ret) {
  3912. ufshcd_toggle_vreg(dev, info->vccq2, false);
  3913. ufshcd_toggle_vreg(dev, info->vccq, false);
  3914. ufshcd_toggle_vreg(dev, info->vcc, false);
  3915. }
  3916. return ret;
  3917. }
  3918. static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
  3919. {
  3920. struct ufs_vreg_info *info = &hba->vreg_info;
  3921. if (info)
  3922. return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
  3923. return 0;
  3924. }
  3925. static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
  3926. {
  3927. int ret = 0;
  3928. if (!vreg)
  3929. goto out;
  3930. vreg->reg = devm_regulator_get(dev, vreg->name);
  3931. if (IS_ERR(vreg->reg)) {
  3932. ret = PTR_ERR(vreg->reg);
  3933. dev_err(dev, "%s: %s get failed, err=%d\n",
  3934. __func__, vreg->name, ret);
  3935. }
  3936. out:
  3937. return ret;
  3938. }
  3939. static int ufshcd_init_vreg(struct ufs_hba *hba)
  3940. {
  3941. int ret = 0;
  3942. struct device *dev = hba->dev;
  3943. struct ufs_vreg_info *info = &hba->vreg_info;
  3944. if (!info)
  3945. goto out;
  3946. ret = ufshcd_get_vreg(dev, info->vcc);
  3947. if (ret)
  3948. goto out;
  3949. ret = ufshcd_get_vreg(dev, info->vccq);
  3950. if (ret)
  3951. goto out;
  3952. ret = ufshcd_get_vreg(dev, info->vccq2);
  3953. out:
  3954. return ret;
  3955. }
  3956. static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
  3957. {
  3958. struct ufs_vreg_info *info = &hba->vreg_info;
  3959. if (info)
  3960. return ufshcd_get_vreg(hba->dev, info->vdd_hba);
  3961. return 0;
  3962. }
  3963. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  3964. bool skip_ref_clk)
  3965. {
  3966. int ret = 0;
  3967. struct ufs_clk_info *clki;
  3968. struct list_head *head = &hba->clk_list_head;
  3969. unsigned long flags;
  3970. if (!head || list_empty(head))
  3971. goto out;
  3972. list_for_each_entry(clki, head, list) {
  3973. if (!IS_ERR_OR_NULL(clki->clk)) {
  3974. if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
  3975. continue;
  3976. if (on && !clki->enabled) {
  3977. ret = clk_prepare_enable(clki->clk);
  3978. if (ret) {
  3979. dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
  3980. __func__, clki->name, ret);
  3981. goto out;
  3982. }
  3983. } else if (!on && clki->enabled) {
  3984. clk_disable_unprepare(clki->clk);
  3985. }
  3986. clki->enabled = on;
  3987. dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
  3988. clki->name, on ? "en" : "dis");
  3989. }
  3990. }
  3991. if (hba->vops && hba->vops->setup_clocks)
  3992. ret = hba->vops->setup_clocks(hba, on);
  3993. out:
  3994. if (ret) {
  3995. list_for_each_entry(clki, head, list) {
  3996. if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
  3997. clk_disable_unprepare(clki->clk);
  3998. }
  3999. } else if (on) {
  4000. spin_lock_irqsave(hba->host->host_lock, flags);
  4001. hba->clk_gating.state = CLKS_ON;
  4002. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4003. }
  4004. return ret;
  4005. }
  4006. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
  4007. {
  4008. return __ufshcd_setup_clocks(hba, on, false);
  4009. }
  4010. static int ufshcd_init_clocks(struct ufs_hba *hba)
  4011. {
  4012. int ret = 0;
  4013. struct ufs_clk_info *clki;
  4014. struct device *dev = hba->dev;
  4015. struct list_head *head = &hba->clk_list_head;
  4016. if (!head || list_empty(head))
  4017. goto out;
  4018. list_for_each_entry(clki, head, list) {
  4019. if (!clki->name)
  4020. continue;
  4021. clki->clk = devm_clk_get(dev, clki->name);
  4022. if (IS_ERR(clki->clk)) {
  4023. ret = PTR_ERR(clki->clk);
  4024. dev_err(dev, "%s: %s clk get failed, %d\n",
  4025. __func__, clki->name, ret);
  4026. goto out;
  4027. }
  4028. if (clki->max_freq) {
  4029. ret = clk_set_rate(clki->clk, clki->max_freq);
  4030. if (ret) {
  4031. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  4032. __func__, clki->name,
  4033. clki->max_freq, ret);
  4034. goto out;
  4035. }
  4036. clki->curr_freq = clki->max_freq;
  4037. }
  4038. dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
  4039. clki->name, clk_get_rate(clki->clk));
  4040. }
  4041. out:
  4042. return ret;
  4043. }
  4044. static int ufshcd_variant_hba_init(struct ufs_hba *hba)
  4045. {
  4046. int err = 0;
  4047. if (!hba->vops)
  4048. goto out;
  4049. if (hba->vops->init) {
  4050. err = hba->vops->init(hba);
  4051. if (err)
  4052. goto out;
  4053. }
  4054. if (hba->vops->setup_regulators) {
  4055. err = hba->vops->setup_regulators(hba, true);
  4056. if (err)
  4057. goto out_exit;
  4058. }
  4059. goto out;
  4060. out_exit:
  4061. if (hba->vops->exit)
  4062. hba->vops->exit(hba);
  4063. out:
  4064. if (err)
  4065. dev_err(hba->dev, "%s: variant %s init failed err %d\n",
  4066. __func__, hba->vops ? hba->vops->name : "", err);
  4067. return err;
  4068. }
  4069. static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
  4070. {
  4071. if (!hba->vops)
  4072. return;
  4073. if (hba->vops->setup_clocks)
  4074. hba->vops->setup_clocks(hba, false);
  4075. if (hba->vops->setup_regulators)
  4076. hba->vops->setup_regulators(hba, false);
  4077. if (hba->vops->exit)
  4078. hba->vops->exit(hba);
  4079. }
  4080. static int ufshcd_hba_init(struct ufs_hba *hba)
  4081. {
  4082. int err;
  4083. /*
  4084. * Handle host controller power separately from the UFS device power
  4085. * rails as it will help controlling the UFS host controller power
  4086. * collapse easily which is different than UFS device power collapse.
  4087. * Also, enable the host controller power before we go ahead with rest
  4088. * of the initialization here.
  4089. */
  4090. err = ufshcd_init_hba_vreg(hba);
  4091. if (err)
  4092. goto out;
  4093. err = ufshcd_setup_hba_vreg(hba, true);
  4094. if (err)
  4095. goto out;
  4096. err = ufshcd_init_clocks(hba);
  4097. if (err)
  4098. goto out_disable_hba_vreg;
  4099. err = ufshcd_setup_clocks(hba, true);
  4100. if (err)
  4101. goto out_disable_hba_vreg;
  4102. err = ufshcd_init_vreg(hba);
  4103. if (err)
  4104. goto out_disable_clks;
  4105. err = ufshcd_setup_vreg(hba, true);
  4106. if (err)
  4107. goto out_disable_clks;
  4108. err = ufshcd_variant_hba_init(hba);
  4109. if (err)
  4110. goto out_disable_vreg;
  4111. hba->is_powered = true;
  4112. goto out;
  4113. out_disable_vreg:
  4114. ufshcd_setup_vreg(hba, false);
  4115. out_disable_clks:
  4116. ufshcd_setup_clocks(hba, false);
  4117. out_disable_hba_vreg:
  4118. ufshcd_setup_hba_vreg(hba, false);
  4119. out:
  4120. return err;
  4121. }
  4122. static void ufshcd_hba_exit(struct ufs_hba *hba)
  4123. {
  4124. if (hba->is_powered) {
  4125. ufshcd_variant_hba_exit(hba);
  4126. ufshcd_setup_vreg(hba, false);
  4127. ufshcd_setup_clocks(hba, false);
  4128. ufshcd_setup_hba_vreg(hba, false);
  4129. hba->is_powered = false;
  4130. }
  4131. }
  4132. static int
  4133. ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
  4134. {
  4135. unsigned char cmd[6] = {REQUEST_SENSE,
  4136. 0,
  4137. 0,
  4138. 0,
  4139. SCSI_SENSE_BUFFERSIZE,
  4140. 0};
  4141. char *buffer;
  4142. int ret;
  4143. buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  4144. if (!buffer) {
  4145. ret = -ENOMEM;
  4146. goto out;
  4147. }
  4148. ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
  4149. SCSI_SENSE_BUFFERSIZE, NULL,
  4150. msecs_to_jiffies(1000), 3, NULL, REQ_PM);
  4151. if (ret)
  4152. pr_err("%s: failed with err %d\n", __func__, ret);
  4153. kfree(buffer);
  4154. out:
  4155. return ret;
  4156. }
  4157. /**
  4158. * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
  4159. * power mode
  4160. * @hba: per adapter instance
  4161. * @pwr_mode: device power mode to set
  4162. *
  4163. * Returns 0 if requested power mode is set successfully
  4164. * Returns non-zero if failed to set the requested power mode
  4165. */
  4166. static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
  4167. enum ufs_dev_pwr_mode pwr_mode)
  4168. {
  4169. unsigned char cmd[6] = { START_STOP };
  4170. struct scsi_sense_hdr sshdr;
  4171. struct scsi_device *sdp;
  4172. unsigned long flags;
  4173. int ret;
  4174. spin_lock_irqsave(hba->host->host_lock, flags);
  4175. sdp = hba->sdev_ufs_device;
  4176. if (sdp) {
  4177. ret = scsi_device_get(sdp);
  4178. if (!ret && !scsi_device_online(sdp)) {
  4179. ret = -ENODEV;
  4180. scsi_device_put(sdp);
  4181. }
  4182. } else {
  4183. ret = -ENODEV;
  4184. }
  4185. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4186. if (ret)
  4187. return ret;
  4188. /*
  4189. * If scsi commands fail, the scsi mid-layer schedules scsi error-
  4190. * handling, which would wait for host to be resumed. Since we know
  4191. * we are functional while we are here, skip host resume in error
  4192. * handling context.
  4193. */
  4194. hba->host->eh_noresume = 1;
  4195. if (hba->wlun_dev_clr_ua) {
  4196. ret = ufshcd_send_request_sense(hba, sdp);
  4197. if (ret)
  4198. goto out;
  4199. /* Unit attention condition is cleared now */
  4200. hba->wlun_dev_clr_ua = false;
  4201. }
  4202. cmd[4] = pwr_mode << 4;
  4203. /*
  4204. * Current function would be generally called from the power management
  4205. * callbacks hence set the REQ_PM flag so that it doesn't resume the
  4206. * already suspended childs.
  4207. */
  4208. ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
  4209. START_STOP_TIMEOUT, 0, NULL, REQ_PM);
  4210. if (ret) {
  4211. sdev_printk(KERN_WARNING, sdp,
  4212. "START_STOP failed for power mode: %d, result %x\n",
  4213. pwr_mode, ret);
  4214. if (driver_byte(ret) & DRIVER_SENSE)
  4215. scsi_print_sense_hdr(sdp, NULL, &sshdr);
  4216. }
  4217. if (!ret)
  4218. hba->curr_dev_pwr_mode = pwr_mode;
  4219. out:
  4220. scsi_device_put(sdp);
  4221. hba->host->eh_noresume = 0;
  4222. return ret;
  4223. }
  4224. static int ufshcd_link_state_transition(struct ufs_hba *hba,
  4225. enum uic_link_state req_link_state,
  4226. int check_for_bkops)
  4227. {
  4228. int ret = 0;
  4229. if (req_link_state == hba->uic_link_state)
  4230. return 0;
  4231. if (req_link_state == UIC_LINK_HIBERN8_STATE) {
  4232. ret = ufshcd_uic_hibern8_enter(hba);
  4233. if (!ret)
  4234. ufshcd_set_link_hibern8(hba);
  4235. else
  4236. goto out;
  4237. }
  4238. /*
  4239. * If autobkops is enabled, link can't be turned off because
  4240. * turning off the link would also turn off the device.
  4241. */
  4242. else if ((req_link_state == UIC_LINK_OFF_STATE) &&
  4243. (!check_for_bkops || (check_for_bkops &&
  4244. !hba->auto_bkops_enabled))) {
  4245. /*
  4246. * Change controller state to "reset state" which
  4247. * should also put the link in off/reset state
  4248. */
  4249. ufshcd_hba_stop(hba);
  4250. /*
  4251. * TODO: Check if we need any delay to make sure that
  4252. * controller is reset
  4253. */
  4254. ufshcd_set_link_off(hba);
  4255. }
  4256. out:
  4257. return ret;
  4258. }
  4259. static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
  4260. {
  4261. /*
  4262. * If UFS device is either in UFS_Sleep turn off VCC rail to save some
  4263. * power.
  4264. *
  4265. * If UFS device and link is in OFF state, all power supplies (VCC,
  4266. * VCCQ, VCCQ2) can be turned off if power on write protect is not
  4267. * required. If UFS link is inactive (Hibern8 or OFF state) and device
  4268. * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
  4269. *
  4270. * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
  4271. * in low power state which would save some power.
  4272. */
  4273. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  4274. !hba->dev_info.is_lu_power_on_wp) {
  4275. ufshcd_setup_vreg(hba, false);
  4276. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  4277. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  4278. if (!ufshcd_is_link_active(hba)) {
  4279. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  4280. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
  4281. }
  4282. }
  4283. }
  4284. static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
  4285. {
  4286. int ret = 0;
  4287. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  4288. !hba->dev_info.is_lu_power_on_wp) {
  4289. ret = ufshcd_setup_vreg(hba, true);
  4290. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  4291. ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
  4292. if (!ret && !ufshcd_is_link_active(hba)) {
  4293. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
  4294. if (ret)
  4295. goto vcc_disable;
  4296. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
  4297. if (ret)
  4298. goto vccq_lpm;
  4299. }
  4300. }
  4301. goto out;
  4302. vccq_lpm:
  4303. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  4304. vcc_disable:
  4305. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  4306. out:
  4307. return ret;
  4308. }
  4309. static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
  4310. {
  4311. if (ufshcd_is_link_off(hba))
  4312. ufshcd_setup_hba_vreg(hba, false);
  4313. }
  4314. static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
  4315. {
  4316. if (ufshcd_is_link_off(hba))
  4317. ufshcd_setup_hba_vreg(hba, true);
  4318. }
  4319. /**
  4320. * ufshcd_suspend - helper function for suspend operations
  4321. * @hba: per adapter instance
  4322. * @pm_op: desired low power operation type
  4323. *
  4324. * This function will try to put the UFS device and link into low power
  4325. * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
  4326. * (System PM level).
  4327. *
  4328. * If this function is called during shutdown, it will make sure that
  4329. * both UFS device and UFS link is powered off.
  4330. *
  4331. * NOTE: UFS device & link must be active before we enter in this function.
  4332. *
  4333. * Returns 0 for success and non-zero for failure
  4334. */
  4335. static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  4336. {
  4337. int ret = 0;
  4338. enum ufs_pm_level pm_lvl;
  4339. enum ufs_dev_pwr_mode req_dev_pwr_mode;
  4340. enum uic_link_state req_link_state;
  4341. hba->pm_op_in_progress = 1;
  4342. if (!ufshcd_is_shutdown_pm(pm_op)) {
  4343. pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
  4344. hba->rpm_lvl : hba->spm_lvl;
  4345. req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
  4346. req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
  4347. } else {
  4348. req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
  4349. req_link_state = UIC_LINK_OFF_STATE;
  4350. }
  4351. /*
  4352. * If we can't transition into any of the low power modes
  4353. * just gate the clocks.
  4354. */
  4355. ufshcd_hold(hba, false);
  4356. hba->clk_gating.is_suspended = true;
  4357. if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
  4358. req_link_state == UIC_LINK_ACTIVE_STATE) {
  4359. goto disable_clks;
  4360. }
  4361. if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
  4362. (req_link_state == hba->uic_link_state))
  4363. goto out;
  4364. /* UFS device & link must be active before we enter in this function */
  4365. if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
  4366. ret = -EINVAL;
  4367. goto out;
  4368. }
  4369. if (ufshcd_is_runtime_pm(pm_op)) {
  4370. if (ufshcd_can_autobkops_during_suspend(hba)) {
  4371. /*
  4372. * The device is idle with no requests in the queue,
  4373. * allow background operations if bkops status shows
  4374. * that performance might be impacted.
  4375. */
  4376. ret = ufshcd_urgent_bkops(hba);
  4377. if (ret)
  4378. goto enable_gating;
  4379. } else {
  4380. /* make sure that auto bkops is disabled */
  4381. ufshcd_disable_auto_bkops(hba);
  4382. }
  4383. }
  4384. if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
  4385. ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
  4386. !ufshcd_is_runtime_pm(pm_op))) {
  4387. /* ensure that bkops is disabled */
  4388. ufshcd_disable_auto_bkops(hba);
  4389. ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
  4390. if (ret)
  4391. goto enable_gating;
  4392. }
  4393. ret = ufshcd_link_state_transition(hba, req_link_state, 1);
  4394. if (ret)
  4395. goto set_dev_active;
  4396. ufshcd_vreg_set_lpm(hba);
  4397. disable_clks:
  4398. /*
  4399. * The clock scaling needs access to controller registers. Hence, Wait
  4400. * for pending clock scaling work to be done before clocks are
  4401. * turned off.
  4402. */
  4403. if (ufshcd_is_clkscaling_enabled(hba)) {
  4404. devfreq_suspend_device(hba->devfreq);
  4405. hba->clk_scaling.window_start_t = 0;
  4406. }
  4407. /*
  4408. * Call vendor specific suspend callback. As these callbacks may access
  4409. * vendor specific host controller register space call them before the
  4410. * host clocks are ON.
  4411. */
  4412. if (hba->vops && hba->vops->suspend) {
  4413. ret = hba->vops->suspend(hba, pm_op);
  4414. if (ret)
  4415. goto set_link_active;
  4416. }
  4417. if (hba->vops && hba->vops->setup_clocks) {
  4418. ret = hba->vops->setup_clocks(hba, false);
  4419. if (ret)
  4420. goto vops_resume;
  4421. }
  4422. if (!ufshcd_is_link_active(hba))
  4423. ufshcd_setup_clocks(hba, false);
  4424. else
  4425. /* If link is active, device ref_clk can't be switched off */
  4426. __ufshcd_setup_clocks(hba, false, true);
  4427. hba->clk_gating.state = CLKS_OFF;
  4428. /*
  4429. * Disable the host irq as host controller as there won't be any
  4430. * host controller trasanction expected till resume.
  4431. */
  4432. ufshcd_disable_irq(hba);
  4433. /* Put the host controller in low power mode if possible */
  4434. ufshcd_hba_vreg_set_lpm(hba);
  4435. goto out;
  4436. vops_resume:
  4437. if (hba->vops && hba->vops->resume)
  4438. hba->vops->resume(hba, pm_op);
  4439. set_link_active:
  4440. ufshcd_vreg_set_hpm(hba);
  4441. if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
  4442. ufshcd_set_link_active(hba);
  4443. else if (ufshcd_is_link_off(hba))
  4444. ufshcd_host_reset_and_restore(hba);
  4445. set_dev_active:
  4446. if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
  4447. ufshcd_disable_auto_bkops(hba);
  4448. enable_gating:
  4449. hba->clk_gating.is_suspended = false;
  4450. ufshcd_release(hba);
  4451. out:
  4452. hba->pm_op_in_progress = 0;
  4453. return ret;
  4454. }
  4455. /**
  4456. * ufshcd_resume - helper function for resume operations
  4457. * @hba: per adapter instance
  4458. * @pm_op: runtime PM or system PM
  4459. *
  4460. * This function basically brings the UFS device, UniPro link and controller
  4461. * to active state.
  4462. *
  4463. * Returns 0 for success and non-zero for failure
  4464. */
  4465. static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  4466. {
  4467. int ret;
  4468. enum uic_link_state old_link_state;
  4469. hba->pm_op_in_progress = 1;
  4470. old_link_state = hba->uic_link_state;
  4471. ufshcd_hba_vreg_set_hpm(hba);
  4472. /* Make sure clocks are enabled before accessing controller */
  4473. ret = ufshcd_setup_clocks(hba, true);
  4474. if (ret)
  4475. goto out;
  4476. /* enable the host irq as host controller would be active soon */
  4477. ret = ufshcd_enable_irq(hba);
  4478. if (ret)
  4479. goto disable_irq_and_vops_clks;
  4480. ret = ufshcd_vreg_set_hpm(hba);
  4481. if (ret)
  4482. goto disable_irq_and_vops_clks;
  4483. /*
  4484. * Call vendor specific resume callback. As these callbacks may access
  4485. * vendor specific host controller register space call them when the
  4486. * host clocks are ON.
  4487. */
  4488. if (hba->vops && hba->vops->resume) {
  4489. ret = hba->vops->resume(hba, pm_op);
  4490. if (ret)
  4491. goto disable_vreg;
  4492. }
  4493. if (ufshcd_is_link_hibern8(hba)) {
  4494. ret = ufshcd_uic_hibern8_exit(hba);
  4495. if (!ret)
  4496. ufshcd_set_link_active(hba);
  4497. else
  4498. goto vendor_suspend;
  4499. } else if (ufshcd_is_link_off(hba)) {
  4500. ret = ufshcd_host_reset_and_restore(hba);
  4501. /*
  4502. * ufshcd_host_reset_and_restore() should have already
  4503. * set the link state as active
  4504. */
  4505. if (ret || !ufshcd_is_link_active(hba))
  4506. goto vendor_suspend;
  4507. }
  4508. if (!ufshcd_is_ufs_dev_active(hba)) {
  4509. ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
  4510. if (ret)
  4511. goto set_old_link_state;
  4512. }
  4513. /*
  4514. * If BKOPs operations are urgently needed at this moment then
  4515. * keep auto-bkops enabled or else disable it.
  4516. */
  4517. ufshcd_urgent_bkops(hba);
  4518. hba->clk_gating.is_suspended = false;
  4519. if (ufshcd_is_clkscaling_enabled(hba))
  4520. devfreq_resume_device(hba->devfreq);
  4521. /* Schedule clock gating in case of no access to UFS device yet */
  4522. ufshcd_release(hba);
  4523. goto out;
  4524. set_old_link_state:
  4525. ufshcd_link_state_transition(hba, old_link_state, 0);
  4526. vendor_suspend:
  4527. if (hba->vops && hba->vops->suspend)
  4528. hba->vops->suspend(hba, pm_op);
  4529. disable_vreg:
  4530. ufshcd_vreg_set_lpm(hba);
  4531. disable_irq_and_vops_clks:
  4532. ufshcd_disable_irq(hba);
  4533. ufshcd_setup_clocks(hba, false);
  4534. out:
  4535. hba->pm_op_in_progress = 0;
  4536. return ret;
  4537. }
  4538. /**
  4539. * ufshcd_system_suspend - system suspend routine
  4540. * @hba: per adapter instance
  4541. * @pm_op: runtime PM or system PM
  4542. *
  4543. * Check the description of ufshcd_suspend() function for more details.
  4544. *
  4545. * Returns 0 for success and non-zero for failure
  4546. */
  4547. int ufshcd_system_suspend(struct ufs_hba *hba)
  4548. {
  4549. int ret = 0;
  4550. if (!hba || !hba->is_powered)
  4551. return 0;
  4552. if (pm_runtime_suspended(hba->dev)) {
  4553. if (hba->rpm_lvl == hba->spm_lvl)
  4554. /*
  4555. * There is possibility that device may still be in
  4556. * active state during the runtime suspend.
  4557. */
  4558. if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
  4559. hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
  4560. goto out;
  4561. /*
  4562. * UFS device and/or UFS link low power states during runtime
  4563. * suspend seems to be different than what is expected during
  4564. * system suspend. Hence runtime resume the devic & link and
  4565. * let the system suspend low power states to take effect.
  4566. * TODO: If resume takes longer time, we might have optimize
  4567. * it in future by not resuming everything if possible.
  4568. */
  4569. ret = ufshcd_runtime_resume(hba);
  4570. if (ret)
  4571. goto out;
  4572. }
  4573. ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
  4574. out:
  4575. if (!ret)
  4576. hba->is_sys_suspended = true;
  4577. return ret;
  4578. }
  4579. EXPORT_SYMBOL(ufshcd_system_suspend);
  4580. /**
  4581. * ufshcd_system_resume - system resume routine
  4582. * @hba: per adapter instance
  4583. *
  4584. * Returns 0 for success and non-zero for failure
  4585. */
  4586. int ufshcd_system_resume(struct ufs_hba *hba)
  4587. {
  4588. if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
  4589. /*
  4590. * Let the runtime resume take care of resuming
  4591. * if runtime suspended.
  4592. */
  4593. return 0;
  4594. return ufshcd_resume(hba, UFS_SYSTEM_PM);
  4595. }
  4596. EXPORT_SYMBOL(ufshcd_system_resume);
  4597. /**
  4598. * ufshcd_runtime_suspend - runtime suspend routine
  4599. * @hba: per adapter instance
  4600. *
  4601. * Check the description of ufshcd_suspend() function for more details.
  4602. *
  4603. * Returns 0 for success and non-zero for failure
  4604. */
  4605. int ufshcd_runtime_suspend(struct ufs_hba *hba)
  4606. {
  4607. if (!hba || !hba->is_powered)
  4608. return 0;
  4609. return ufshcd_suspend(hba, UFS_RUNTIME_PM);
  4610. }
  4611. EXPORT_SYMBOL(ufshcd_runtime_suspend);
  4612. /**
  4613. * ufshcd_runtime_resume - runtime resume routine
  4614. * @hba: per adapter instance
  4615. *
  4616. * This function basically brings the UFS device, UniPro link and controller
  4617. * to active state. Following operations are done in this function:
  4618. *
  4619. * 1. Turn on all the controller related clocks
  4620. * 2. Bring the UniPro link out of Hibernate state
  4621. * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
  4622. * to active state.
  4623. * 4. If auto-bkops is enabled on the device, disable it.
  4624. *
  4625. * So following would be the possible power state after this function return
  4626. * successfully:
  4627. * S1: UFS device in Active state with VCC rail ON
  4628. * UniPro link in Active state
  4629. * All the UFS/UniPro controller clocks are ON
  4630. *
  4631. * Returns 0 for success and non-zero for failure
  4632. */
  4633. int ufshcd_runtime_resume(struct ufs_hba *hba)
  4634. {
  4635. if (!hba || !hba->is_powered)
  4636. return 0;
  4637. else
  4638. return ufshcd_resume(hba, UFS_RUNTIME_PM);
  4639. }
  4640. EXPORT_SYMBOL(ufshcd_runtime_resume);
  4641. int ufshcd_runtime_idle(struct ufs_hba *hba)
  4642. {
  4643. return 0;
  4644. }
  4645. EXPORT_SYMBOL(ufshcd_runtime_idle);
  4646. /**
  4647. * ufshcd_shutdown - shutdown routine
  4648. * @hba: per adapter instance
  4649. *
  4650. * This function would power off both UFS device and UFS link.
  4651. *
  4652. * Returns 0 always to allow force shutdown even in case of errors.
  4653. */
  4654. int ufshcd_shutdown(struct ufs_hba *hba)
  4655. {
  4656. int ret = 0;
  4657. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
  4658. goto out;
  4659. if (pm_runtime_suspended(hba->dev)) {
  4660. ret = ufshcd_runtime_resume(hba);
  4661. if (ret)
  4662. goto out;
  4663. }
  4664. ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
  4665. out:
  4666. if (ret)
  4667. dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
  4668. /* allow force shutdown even in case of errors */
  4669. return 0;
  4670. }
  4671. EXPORT_SYMBOL(ufshcd_shutdown);
  4672. /**
  4673. * ufshcd_remove - de-allocate SCSI host and host memory space
  4674. * data structure memory
  4675. * @hba - per adapter instance
  4676. */
  4677. void ufshcd_remove(struct ufs_hba *hba)
  4678. {
  4679. scsi_remove_host(hba->host);
  4680. /* disable interrupts */
  4681. ufshcd_disable_intr(hba, hba->intr_mask);
  4682. ufshcd_hba_stop(hba);
  4683. scsi_host_put(hba->host);
  4684. ufshcd_exit_clk_gating(hba);
  4685. if (ufshcd_is_clkscaling_enabled(hba))
  4686. devfreq_remove_device(hba->devfreq);
  4687. ufshcd_hba_exit(hba);
  4688. }
  4689. EXPORT_SYMBOL_GPL(ufshcd_remove);
  4690. /**
  4691. * ufshcd_set_dma_mask - Set dma mask based on the controller
  4692. * addressing capability
  4693. * @hba: per adapter instance
  4694. *
  4695. * Returns 0 for success, non-zero for failure
  4696. */
  4697. static int ufshcd_set_dma_mask(struct ufs_hba *hba)
  4698. {
  4699. if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
  4700. if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
  4701. return 0;
  4702. }
  4703. return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
  4704. }
  4705. /**
  4706. * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
  4707. * @dev: pointer to device handle
  4708. * @hba_handle: driver private handle
  4709. * Returns 0 on success, non-zero value on failure
  4710. */
  4711. int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
  4712. {
  4713. struct Scsi_Host *host;
  4714. struct ufs_hba *hba;
  4715. int err = 0;
  4716. if (!dev) {
  4717. dev_err(dev,
  4718. "Invalid memory reference for dev is NULL\n");
  4719. err = -ENODEV;
  4720. goto out_error;
  4721. }
  4722. host = scsi_host_alloc(&ufshcd_driver_template,
  4723. sizeof(struct ufs_hba));
  4724. if (!host) {
  4725. dev_err(dev, "scsi_host_alloc failed\n");
  4726. err = -ENOMEM;
  4727. goto out_error;
  4728. }
  4729. hba = shost_priv(host);
  4730. hba->host = host;
  4731. hba->dev = dev;
  4732. *hba_handle = hba;
  4733. out_error:
  4734. return err;
  4735. }
  4736. EXPORT_SYMBOL(ufshcd_alloc_host);
  4737. static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
  4738. {
  4739. int ret = 0;
  4740. struct ufs_clk_info *clki;
  4741. struct list_head *head = &hba->clk_list_head;
  4742. if (!head || list_empty(head))
  4743. goto out;
  4744. list_for_each_entry(clki, head, list) {
  4745. if (!IS_ERR_OR_NULL(clki->clk)) {
  4746. if (scale_up && clki->max_freq) {
  4747. if (clki->curr_freq == clki->max_freq)
  4748. continue;
  4749. ret = clk_set_rate(clki->clk, clki->max_freq);
  4750. if (ret) {
  4751. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  4752. __func__, clki->name,
  4753. clki->max_freq, ret);
  4754. break;
  4755. }
  4756. clki->curr_freq = clki->max_freq;
  4757. } else if (!scale_up && clki->min_freq) {
  4758. if (clki->curr_freq == clki->min_freq)
  4759. continue;
  4760. ret = clk_set_rate(clki->clk, clki->min_freq);
  4761. if (ret) {
  4762. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  4763. __func__, clki->name,
  4764. clki->min_freq, ret);
  4765. break;
  4766. }
  4767. clki->curr_freq = clki->min_freq;
  4768. }
  4769. }
  4770. dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
  4771. clki->name, clk_get_rate(clki->clk));
  4772. }
  4773. if (hba->vops->clk_scale_notify)
  4774. hba->vops->clk_scale_notify(hba);
  4775. out:
  4776. return ret;
  4777. }
  4778. static int ufshcd_devfreq_target(struct device *dev,
  4779. unsigned long *freq, u32 flags)
  4780. {
  4781. int err = 0;
  4782. struct ufs_hba *hba = dev_get_drvdata(dev);
  4783. if (!ufshcd_is_clkscaling_enabled(hba))
  4784. return -EINVAL;
  4785. if (*freq == UINT_MAX)
  4786. err = ufshcd_scale_clks(hba, true);
  4787. else if (*freq == 0)
  4788. err = ufshcd_scale_clks(hba, false);
  4789. return err;
  4790. }
  4791. static int ufshcd_devfreq_get_dev_status(struct device *dev,
  4792. struct devfreq_dev_status *stat)
  4793. {
  4794. struct ufs_hba *hba = dev_get_drvdata(dev);
  4795. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  4796. unsigned long flags;
  4797. if (!ufshcd_is_clkscaling_enabled(hba))
  4798. return -EINVAL;
  4799. memset(stat, 0, sizeof(*stat));
  4800. spin_lock_irqsave(hba->host->host_lock, flags);
  4801. if (!scaling->window_start_t)
  4802. goto start_window;
  4803. if (scaling->is_busy_started)
  4804. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  4805. scaling->busy_start_t));
  4806. stat->total_time = jiffies_to_usecs((long)jiffies -
  4807. (long)scaling->window_start_t);
  4808. stat->busy_time = scaling->tot_busy_t;
  4809. start_window:
  4810. scaling->window_start_t = jiffies;
  4811. scaling->tot_busy_t = 0;
  4812. if (hba->outstanding_reqs) {
  4813. scaling->busy_start_t = ktime_get();
  4814. scaling->is_busy_started = true;
  4815. } else {
  4816. scaling->busy_start_t = ktime_set(0, 0);
  4817. scaling->is_busy_started = false;
  4818. }
  4819. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4820. return 0;
  4821. }
  4822. static struct devfreq_dev_profile ufs_devfreq_profile = {
  4823. .polling_ms = 100,
  4824. .target = ufshcd_devfreq_target,
  4825. .get_dev_status = ufshcd_devfreq_get_dev_status,
  4826. };
  4827. /**
  4828. * ufshcd_init - Driver initialization routine
  4829. * @hba: per-adapter instance
  4830. * @mmio_base: base register address
  4831. * @irq: Interrupt line of device
  4832. * Returns 0 on success, non-zero value on failure
  4833. */
  4834. int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
  4835. {
  4836. int err;
  4837. struct Scsi_Host *host = hba->host;
  4838. struct device *dev = hba->dev;
  4839. if (!mmio_base) {
  4840. dev_err(hba->dev,
  4841. "Invalid memory reference for mmio_base is NULL\n");
  4842. err = -ENODEV;
  4843. goto out_error;
  4844. }
  4845. hba->mmio_base = mmio_base;
  4846. hba->irq = irq;
  4847. err = ufshcd_hba_init(hba);
  4848. if (err)
  4849. goto out_error;
  4850. /* Read capabilities registers */
  4851. ufshcd_hba_capabilities(hba);
  4852. /* Get UFS version supported by the controller */
  4853. hba->ufs_version = ufshcd_get_ufs_version(hba);
  4854. /* Get Interrupt bit mask per version */
  4855. hba->intr_mask = ufshcd_get_intr_mask(hba);
  4856. err = ufshcd_set_dma_mask(hba);
  4857. if (err) {
  4858. dev_err(hba->dev, "set dma mask failed\n");
  4859. goto out_disable;
  4860. }
  4861. /* Allocate memory for host memory space */
  4862. err = ufshcd_memory_alloc(hba);
  4863. if (err) {
  4864. dev_err(hba->dev, "Memory allocation failed\n");
  4865. goto out_disable;
  4866. }
  4867. /* Configure LRB */
  4868. ufshcd_host_memory_configure(hba);
  4869. host->can_queue = hba->nutrs;
  4870. host->cmd_per_lun = hba->nutrs;
  4871. host->max_id = UFSHCD_MAX_ID;
  4872. host->max_lun = UFS_MAX_LUNS;
  4873. host->max_channel = UFSHCD_MAX_CHANNEL;
  4874. host->unique_id = host->host_no;
  4875. host->max_cmd_len = MAX_CDB_SIZE;
  4876. hba->max_pwr_info.is_valid = false;
  4877. /* Initailize wait queue for task management */
  4878. init_waitqueue_head(&hba->tm_wq);
  4879. init_waitqueue_head(&hba->tm_tag_wq);
  4880. /* Initialize work queues */
  4881. INIT_WORK(&hba->eh_work, ufshcd_err_handler);
  4882. INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
  4883. /* Initialize UIC command mutex */
  4884. mutex_init(&hba->uic_cmd_mutex);
  4885. /* Initialize mutex for device management commands */
  4886. mutex_init(&hba->dev_cmd.lock);
  4887. /* Initialize device management tag acquire wait queue */
  4888. init_waitqueue_head(&hba->dev_cmd.tag_wq);
  4889. ufshcd_init_clk_gating(hba);
  4890. /* IRQ registration */
  4891. err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
  4892. if (err) {
  4893. dev_err(hba->dev, "request irq failed\n");
  4894. goto exit_gating;
  4895. } else {
  4896. hba->is_irq_enabled = true;
  4897. }
  4898. /* Enable SCSI tag mapping */
  4899. err = scsi_init_shared_tag_map(host, host->can_queue);
  4900. if (err) {
  4901. dev_err(hba->dev, "init shared queue failed\n");
  4902. goto exit_gating;
  4903. }
  4904. err = scsi_add_host(host, hba->dev);
  4905. if (err) {
  4906. dev_err(hba->dev, "scsi_add_host failed\n");
  4907. goto exit_gating;
  4908. }
  4909. /* Host controller enable */
  4910. err = ufshcd_hba_enable(hba);
  4911. if (err) {
  4912. dev_err(hba->dev, "Host controller enable failed\n");
  4913. goto out_remove_scsi_host;
  4914. }
  4915. if (ufshcd_is_clkscaling_enabled(hba)) {
  4916. hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
  4917. "simple_ondemand", NULL);
  4918. if (IS_ERR(hba->devfreq)) {
  4919. dev_err(hba->dev, "Unable to register with devfreq %ld\n",
  4920. PTR_ERR(hba->devfreq));
  4921. goto out_remove_scsi_host;
  4922. }
  4923. /* Suspend devfreq until the UFS device is detected */
  4924. devfreq_suspend_device(hba->devfreq);
  4925. hba->clk_scaling.window_start_t = 0;
  4926. }
  4927. /* Hold auto suspend until async scan completes */
  4928. pm_runtime_get_sync(dev);
  4929. /*
  4930. * The device-initialize-sequence hasn't been invoked yet.
  4931. * Set the device to power-off state
  4932. */
  4933. ufshcd_set_ufs_dev_poweroff(hba);
  4934. async_schedule(ufshcd_async_scan, hba);
  4935. return 0;
  4936. out_remove_scsi_host:
  4937. scsi_remove_host(hba->host);
  4938. exit_gating:
  4939. ufshcd_exit_clk_gating(hba);
  4940. out_disable:
  4941. hba->is_irq_enabled = false;
  4942. scsi_host_put(host);
  4943. ufshcd_hba_exit(hba);
  4944. out_error:
  4945. return err;
  4946. }
  4947. EXPORT_SYMBOL_GPL(ufshcd_init);
  4948. MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
  4949. MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
  4950. MODULE_DESCRIPTION("Generic UFS host controller driver Core");
  4951. MODULE_LICENSE("GPL");
  4952. MODULE_VERSION(UFSHCD_DRIVER_VERSION);