qla_tmpl.c 26 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_tmpl.h"
  9. /* note default template is in big endian */
  10. static const uint32_t ql27xx_fwdt_default_template[] = {
  11. 0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
  12. 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
  13. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  14. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  15. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  16. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  17. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  18. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  19. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  20. 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  21. 0x00000000, 0x04010000, 0x14000000, 0x00000000,
  22. 0x02000000, 0x44000000, 0x09010000, 0x10000000,
  23. 0x00000000, 0x02000000, 0x01010000, 0x1c000000,
  24. 0x00000000, 0x02000000, 0x00600000, 0x00000000,
  25. 0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
  26. 0x02000000, 0x00600000, 0x00000000, 0xcc000000,
  27. 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
  28. 0x10600000, 0x00000000, 0xd4000000, 0x01010000,
  29. 0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
  30. 0x00000060, 0xf0000000, 0x00010000, 0x18000000,
  31. 0x00000000, 0x02000000, 0x00700000, 0x041000c0,
  32. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  33. 0x10700000, 0x041000c0, 0x00010000, 0x18000000,
  34. 0x00000000, 0x02000000, 0x40700000, 0x041000c0,
  35. 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
  36. 0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
  37. 0x18000000, 0x00000000, 0x02000000, 0x007c0000,
  38. 0x040300c4, 0x00010000, 0x18000000, 0x00000000,
  39. 0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
  40. 0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
  41. 0x00000000, 0xc0000000, 0x00010000, 0x18000000,
  42. 0x00000000, 0x02000000, 0x007c0000, 0x04200000,
  43. 0x0b010000, 0x18000000, 0x00000000, 0x02000000,
  44. 0x0c000000, 0x00000000, 0x02010000, 0x20000000,
  45. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  46. 0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
  47. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  48. 0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
  49. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  50. 0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
  51. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  52. 0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
  53. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  54. 0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
  55. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  56. 0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
  57. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  58. 0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
  59. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  60. 0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
  61. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  62. 0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
  63. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  64. 0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
  65. 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
  66. 0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
  67. 0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
  68. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  69. 0x0a000000, 0x04200080, 0x00010000, 0x18000000,
  70. 0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
  71. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  72. 0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
  73. 0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
  74. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  75. 0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
  76. 0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
  77. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  78. 0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
  79. 0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
  80. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  81. 0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
  82. 0x00000000, 0x02000000, 0x00300000, 0x041000c0,
  83. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  84. 0x10300000, 0x041000c0, 0x00010000, 0x18000000,
  85. 0x00000000, 0x02000000, 0x20300000, 0x041000c0,
  86. 0x00010000, 0x18000000, 0x00000000, 0x02000000,
  87. 0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
  88. 0x00000000, 0x02000000, 0x06010000, 0x1c000000,
  89. 0x00000000, 0x02000000, 0x01000000, 0x00000200,
  90. 0xff230200, 0x06010000, 0x1c000000, 0x00000000,
  91. 0x02000000, 0x02000000, 0x00001000, 0x00000000,
  92. 0x07010000, 0x18000000, 0x00000000, 0x02000000,
  93. 0x00000000, 0x01000000, 0x07010000, 0x18000000,
  94. 0x00000000, 0x02000000, 0x00000000, 0x02000000,
  95. 0x07010000, 0x18000000, 0x00000000, 0x02000000,
  96. 0x00000000, 0x03000000, 0x0d010000, 0x14000000,
  97. 0x00000000, 0x02000000, 0x00000000, 0xff000000,
  98. 0x10000000, 0x00000000, 0x00000080,
  99. };
  100. static inline void __iomem *
  101. qla27xx_isp_reg(struct scsi_qla_host *vha)
  102. {
  103. return &vha->hw->iobase->isp24;
  104. }
  105. static inline void
  106. qla27xx_insert16(uint16_t value, void *buf, ulong *len)
  107. {
  108. if (buf) {
  109. buf += *len;
  110. *(__le16 *)buf = cpu_to_le16(value);
  111. }
  112. *len += sizeof(value);
  113. }
  114. static inline void
  115. qla27xx_insert32(uint32_t value, void *buf, ulong *len)
  116. {
  117. if (buf) {
  118. buf += *len;
  119. *(__le32 *)buf = cpu_to_le32(value);
  120. }
  121. *len += sizeof(value);
  122. }
  123. static inline void
  124. qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
  125. {
  126. if (buf && mem && size) {
  127. buf += *len;
  128. memcpy(buf, mem, size);
  129. }
  130. *len += size;
  131. }
  132. static inline void
  133. qla27xx_read8(void *window, void *buf, ulong *len)
  134. {
  135. uint8_t value = ~0;
  136. if (buf) {
  137. value = RD_REG_BYTE((__iomem void *)window);
  138. }
  139. qla27xx_insert32(value, buf, len);
  140. }
  141. static inline void
  142. qla27xx_read16(void *window, void *buf, ulong *len)
  143. {
  144. uint16_t value = ~0;
  145. if (buf) {
  146. value = RD_REG_WORD((__iomem void *)window);
  147. }
  148. qla27xx_insert32(value, buf, len);
  149. }
  150. static inline void
  151. qla27xx_read32(void *window, void *buf, ulong *len)
  152. {
  153. uint32_t value = ~0;
  154. if (buf) {
  155. value = RD_REG_DWORD((__iomem void *)window);
  156. }
  157. qla27xx_insert32(value, buf, len);
  158. }
  159. static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *)
  160. {
  161. return
  162. (width == 1) ? qla27xx_read8 :
  163. (width == 2) ? qla27xx_read16 :
  164. qla27xx_read32;
  165. }
  166. static inline void
  167. qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
  168. uint offset, void *buf, ulong *len)
  169. {
  170. void *window = (void *)reg + offset;
  171. qla27xx_read32(window, buf, len);
  172. }
  173. static inline void
  174. qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
  175. uint offset, uint32_t data, void *buf)
  176. {
  177. __iomem void *window = (void __iomem *)reg + offset;
  178. if (buf) {
  179. WRT_REG_DWORD(window, data);
  180. }
  181. }
  182. static inline void
  183. qla27xx_read_window(__iomem struct device_reg_24xx *reg,
  184. uint32_t addr, uint offset, uint count, uint width, void *buf,
  185. ulong *len)
  186. {
  187. void *window = (void *)reg + offset;
  188. void (*readn)(void *, void *, ulong *) = qla27xx_read_vector(width);
  189. qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
  190. while (count--) {
  191. qla27xx_insert32(addr, buf, len);
  192. readn(window, buf, len);
  193. window += width;
  194. addr++;
  195. }
  196. }
  197. static inline void
  198. qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
  199. {
  200. if (buf)
  201. ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
  202. ql_dbg(ql_dbg_misc + ql_dbg_verbose, NULL, 0xd011,
  203. "Skipping entry %d\n", ent->hdr.entry_type);
  204. }
  205. static int
  206. qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
  207. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  208. {
  209. ql_dbg(ql_dbg_misc, vha, 0xd100,
  210. "%s: nop [%lx]\n", __func__, *len);
  211. qla27xx_skip_entry(ent, buf);
  212. return false;
  213. }
  214. static int
  215. qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
  216. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  217. {
  218. ql_dbg(ql_dbg_misc, vha, 0xd1ff,
  219. "%s: end [%lx]\n", __func__, *len);
  220. qla27xx_skip_entry(ent, buf);
  221. /* terminate */
  222. return true;
  223. }
  224. static int
  225. qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
  226. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  227. {
  228. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  229. ql_dbg(ql_dbg_misc, vha, 0xd200,
  230. "%s: rdio t1 [%lx]\n", __func__, *len);
  231. qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
  232. ent->t256.reg_count, ent->t256.reg_width, buf, len);
  233. return false;
  234. }
  235. static int
  236. qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
  237. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  238. {
  239. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  240. ql_dbg(ql_dbg_misc, vha, 0xd201,
  241. "%s: wrio t1 [%lx]\n", __func__, *len);
  242. qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
  243. qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
  244. return false;
  245. }
  246. static int
  247. qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
  248. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  249. {
  250. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  251. ql_dbg(ql_dbg_misc, vha, 0xd202,
  252. "%s: rdio t2 [%lx]\n", __func__, *len);
  253. qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
  254. qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
  255. ent->t258.reg_count, ent->t258.reg_width, buf, len);
  256. return false;
  257. }
  258. static int
  259. qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
  260. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  261. {
  262. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  263. ql_dbg(ql_dbg_misc, vha, 0xd203,
  264. "%s: wrio t2 [%lx]\n", __func__, *len);
  265. qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
  266. qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
  267. qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
  268. return false;
  269. }
  270. static int
  271. qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
  272. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  273. {
  274. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  275. ql_dbg(ql_dbg_misc, vha, 0xd204,
  276. "%s: rdpci [%lx]\n", __func__, *len);
  277. qla27xx_insert32(ent->t260.pci_offset, buf, len);
  278. qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
  279. return false;
  280. }
  281. static int
  282. qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
  283. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  284. {
  285. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  286. ql_dbg(ql_dbg_misc, vha, 0xd205,
  287. "%s: wrpci [%lx]\n", __func__, *len);
  288. qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
  289. return false;
  290. }
  291. static int
  292. qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
  293. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  294. {
  295. ulong dwords;
  296. ulong start;
  297. ulong end;
  298. ql_dbg(ql_dbg_misc, vha, 0xd206,
  299. "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
  300. start = ent->t262.start_addr;
  301. end = ent->t262.end_addr;
  302. if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
  303. ;
  304. } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
  305. end = vha->hw->fw_memory_size;
  306. if (buf)
  307. ent->t262.end_addr = end;
  308. } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
  309. start = vha->hw->fw_shared_ram_start;
  310. end = vha->hw->fw_shared_ram_end;
  311. if (buf) {
  312. ent->t262.start_addr = start;
  313. ent->t262.end_addr = end;
  314. }
  315. } else {
  316. ql_dbg(ql_dbg_misc, vha, 0xd022,
  317. "%s: unknown area %x\n", __func__, ent->t262.ram_area);
  318. qla27xx_skip_entry(ent, buf);
  319. goto done;
  320. }
  321. if (end < start || end == 0) {
  322. ql_dbg(ql_dbg_misc, vha, 0xd023,
  323. "%s: unusable range (start=%x end=%x)\n", __func__,
  324. ent->t262.end_addr, ent->t262.start_addr);
  325. qla27xx_skip_entry(ent, buf);
  326. goto done;
  327. }
  328. dwords = end - start + 1;
  329. if (buf) {
  330. buf += *len;
  331. qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
  332. }
  333. *len += dwords * sizeof(uint32_t);
  334. done:
  335. return false;
  336. }
  337. static int
  338. qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
  339. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  340. {
  341. uint count = 0;
  342. uint i;
  343. uint length;
  344. ql_dbg(ql_dbg_misc, vha, 0xd207,
  345. "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
  346. if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
  347. for (i = 0; i < vha->hw->max_req_queues; i++) {
  348. struct req_que *req = vha->hw->req_q_map[i];
  349. if (req || !buf) {
  350. length = req ?
  351. req->length : REQUEST_ENTRY_CNT_24XX;
  352. qla27xx_insert16(i, buf, len);
  353. qla27xx_insert16(length, buf, len);
  354. qla27xx_insertbuf(req ? req->ring : NULL,
  355. length * sizeof(*req->ring), buf, len);
  356. count++;
  357. }
  358. }
  359. } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
  360. for (i = 0; i < vha->hw->max_rsp_queues; i++) {
  361. struct rsp_que *rsp = vha->hw->rsp_q_map[i];
  362. if (rsp || !buf) {
  363. length = rsp ?
  364. rsp->length : RESPONSE_ENTRY_CNT_MQ;
  365. qla27xx_insert16(i, buf, len);
  366. qla27xx_insert16(length, buf, len);
  367. qla27xx_insertbuf(rsp ? rsp->ring : NULL,
  368. length * sizeof(*rsp->ring), buf, len);
  369. count++;
  370. }
  371. }
  372. } else {
  373. ql_dbg(ql_dbg_misc, vha, 0xd026,
  374. "%s: unknown queue %x\n", __func__, ent->t263.queue_type);
  375. qla27xx_skip_entry(ent, buf);
  376. }
  377. if (buf)
  378. ent->t263.num_queues = count;
  379. return false;
  380. }
  381. static int
  382. qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
  383. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  384. {
  385. ql_dbg(ql_dbg_misc, vha, 0xd208,
  386. "%s: getfce [%lx]\n", __func__, *len);
  387. if (vha->hw->fce) {
  388. if (buf) {
  389. ent->t264.fce_trace_size = FCE_SIZE;
  390. ent->t264.write_pointer = vha->hw->fce_wr;
  391. ent->t264.base_pointer = vha->hw->fce_dma;
  392. ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
  393. ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
  394. ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
  395. ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
  396. ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
  397. ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
  398. }
  399. qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
  400. } else {
  401. ql_dbg(ql_dbg_misc, vha, 0xd027,
  402. "%s: missing fce\n", __func__);
  403. qla27xx_skip_entry(ent, buf);
  404. }
  405. return false;
  406. }
  407. static int
  408. qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
  409. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  410. {
  411. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  412. ql_dbg(ql_dbg_misc, vha, 0xd209,
  413. "%s: pause risc [%lx]\n", __func__, *len);
  414. if (buf)
  415. qla24xx_pause_risc(reg, vha->hw);
  416. return false;
  417. }
  418. static int
  419. qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
  420. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  421. {
  422. ql_dbg(ql_dbg_misc, vha, 0xd20a,
  423. "%s: reset risc [%lx]\n", __func__, *len);
  424. if (buf)
  425. qla24xx_soft_reset(vha->hw);
  426. return false;
  427. }
  428. static int
  429. qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
  430. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  431. {
  432. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  433. ql_dbg(ql_dbg_misc, vha, 0xd20b,
  434. "%s: dis intr [%lx]\n", __func__, *len);
  435. qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
  436. return false;
  437. }
  438. static int
  439. qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
  440. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  441. {
  442. ql_dbg(ql_dbg_misc, vha, 0xd20c,
  443. "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
  444. if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) {
  445. if (vha->hw->eft) {
  446. if (buf) {
  447. ent->t268.buf_size = EFT_SIZE;
  448. ent->t268.start_addr = vha->hw->eft_dma;
  449. }
  450. qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
  451. } else {
  452. ql_dbg(ql_dbg_misc, vha, 0xd028,
  453. "%s: missing eft\n", __func__);
  454. qla27xx_skip_entry(ent, buf);
  455. }
  456. } else {
  457. ql_dbg(ql_dbg_misc, vha, 0xd02b,
  458. "%s: unknown buffer %x\n", __func__, ent->t268.buf_type);
  459. qla27xx_skip_entry(ent, buf);
  460. }
  461. return false;
  462. }
  463. static int
  464. qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
  465. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  466. {
  467. ql_dbg(ql_dbg_misc, vha, 0xd20d,
  468. "%s: scratch [%lx]\n", __func__, *len);
  469. qla27xx_insert32(0xaaaaaaaa, buf, len);
  470. qla27xx_insert32(0xbbbbbbbb, buf, len);
  471. qla27xx_insert32(0xcccccccc, buf, len);
  472. qla27xx_insert32(0xdddddddd, buf, len);
  473. qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
  474. if (buf)
  475. ent->t269.scratch_size = 5 * sizeof(uint32_t);
  476. return false;
  477. }
  478. static int
  479. qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
  480. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  481. {
  482. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  483. ulong dwords = ent->t270.count;
  484. ulong addr = ent->t270.addr;
  485. ql_dbg(ql_dbg_misc, vha, 0xd20e,
  486. "%s: rdremreg [%lx]\n", __func__, *len);
  487. qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
  488. while (dwords--) {
  489. qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
  490. qla27xx_insert32(addr, buf, len);
  491. qla27xx_read_reg(reg, 0xc4, buf, len);
  492. addr += sizeof(uint32_t);
  493. }
  494. return false;
  495. }
  496. static int
  497. qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
  498. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  499. {
  500. struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
  501. ulong addr = ent->t271.addr;
  502. ulong data = ent->t271.data;
  503. ql_dbg(ql_dbg_misc, vha, 0xd20f,
  504. "%s: wrremreg [%lx]\n", __func__, *len);
  505. qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
  506. qla27xx_write_reg(reg, 0xc4, data, buf);
  507. qla27xx_write_reg(reg, 0xc0, addr, buf);
  508. return false;
  509. }
  510. static int
  511. qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
  512. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  513. {
  514. ulong dwords = ent->t272.count;
  515. ulong start = ent->t272.addr;
  516. ql_dbg(ql_dbg_misc, vha, 0xd210,
  517. "%s: rdremram [%lx]\n", __func__, *len);
  518. if (buf) {
  519. ql_dbg(ql_dbg_misc, vha, 0xd02c,
  520. "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
  521. buf += *len;
  522. qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
  523. }
  524. *len += dwords * sizeof(uint32_t);
  525. return false;
  526. }
  527. static int
  528. qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
  529. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  530. {
  531. ulong dwords = ent->t273.count;
  532. ulong addr = ent->t273.addr;
  533. uint32_t value;
  534. ql_dbg(ql_dbg_misc, vha, 0xd211,
  535. "%s: pcicfg [%lx]\n", __func__, *len);
  536. while (dwords--) {
  537. value = ~0;
  538. if (pci_read_config_dword(vha->hw->pdev, addr, &value))
  539. ql_dbg(ql_dbg_misc, vha, 0xd02d,
  540. "%s: failed pcicfg read at %lx\n", __func__, addr);
  541. qla27xx_insert32(addr, buf, len);
  542. qla27xx_insert32(value, buf, len);
  543. addr += sizeof(uint32_t);
  544. }
  545. return false;
  546. }
  547. static int
  548. qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
  549. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  550. {
  551. uint count = 0;
  552. uint i;
  553. ql_dbg(ql_dbg_misc, vha, 0xd212,
  554. "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
  555. if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
  556. for (i = 0; i < vha->hw->max_req_queues; i++) {
  557. struct req_que *req = vha->hw->req_q_map[i];
  558. if (req || !buf) {
  559. qla27xx_insert16(i, buf, len);
  560. qla27xx_insert16(1, buf, len);
  561. qla27xx_insert32(req && req->out_ptr ?
  562. *req->out_ptr : 0, buf, len);
  563. count++;
  564. }
  565. }
  566. } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
  567. for (i = 0; i < vha->hw->max_rsp_queues; i++) {
  568. struct rsp_que *rsp = vha->hw->rsp_q_map[i];
  569. if (rsp || !buf) {
  570. qla27xx_insert16(i, buf, len);
  571. qla27xx_insert16(1, buf, len);
  572. qla27xx_insert32(rsp && rsp->in_ptr ?
  573. *rsp->in_ptr : 0, buf, len);
  574. count++;
  575. }
  576. }
  577. } else {
  578. ql_dbg(ql_dbg_misc, vha, 0xd02f,
  579. "%s: unknown queue %x\n", __func__, ent->t274.queue_type);
  580. qla27xx_skip_entry(ent, buf);
  581. }
  582. if (buf)
  583. ent->t274.num_queues = count;
  584. if (!count)
  585. qla27xx_skip_entry(ent, buf);
  586. return false;
  587. }
  588. static int
  589. qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
  590. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  591. {
  592. ulong offset = offsetof(typeof(*ent), t275.buffer);
  593. ql_dbg(ql_dbg_misc, vha, 0xd213,
  594. "%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
  595. if (!ent->t275.length) {
  596. ql_dbg(ql_dbg_misc, vha, 0xd020,
  597. "%s: buffer zero length\n", __func__);
  598. qla27xx_skip_entry(ent, buf);
  599. goto done;
  600. }
  601. if (offset + ent->t275.length > ent->hdr.entry_size) {
  602. ql_dbg(ql_dbg_misc, vha, 0xd030,
  603. "%s: buffer overflow\n", __func__);
  604. qla27xx_skip_entry(ent, buf);
  605. goto done;
  606. }
  607. qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
  608. done:
  609. return false;
  610. }
  611. static int
  612. qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
  613. struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
  614. {
  615. ql_dbg(ql_dbg_misc, vha, 0xd2ff,
  616. "%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len);
  617. qla27xx_skip_entry(ent, buf);
  618. return false;
  619. }
  620. struct qla27xx_fwdt_entry_call {
  621. uint type;
  622. int (*call)(
  623. struct scsi_qla_host *,
  624. struct qla27xx_fwdt_entry *,
  625. void *,
  626. ulong *);
  627. };
  628. static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
  629. { ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } ,
  630. { ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } ,
  631. { ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } ,
  632. { ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } ,
  633. { ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } ,
  634. { ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } ,
  635. { ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } ,
  636. { ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } ,
  637. { ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } ,
  638. { ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } ,
  639. { ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } ,
  640. { ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } ,
  641. { ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } ,
  642. { ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } ,
  643. { ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } ,
  644. { ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } ,
  645. { ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } ,
  646. { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
  647. { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
  648. { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
  649. { ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } ,
  650. { ENTRY_TYPE_WRITE_BUF , qla27xx_fwdt_entry_t275 } ,
  651. { -1 , qla27xx_fwdt_entry_other }
  652. };
  653. static inline int (*qla27xx_find_entry(uint type))
  654. (struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *)
  655. {
  656. struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list;
  657. while (list->type < type)
  658. list++;
  659. if (list->type == type)
  660. return list->call;
  661. return qla27xx_fwdt_entry_other;
  662. }
  663. static inline void *
  664. qla27xx_next_entry(void *p)
  665. {
  666. struct qla27xx_fwdt_entry *ent = p;
  667. return p + ent->hdr.entry_size;
  668. }
  669. static void
  670. qla27xx_walk_template(struct scsi_qla_host *vha,
  671. struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
  672. {
  673. struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
  674. ulong count = tmp->entry_count;
  675. ql_dbg(ql_dbg_misc, vha, 0xd01a,
  676. "%s: entry count %lx\n", __func__, count);
  677. while (count--) {
  678. if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len))
  679. break;
  680. ent = qla27xx_next_entry(ent);
  681. }
  682. if (count)
  683. ql_dbg(ql_dbg_misc, vha, 0xd018,
  684. "%s: residual count (%lx)\n", __func__, count);
  685. if (ent->hdr.entry_type != ENTRY_TYPE_TMP_END)
  686. ql_dbg(ql_dbg_misc, vha, 0xd019,
  687. "%s: missing end (%lx)\n", __func__, count);
  688. ql_dbg(ql_dbg_misc, vha, 0xd01b,
  689. "%s: len=%lx\n", __func__, *len);
  690. if (buf) {
  691. ql_log(ql_log_warn, vha, 0xd015,
  692. "Firmware dump saved to temp buffer (%ld/%p)\n",
  693. vha->host_no, vha->hw->fw_dump);
  694. qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
  695. }
  696. }
  697. static void
  698. qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
  699. {
  700. tmp->capture_timestamp = jiffies;
  701. }
  702. static void
  703. qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
  704. {
  705. uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
  706. int rval = 0;
  707. rval = sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu",
  708. v+0, v+1, v+2, v+3, v+4, v+5);
  709. tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0];
  710. tmp->driver_info[1] = v[5] << 8 | v[4];
  711. tmp->driver_info[2] = 0x12345678;
  712. }
  713. static void
  714. qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
  715. struct scsi_qla_host *vha)
  716. {
  717. tmp->firmware_version[0] = vha->hw->fw_major_version;
  718. tmp->firmware_version[1] = vha->hw->fw_minor_version;
  719. tmp->firmware_version[2] = vha->hw->fw_subminor_version;
  720. tmp->firmware_version[3] =
  721. vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes;
  722. tmp->firmware_version[4] =
  723. vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0];
  724. }
  725. static void
  726. ql27xx_edit_template(struct scsi_qla_host *vha,
  727. struct qla27xx_fwdt_template *tmp)
  728. {
  729. qla27xx_time_stamp(tmp);
  730. qla27xx_driver_info(tmp);
  731. qla27xx_firmware_info(tmp, vha);
  732. }
  733. static inline uint32_t
  734. qla27xx_template_checksum(void *p, ulong size)
  735. {
  736. uint32_t *buf = p;
  737. uint64_t sum = 0;
  738. size /= sizeof(*buf);
  739. while (size--)
  740. sum += *buf++;
  741. sum = (sum & 0xffffffff) + (sum >> 32);
  742. return ~sum;
  743. }
  744. static inline int
  745. qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
  746. {
  747. return qla27xx_template_checksum(tmp, tmp->template_size) == 0;
  748. }
  749. static inline int
  750. qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
  751. {
  752. return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
  753. }
  754. static void
  755. qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
  756. {
  757. struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
  758. ulong len;
  759. if (qla27xx_fwdt_template_valid(tmp)) {
  760. len = tmp->template_size;
  761. tmp = memcpy(vha->hw->fw_dump, tmp, len);
  762. ql27xx_edit_template(vha, tmp);
  763. qla27xx_walk_template(vha, tmp, tmp, &len);
  764. vha->hw->fw_dump_len = len;
  765. vha->hw->fw_dumped = 1;
  766. }
  767. }
  768. ulong
  769. qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
  770. {
  771. struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
  772. ulong len = 0;
  773. if (qla27xx_fwdt_template_valid(tmp)) {
  774. len = tmp->template_size;
  775. qla27xx_walk_template(vha, tmp, NULL, &len);
  776. }
  777. return len;
  778. }
  779. ulong
  780. qla27xx_fwdt_template_size(void *p)
  781. {
  782. struct qla27xx_fwdt_template *tmp = p;
  783. return tmp->template_size;
  784. }
  785. ulong
  786. qla27xx_fwdt_template_default_size(void)
  787. {
  788. return sizeof(ql27xx_fwdt_default_template);
  789. }
  790. const void *
  791. qla27xx_fwdt_template_default(void)
  792. {
  793. return ql27xx_fwdt_default_template;
  794. }
  795. int
  796. qla27xx_fwdt_template_valid(void *p)
  797. {
  798. struct qla27xx_fwdt_template *tmp = p;
  799. if (!qla27xx_verify_template_header(tmp)) {
  800. ql_log(ql_log_warn, NULL, 0xd01c,
  801. "%s: template type %x\n", __func__, tmp->template_type);
  802. return false;
  803. }
  804. if (!qla27xx_verify_template_checksum(tmp)) {
  805. ql_log(ql_log_warn, NULL, 0xd01d,
  806. "%s: failed template checksum\n", __func__);
  807. return false;
  808. }
  809. return true;
  810. }
  811. void
  812. qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
  813. {
  814. ulong flags = 0;
  815. if (!hardware_locked)
  816. spin_lock_irqsave(&vha->hw->hardware_lock, flags);
  817. if (!vha->hw->fw_dump)
  818. ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
  819. else if (!vha->hw->fw_dump_template)
  820. ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
  821. else if (vha->hw->fw_dumped)
  822. ql_log(ql_log_warn, vha, 0xd300,
  823. "Firmware has been previously dumped (%p),"
  824. " -- ignoring request\n", vha->hw->fw_dump);
  825. else
  826. qla27xx_execute_fwdt_template(vha);
  827. if (!hardware_locked)
  828. spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
  829. }