qla_mr.c 90 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/pci.h>
  10. #include <linux/ratelimit.h>
  11. #include <linux/vmalloc.h>
  12. #include <scsi/scsi_tcq.h>
  13. #include <linux/utsname.h>
  14. /* QLAFX00 specific Mailbox implementation functions */
  15. /*
  16. * qlafx00_mailbox_command
  17. * Issue mailbox command and waits for completion.
  18. *
  19. * Input:
  20. * ha = adapter block pointer.
  21. * mcp = driver internal mbx struct pointer.
  22. *
  23. * Output:
  24. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  25. *
  26. * Returns:
  27. * 0 : QLA_SUCCESS = cmd performed success
  28. * 1 : QLA_FUNCTION_FAILED (error encountered)
  29. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  30. *
  31. * Context:
  32. * Kernel context.
  33. */
  34. static int
  35. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  36. {
  37. int rval;
  38. unsigned long flags = 0;
  39. device_reg_t *reg;
  40. uint8_t abort_active;
  41. uint8_t io_lock_on;
  42. uint16_t command = 0;
  43. uint32_t *iptr;
  44. uint32_t __iomem *optr;
  45. uint32_t cnt;
  46. uint32_t mboxes;
  47. unsigned long wait_time;
  48. struct qla_hw_data *ha = vha->hw;
  49. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  50. if (ha->pdev->error_state > pci_channel_io_frozen) {
  51. ql_log(ql_log_warn, vha, 0x115c,
  52. "error_state is greater than pci_channel_io_frozen, "
  53. "exiting.\n");
  54. return QLA_FUNCTION_TIMEOUT;
  55. }
  56. if (vha->device_flags & DFLG_DEV_FAILED) {
  57. ql_log(ql_log_warn, vha, 0x115f,
  58. "Device in failed state, exiting.\n");
  59. return QLA_FUNCTION_TIMEOUT;
  60. }
  61. reg = ha->iobase;
  62. io_lock_on = base_vha->flags.init_done;
  63. rval = QLA_SUCCESS;
  64. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  65. if (ha->flags.pci_channel_io_perm_failure) {
  66. ql_log(ql_log_warn, vha, 0x1175,
  67. "Perm failure on EEH timeout MBX, exiting.\n");
  68. return QLA_FUNCTION_TIMEOUT;
  69. }
  70. if (ha->flags.isp82xx_fw_hung) {
  71. /* Setting Link-Down error */
  72. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  73. ql_log(ql_log_warn, vha, 0x1176,
  74. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  75. rval = QLA_FUNCTION_FAILED;
  76. goto premature_exit;
  77. }
  78. /*
  79. * Wait for active mailbox commands to finish by waiting at most tov
  80. * seconds. This is to serialize actual issuing of mailbox cmds during
  81. * non ISP abort time.
  82. */
  83. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  84. /* Timeout occurred. Return error. */
  85. ql_log(ql_log_warn, vha, 0x1177,
  86. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  87. mcp->mb[0]);
  88. return QLA_FUNCTION_TIMEOUT;
  89. }
  90. ha->flags.mbox_busy = 1;
  91. /* Save mailbox command for debug */
  92. ha->mcp32 = mcp;
  93. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  94. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  95. spin_lock_irqsave(&ha->hardware_lock, flags);
  96. /* Load mailbox registers. */
  97. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  98. iptr = mcp->mb;
  99. command = mcp->mb[0];
  100. mboxes = mcp->out_mb;
  101. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  102. if (mboxes & BIT_0)
  103. WRT_REG_DWORD(optr, *iptr);
  104. mboxes >>= 1;
  105. optr++;
  106. iptr++;
  107. }
  108. /* Issue set host interrupt command to send cmd out. */
  109. ha->flags.mbox_int = 0;
  110. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  111. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  112. (uint8_t *)mcp->mb, 16);
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  114. ((uint8_t *)mcp->mb + 0x10), 16);
  115. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  116. ((uint8_t *)mcp->mb + 0x20), 8);
  117. /* Unlock mbx registers and wait for interrupt */
  118. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  119. "Going to unlock irq & waiting for interrupts. "
  120. "jiffies=%lx.\n", jiffies);
  121. /* Wait for mbx cmd completion until timeout */
  122. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  123. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  124. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  125. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  127. } else {
  128. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  129. "Cmd=%x Polling Mode.\n", command);
  130. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  131. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  132. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  133. while (!ha->flags.mbox_int) {
  134. if (time_after(jiffies, wait_time))
  135. break;
  136. /* Check for pending interrupts. */
  137. qla2x00_poll(ha->rsp_q_map[0]);
  138. if (!ha->flags.mbox_int &&
  139. !(IS_QLA2200(ha) &&
  140. command == MBC_LOAD_RISC_RAM_EXTENDED))
  141. usleep_range(10000, 11000);
  142. } /* while */
  143. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  144. "Waited %d sec.\n",
  145. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  146. }
  147. /* Check whether we timed out */
  148. if (ha->flags.mbox_int) {
  149. uint32_t *iptr2;
  150. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  151. "Cmd=%x completed.\n", command);
  152. /* Got interrupt. Clear the flag. */
  153. ha->flags.mbox_int = 0;
  154. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  155. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  156. rval = QLA_FUNCTION_FAILED;
  157. /* Load return mailbox registers. */
  158. iptr2 = mcp->mb;
  159. iptr = (uint32_t *)&ha->mailbox_out32[0];
  160. mboxes = mcp->in_mb;
  161. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  162. if (mboxes & BIT_0)
  163. *iptr2 = *iptr;
  164. mboxes >>= 1;
  165. iptr2++;
  166. iptr++;
  167. }
  168. } else {
  169. rval = QLA_FUNCTION_TIMEOUT;
  170. }
  171. ha->flags.mbox_busy = 0;
  172. /* Clean up */
  173. ha->mcp32 = NULL;
  174. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  175. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  176. "checking for additional resp interrupt.\n");
  177. /* polling mode for non isp_abort commands. */
  178. qla2x00_poll(ha->rsp_q_map[0]);
  179. }
  180. if (rval == QLA_FUNCTION_TIMEOUT &&
  181. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  182. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  183. ha->flags.eeh_busy) {
  184. /* not in dpc. schedule it for dpc to take over. */
  185. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  186. "Timeout, schedule isp_abort_needed.\n");
  187. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  188. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  189. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  190. ql_log(ql_log_info, base_vha, 0x115e,
  191. "Mailbox cmd timeout occurred, cmd=0x%x, "
  192. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  193. "abort.\n", command, mcp->mb[0],
  194. ha->flags.eeh_busy);
  195. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  196. qla2xxx_wake_dpc(vha);
  197. }
  198. } else if (!abort_active) {
  199. /* call abort directly since we are in the DPC thread */
  200. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  201. "Timeout, calling abort_isp.\n");
  202. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  203. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  204. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  205. ql_log(ql_log_info, base_vha, 0x1161,
  206. "Mailbox cmd timeout occurred, cmd=0x%x, "
  207. "mb[0]=0x%x. Scheduling ISP abort ",
  208. command, mcp->mb[0]);
  209. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  210. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  211. if (ha->isp_ops->abort_isp(vha)) {
  212. /* Failed. retry later. */
  213. set_bit(ISP_ABORT_NEEDED,
  214. &vha->dpc_flags);
  215. }
  216. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  217. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  218. "Finished abort_isp.\n");
  219. }
  220. }
  221. }
  222. premature_exit:
  223. /* Allow next mbx cmd to come in. */
  224. complete(&ha->mbx_cmd_comp);
  225. if (rval) {
  226. ql_log(ql_log_warn, base_vha, 0x1163,
  227. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  228. "mb[3]=%x, cmd=%x ****.\n",
  229. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  230. } else {
  231. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  232. }
  233. return rval;
  234. }
  235. /*
  236. * qlafx00_driver_shutdown
  237. * Indicate a driver shutdown to firmware.
  238. *
  239. * Input:
  240. * ha = adapter block pointer.
  241. *
  242. * Returns:
  243. * local function return status code.
  244. *
  245. * Context:
  246. * Kernel context.
  247. */
  248. int
  249. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  250. {
  251. int rval;
  252. struct mbx_cmd_32 mc;
  253. struct mbx_cmd_32 *mcp = &mc;
  254. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  255. "Entered %s.\n", __func__);
  256. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  257. mcp->out_mb = MBX_0;
  258. mcp->in_mb = MBX_0;
  259. if (tmo)
  260. mcp->tov = tmo;
  261. else
  262. mcp->tov = MBX_TOV_SECONDS;
  263. mcp->flags = 0;
  264. rval = qlafx00_mailbox_command(vha, mcp);
  265. if (rval != QLA_SUCCESS) {
  266. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  267. "Failed=%x.\n", rval);
  268. } else {
  269. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  270. "Done %s.\n", __func__);
  271. }
  272. return rval;
  273. }
  274. /*
  275. * qlafx00_get_firmware_state
  276. * Get adapter firmware state.
  277. *
  278. * Input:
  279. * ha = adapter block pointer.
  280. * TARGET_QUEUE_LOCK must be released.
  281. * ADAPTER_STATE_LOCK must be released.
  282. *
  283. * Returns:
  284. * qla7xxx local function return status code.
  285. *
  286. * Context:
  287. * Kernel context.
  288. */
  289. static int
  290. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  291. {
  292. int rval;
  293. struct mbx_cmd_32 mc;
  294. struct mbx_cmd_32 *mcp = &mc;
  295. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  296. "Entered %s.\n", __func__);
  297. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  298. mcp->out_mb = MBX_0;
  299. mcp->in_mb = MBX_1|MBX_0;
  300. mcp->tov = MBX_TOV_SECONDS;
  301. mcp->flags = 0;
  302. rval = qlafx00_mailbox_command(vha, mcp);
  303. /* Return firmware states. */
  304. states[0] = mcp->mb[1];
  305. if (rval != QLA_SUCCESS) {
  306. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  307. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  308. } else {
  309. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  310. "Done %s.\n", __func__);
  311. }
  312. return rval;
  313. }
  314. /*
  315. * qlafx00_init_firmware
  316. * Initialize adapter firmware.
  317. *
  318. * Input:
  319. * ha = adapter block pointer.
  320. * dptr = Initialization control block pointer.
  321. * size = size of initialization control block.
  322. * TARGET_QUEUE_LOCK must be released.
  323. * ADAPTER_STATE_LOCK must be released.
  324. *
  325. * Returns:
  326. * qlafx00 local function return status code.
  327. *
  328. * Context:
  329. * Kernel context.
  330. */
  331. int
  332. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  333. {
  334. int rval;
  335. struct mbx_cmd_32 mc;
  336. struct mbx_cmd_32 *mcp = &mc;
  337. struct qla_hw_data *ha = vha->hw;
  338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  339. "Entered %s.\n", __func__);
  340. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  341. mcp->mb[1] = 0;
  342. mcp->mb[2] = MSD(ha->init_cb_dma);
  343. mcp->mb[3] = LSD(ha->init_cb_dma);
  344. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  345. mcp->in_mb = MBX_0;
  346. mcp->buf_size = size;
  347. mcp->flags = MBX_DMA_OUT;
  348. mcp->tov = MBX_TOV_SECONDS;
  349. rval = qlafx00_mailbox_command(vha, mcp);
  350. if (rval != QLA_SUCCESS) {
  351. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  352. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  353. } else {
  354. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  355. "Done %s.\n", __func__);
  356. }
  357. return rval;
  358. }
  359. /*
  360. * qlafx00_mbx_reg_test
  361. */
  362. static int
  363. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  364. {
  365. int rval;
  366. struct mbx_cmd_32 mc;
  367. struct mbx_cmd_32 *mcp = &mc;
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  369. "Entered %s.\n", __func__);
  370. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  371. mcp->mb[1] = 0xAAAA;
  372. mcp->mb[2] = 0x5555;
  373. mcp->mb[3] = 0xAA55;
  374. mcp->mb[4] = 0x55AA;
  375. mcp->mb[5] = 0xA5A5;
  376. mcp->mb[6] = 0x5A5A;
  377. mcp->mb[7] = 0x2525;
  378. mcp->mb[8] = 0xBBBB;
  379. mcp->mb[9] = 0x6666;
  380. mcp->mb[10] = 0xBB66;
  381. mcp->mb[11] = 0x66BB;
  382. mcp->mb[12] = 0xB6B6;
  383. mcp->mb[13] = 0x6B6B;
  384. mcp->mb[14] = 0x3636;
  385. mcp->mb[15] = 0xCCCC;
  386. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  387. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  388. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  389. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  390. mcp->buf_size = 0;
  391. mcp->flags = MBX_DMA_OUT;
  392. mcp->tov = MBX_TOV_SECONDS;
  393. rval = qlafx00_mailbox_command(vha, mcp);
  394. if (rval == QLA_SUCCESS) {
  395. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  396. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  397. rval = QLA_FUNCTION_FAILED;
  398. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  399. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  400. rval = QLA_FUNCTION_FAILED;
  401. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  402. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  403. rval = QLA_FUNCTION_FAILED;
  404. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  405. mcp->mb[31] != 0xCCCC)
  406. rval = QLA_FUNCTION_FAILED;
  407. }
  408. if (rval != QLA_SUCCESS) {
  409. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  410. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  411. } else {
  412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  413. "Done %s.\n", __func__);
  414. }
  415. return rval;
  416. }
  417. /**
  418. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  419. * @ha: HA context
  420. *
  421. * Returns 0 on success.
  422. */
  423. int
  424. qlafx00_pci_config(scsi_qla_host_t *vha)
  425. {
  426. uint16_t w;
  427. struct qla_hw_data *ha = vha->hw;
  428. pci_set_master(ha->pdev);
  429. pci_try_set_mwi(ha->pdev);
  430. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  431. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  432. w &= ~PCI_COMMAND_INTX_DISABLE;
  433. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  434. /* PCIe -- adjust Maximum Read Request Size (2048). */
  435. if (pci_is_pcie(ha->pdev))
  436. pcie_set_readrq(ha->pdev, 2048);
  437. ha->chip_revision = ha->pdev->revision;
  438. return QLA_SUCCESS;
  439. }
  440. /**
  441. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  442. * @ha: HA context
  443. *
  444. */
  445. static inline void
  446. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  447. {
  448. unsigned long flags = 0;
  449. struct qla_hw_data *ha = vha->hw;
  450. int i, core;
  451. uint32_t cnt;
  452. uint32_t reg_val;
  453. spin_lock_irqsave(&ha->hardware_lock, flags);
  454. QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
  455. QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
  456. /* stop the XOR DMA engines */
  457. QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
  458. QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
  459. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
  460. QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
  461. /* stop the IDMA engines */
  462. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
  463. reg_val &= ~(1<<12);
  464. QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
  465. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
  466. reg_val &= ~(1<<12);
  467. QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
  468. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
  469. reg_val &= ~(1<<12);
  470. QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
  471. reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
  472. reg_val &= ~(1<<12);
  473. QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
  474. for (i = 0; i < 100000; i++) {
  475. if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
  476. (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
  477. break;
  478. udelay(100);
  479. }
  480. /* Set all 4 cores in reset */
  481. for (i = 0; i < 4; i++) {
  482. QLAFX00_SET_HBA_SOC_REG(ha,
  483. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  484. QLAFX00_SET_HBA_SOC_REG(ha,
  485. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  486. }
  487. /* Reset all units in Fabric */
  488. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
  489. /* */
  490. QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
  491. QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
  492. /* Set all 4 core Memory Power Down Registers */
  493. for (i = 0; i < 5; i++) {
  494. QLAFX00_SET_HBA_SOC_REG(ha,
  495. (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
  496. }
  497. /* Reset all interrupt control registers */
  498. for (i = 0; i < 115; i++) {
  499. QLAFX00_SET_HBA_SOC_REG(ha,
  500. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  501. }
  502. /* Reset Timers control registers. per core */
  503. for (core = 0; core < 4; core++)
  504. for (i = 0; i < 8; i++)
  505. QLAFX00_SET_HBA_SOC_REG(ha,
  506. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  507. /* Reset per core IRQ ack register */
  508. for (core = 0; core < 4; core++)
  509. QLAFX00_SET_HBA_SOC_REG(ha,
  510. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  511. /* Set Fabric control and config to defaults */
  512. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  513. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  514. /* Kick in Fabric units */
  515. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  516. /* Kick in Core0 to start boot process */
  517. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  518. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  519. /* Wait 10secs for soft-reset to complete. */
  520. for (cnt = 10; cnt; cnt--) {
  521. msleep(1000);
  522. barrier();
  523. }
  524. }
  525. /**
  526. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  527. * @ha: HA context
  528. *
  529. * Returns 0 on success.
  530. */
  531. void
  532. qlafx00_soft_reset(scsi_qla_host_t *vha)
  533. {
  534. struct qla_hw_data *ha = vha->hw;
  535. if (unlikely(pci_channel_offline(ha->pdev) &&
  536. ha->flags.pci_channel_io_perm_failure))
  537. return;
  538. ha->isp_ops->disable_intrs(ha);
  539. qlafx00_soc_cpu_reset(vha);
  540. }
  541. /**
  542. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  543. * @ha: HA context
  544. *
  545. * Returns 0 on success.
  546. */
  547. int
  548. qlafx00_chip_diag(scsi_qla_host_t *vha)
  549. {
  550. int rval = 0;
  551. struct qla_hw_data *ha = vha->hw;
  552. struct req_que *req = ha->req_q_map[0];
  553. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  554. rval = qlafx00_mbx_reg_test(vha);
  555. if (rval) {
  556. ql_log(ql_log_warn, vha, 0x1165,
  557. "Failed mailbox send register test\n");
  558. } else {
  559. /* Flag a successful rval */
  560. rval = QLA_SUCCESS;
  561. }
  562. return rval;
  563. }
  564. void
  565. qlafx00_config_rings(struct scsi_qla_host *vha)
  566. {
  567. struct qla_hw_data *ha = vha->hw;
  568. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  569. WRT_REG_DWORD(&reg->req_q_in, 0);
  570. WRT_REG_DWORD(&reg->req_q_out, 0);
  571. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  572. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  573. /* PCI posting */
  574. RD_REG_DWORD(&reg->rsp_q_out);
  575. }
  576. char *
  577. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  578. {
  579. struct qla_hw_data *ha = vha->hw;
  580. if (pci_is_pcie(ha->pdev)) {
  581. strcpy(str, "PCIe iSA");
  582. return str;
  583. }
  584. return str;
  585. }
  586. char *
  587. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
  588. {
  589. struct qla_hw_data *ha = vha->hw;
  590. snprintf(str, size, "%s", ha->mr.fw_version);
  591. return str;
  592. }
  593. void
  594. qlafx00_enable_intrs(struct qla_hw_data *ha)
  595. {
  596. unsigned long flags = 0;
  597. spin_lock_irqsave(&ha->hardware_lock, flags);
  598. ha->interrupts_on = 1;
  599. QLAFX00_ENABLE_ICNTRL_REG(ha);
  600. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  601. }
  602. void
  603. qlafx00_disable_intrs(struct qla_hw_data *ha)
  604. {
  605. unsigned long flags = 0;
  606. spin_lock_irqsave(&ha->hardware_lock, flags);
  607. ha->interrupts_on = 0;
  608. QLAFX00_DISABLE_ICNTRL_REG(ha);
  609. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  610. }
  611. int
  612. qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
  613. {
  614. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  615. }
  616. int
  617. qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
  618. {
  619. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  620. }
  621. int
  622. qlafx00_loop_reset(scsi_qla_host_t *vha)
  623. {
  624. int ret;
  625. struct fc_port *fcport;
  626. struct qla_hw_data *ha = vha->hw;
  627. if (ql2xtargetreset) {
  628. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  629. if (fcport->port_type != FCT_TARGET)
  630. continue;
  631. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  632. if (ret != QLA_SUCCESS) {
  633. ql_dbg(ql_dbg_taskm, vha, 0x803d,
  634. "Bus Reset failed: Reset=%d "
  635. "d_id=%x.\n", ret, fcport->d_id.b24);
  636. }
  637. }
  638. }
  639. return QLA_SUCCESS;
  640. }
  641. int
  642. qlafx00_iospace_config(struct qla_hw_data *ha)
  643. {
  644. if (pci_request_selected_regions(ha->pdev, ha->bars,
  645. QLA2XXX_DRIVER_NAME)) {
  646. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  647. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  648. pci_name(ha->pdev));
  649. goto iospace_error_exit;
  650. }
  651. /* Use MMIO operations for all accesses. */
  652. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  653. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  654. "Invalid pci I/O region size (%s).\n",
  655. pci_name(ha->pdev));
  656. goto iospace_error_exit;
  657. }
  658. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  659. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  660. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  661. pci_name(ha->pdev));
  662. goto iospace_error_exit;
  663. }
  664. ha->cregbase =
  665. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  666. if (!ha->cregbase) {
  667. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  668. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  669. goto iospace_error_exit;
  670. }
  671. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  672. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  673. "region #2 not an MMIO resource (%s), aborting\n",
  674. pci_name(ha->pdev));
  675. goto iospace_error_exit;
  676. }
  677. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  678. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  679. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  680. pci_name(ha->pdev));
  681. goto iospace_error_exit;
  682. }
  683. ha->iobase =
  684. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  685. if (!ha->iobase) {
  686. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  687. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  688. goto iospace_error_exit;
  689. }
  690. /* Determine queue resources */
  691. ha->max_req_queues = ha->max_rsp_queues = 1;
  692. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  693. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  694. ha->bars, ha->cregbase, ha->iobase);
  695. return 0;
  696. iospace_error_exit:
  697. return -ENOMEM;
  698. }
  699. static void
  700. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  701. {
  702. struct qla_hw_data *ha = vha->hw;
  703. struct req_que *req = ha->req_q_map[0];
  704. struct rsp_que *rsp = ha->rsp_q_map[0];
  705. req->length_fx00 = req->length;
  706. req->ring_fx00 = req->ring;
  707. req->dma_fx00 = req->dma;
  708. rsp->length_fx00 = rsp->length;
  709. rsp->ring_fx00 = rsp->ring;
  710. rsp->dma_fx00 = rsp->dma;
  711. ql_dbg(ql_dbg_init, vha, 0x012d,
  712. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  713. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  714. req->length_fx00, (u64)req->dma_fx00);
  715. ql_dbg(ql_dbg_init, vha, 0x012e,
  716. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  717. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  718. rsp->length_fx00, (u64)rsp->dma_fx00);
  719. }
  720. static int
  721. qlafx00_config_queues(struct scsi_qla_host *vha)
  722. {
  723. struct qla_hw_data *ha = vha->hw;
  724. struct req_que *req = ha->req_q_map[0];
  725. struct rsp_que *rsp = ha->rsp_q_map[0];
  726. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  727. req->length = ha->req_que_len;
  728. req->ring = (void *)ha->iobase + ha->req_que_off;
  729. req->dma = bar2_hdl + ha->req_que_off;
  730. if ((!req->ring) || (req->length == 0)) {
  731. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  732. "Unable to allocate memory for req_ring\n");
  733. return QLA_FUNCTION_FAILED;
  734. }
  735. ql_dbg(ql_dbg_init, vha, 0x0130,
  736. "req: %p req_ring pointer %p req len 0x%x "
  737. "req off 0x%x\n, req->dma: 0x%llx",
  738. req, req->ring, req->length,
  739. ha->req_que_off, (u64)req->dma);
  740. rsp->length = ha->rsp_que_len;
  741. rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
  742. rsp->dma = bar2_hdl + ha->rsp_que_off;
  743. if ((!rsp->ring) || (rsp->length == 0)) {
  744. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  745. "Unable to allocate memory for rsp_ring\n");
  746. return QLA_FUNCTION_FAILED;
  747. }
  748. ql_dbg(ql_dbg_init, vha, 0x0132,
  749. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  750. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  751. rsp, rsp->ring, rsp->length,
  752. ha->rsp_que_off, (u64)rsp->dma);
  753. return QLA_SUCCESS;
  754. }
  755. static int
  756. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  757. {
  758. int rval = 0;
  759. unsigned long wtime;
  760. uint16_t wait_time; /* Wait time */
  761. struct qla_hw_data *ha = vha->hw;
  762. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  763. uint32_t aenmbx, aenmbx7 = 0;
  764. uint32_t pseudo_aen;
  765. uint32_t state[5];
  766. bool done = false;
  767. /* 30 seconds wait - Adjust if required */
  768. wait_time = 30;
  769. pseudo_aen = RD_REG_DWORD(&reg->pseudoaen);
  770. if (pseudo_aen == 1) {
  771. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  772. ha->mbx_intr_code = MSW(aenmbx7);
  773. ha->rqstq_intr_code = LSW(aenmbx7);
  774. rval = qlafx00_driver_shutdown(vha, 10);
  775. if (rval != QLA_SUCCESS)
  776. qlafx00_soft_reset(vha);
  777. }
  778. /* wait time before firmware ready */
  779. wtime = jiffies + (wait_time * HZ);
  780. do {
  781. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  782. barrier();
  783. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  784. "aenmbx: 0x%x\n", aenmbx);
  785. switch (aenmbx) {
  786. case MBA_FW_NOT_STARTED:
  787. case MBA_FW_STARTING:
  788. break;
  789. case MBA_SYSTEM_ERR:
  790. case MBA_REQ_TRANSFER_ERR:
  791. case MBA_RSP_TRANSFER_ERR:
  792. case MBA_FW_INIT_FAILURE:
  793. qlafx00_soft_reset(vha);
  794. break;
  795. case MBA_FW_RESTART_CMPLT:
  796. /* Set the mbx and rqstq intr code */
  797. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  798. ha->mbx_intr_code = MSW(aenmbx7);
  799. ha->rqstq_intr_code = LSW(aenmbx7);
  800. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  801. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  802. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  803. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  804. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  805. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  806. ql_dbg(ql_dbg_init, vha, 0x0134,
  807. "f/w returned mbx_intr_code: 0x%x, "
  808. "rqstq_intr_code: 0x%x\n",
  809. ha->mbx_intr_code, ha->rqstq_intr_code);
  810. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  811. rval = QLA_SUCCESS;
  812. done = true;
  813. break;
  814. default:
  815. if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
  816. break;
  817. /* If fw is apparently not ready. In order to continue,
  818. * we might need to issue Mbox cmd, but the problem is
  819. * that the DoorBell vector values that come with the
  820. * 8060 AEN are most likely gone by now (and thus no
  821. * bell would be rung on the fw side when mbox cmd is
  822. * issued). We have to therefore grab the 8060 AEN
  823. * shadow regs (filled in by FW when the last 8060
  824. * AEN was being posted).
  825. * Do the following to determine what is needed in
  826. * order to get the FW ready:
  827. * 1. reload the 8060 AEN values from the shadow regs
  828. * 2. clear int status to get rid of possible pending
  829. * interrupts
  830. * 3. issue Get FW State Mbox cmd to determine fw state
  831. * Set the mbx and rqstq intr code from Shadow Regs
  832. */
  833. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  834. ha->mbx_intr_code = MSW(aenmbx7);
  835. ha->rqstq_intr_code = LSW(aenmbx7);
  836. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  837. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  838. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  839. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  840. ql_dbg(ql_dbg_init, vha, 0x0135,
  841. "f/w returned mbx_intr_code: 0x%x, "
  842. "rqstq_intr_code: 0x%x\n",
  843. ha->mbx_intr_code, ha->rqstq_intr_code);
  844. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  845. /* Get the FW state */
  846. rval = qlafx00_get_firmware_state(vha, state);
  847. if (rval != QLA_SUCCESS) {
  848. /* Retry if timer has not expired */
  849. break;
  850. }
  851. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  852. /* Firmware is waiting to be
  853. * initialized by driver
  854. */
  855. rval = QLA_SUCCESS;
  856. done = true;
  857. break;
  858. }
  859. /* Issue driver shutdown and wait until f/w recovers.
  860. * Driver should continue to poll until 8060 AEN is
  861. * received indicating firmware recovery.
  862. */
  863. ql_dbg(ql_dbg_init, vha, 0x0136,
  864. "Sending Driver shutdown fw_state 0x%x\n",
  865. state[0]);
  866. rval = qlafx00_driver_shutdown(vha, 10);
  867. if (rval != QLA_SUCCESS) {
  868. rval = QLA_FUNCTION_FAILED;
  869. break;
  870. }
  871. msleep(500);
  872. wtime = jiffies + (wait_time * HZ);
  873. break;
  874. }
  875. if (!done) {
  876. if (time_after_eq(jiffies, wtime)) {
  877. ql_dbg(ql_dbg_init, vha, 0x0137,
  878. "Init f/w failed: aen[7]: 0x%x\n",
  879. RD_REG_DWORD(&reg->aenmailbox7));
  880. rval = QLA_FUNCTION_FAILED;
  881. done = true;
  882. break;
  883. }
  884. /* Delay for a while */
  885. msleep(500);
  886. }
  887. } while (!done);
  888. if (rval)
  889. ql_dbg(ql_dbg_init, vha, 0x0138,
  890. "%s **** FAILED ****.\n", __func__);
  891. else
  892. ql_dbg(ql_dbg_init, vha, 0x0139,
  893. "%s **** SUCCESS ****.\n", __func__);
  894. return rval;
  895. }
  896. /*
  897. * qlafx00_fw_ready() - Waits for firmware ready.
  898. * @ha: HA context
  899. *
  900. * Returns 0 on success.
  901. */
  902. int
  903. qlafx00_fw_ready(scsi_qla_host_t *vha)
  904. {
  905. int rval;
  906. unsigned long wtime;
  907. uint16_t wait_time; /* Wait time if loop is coming ready */
  908. uint32_t state[5];
  909. rval = QLA_SUCCESS;
  910. wait_time = 10;
  911. /* wait time before firmware ready */
  912. wtime = jiffies + (wait_time * HZ);
  913. /* Wait for ISP to finish init */
  914. if (!vha->flags.init_done)
  915. ql_dbg(ql_dbg_init, vha, 0x013a,
  916. "Waiting for init to complete...\n");
  917. do {
  918. rval = qlafx00_get_firmware_state(vha, state);
  919. if (rval == QLA_SUCCESS) {
  920. if (state[0] == FSTATE_FX00_INITIALIZED) {
  921. ql_dbg(ql_dbg_init, vha, 0x013b,
  922. "fw_state=%x\n", state[0]);
  923. rval = QLA_SUCCESS;
  924. break;
  925. }
  926. }
  927. rval = QLA_FUNCTION_FAILED;
  928. if (time_after_eq(jiffies, wtime))
  929. break;
  930. /* Delay for a while */
  931. msleep(500);
  932. ql_dbg(ql_dbg_init, vha, 0x013c,
  933. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  934. } while (1);
  935. if (rval)
  936. ql_dbg(ql_dbg_init, vha, 0x013d,
  937. "Firmware ready **** FAILED ****.\n");
  938. else
  939. ql_dbg(ql_dbg_init, vha, 0x013e,
  940. "Firmware ready **** SUCCESS ****.\n");
  941. return rval;
  942. }
  943. static int
  944. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  945. struct list_head *new_fcports)
  946. {
  947. int rval;
  948. uint16_t tgt_id;
  949. fc_port_t *fcport, *new_fcport;
  950. int found;
  951. struct qla_hw_data *ha = vha->hw;
  952. rval = QLA_SUCCESS;
  953. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  954. return QLA_FUNCTION_FAILED;
  955. if ((atomic_read(&vha->loop_down_timer) ||
  956. STATE_TRANSITION(vha))) {
  957. atomic_set(&vha->loop_down_timer, 0);
  958. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  959. return QLA_FUNCTION_FAILED;
  960. }
  961. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  962. "Listing Target bit map...\n");
  963. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  964. 0x2089, (uint8_t *)ha->gid_list, 32);
  965. /* Allocate temporary rmtport for any new rmtports discovered. */
  966. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  967. if (new_fcport == NULL)
  968. return QLA_MEMORY_ALLOC_FAILED;
  969. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  970. QLAFX00_TGT_NODE_LIST_SIZE) {
  971. /* Send get target node info */
  972. new_fcport->tgt_id = tgt_id;
  973. rval = qlafx00_fx_disc(vha, new_fcport,
  974. FXDISC_GET_TGT_NODE_INFO);
  975. if (rval != QLA_SUCCESS) {
  976. ql_log(ql_log_warn, vha, 0x208a,
  977. "Target info scan failed -- assuming zero-entry "
  978. "result...\n");
  979. continue;
  980. }
  981. /* Locate matching device in database. */
  982. found = 0;
  983. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  984. if (memcmp(new_fcport->port_name,
  985. fcport->port_name, WWN_SIZE))
  986. continue;
  987. found++;
  988. /*
  989. * If tgt_id is same and state FCS_ONLINE, nothing
  990. * changed.
  991. */
  992. if (fcport->tgt_id == new_fcport->tgt_id &&
  993. atomic_read(&fcport->state) == FCS_ONLINE)
  994. break;
  995. /*
  996. * Tgt ID changed or device was marked to be updated.
  997. */
  998. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  999. "TGT-ID Change(%s): Present tgt id: "
  1000. "0x%x state: 0x%x "
  1001. "wwnn = %llx wwpn = %llx.\n",
  1002. __func__, fcport->tgt_id,
  1003. atomic_read(&fcport->state),
  1004. (unsigned long long)wwn_to_u64(fcport->node_name),
  1005. (unsigned long long)wwn_to_u64(fcport->port_name));
  1006. ql_log(ql_log_info, vha, 0x208c,
  1007. "TGT-ID Announce(%s): Discovered tgt "
  1008. "id 0x%x wwnn = %llx "
  1009. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1010. (unsigned long long)
  1011. wwn_to_u64(new_fcport->node_name),
  1012. (unsigned long long)
  1013. wwn_to_u64(new_fcport->port_name));
  1014. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1015. fcport->old_tgt_id = fcport->tgt_id;
  1016. fcport->tgt_id = new_fcport->tgt_id;
  1017. ql_log(ql_log_info, vha, 0x208d,
  1018. "TGT-ID: New fcport Added: %p\n", fcport);
  1019. qla2x00_update_fcport(vha, fcport);
  1020. } else {
  1021. ql_log(ql_log_info, vha, 0x208e,
  1022. " Existing TGT-ID %x did not get "
  1023. " offline event from firmware.\n",
  1024. fcport->old_tgt_id);
  1025. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1026. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1027. kfree(new_fcport);
  1028. return rval;
  1029. }
  1030. break;
  1031. }
  1032. if (found)
  1033. continue;
  1034. /* If device was not in our fcports list, then add it. */
  1035. list_add_tail(&new_fcport->list, new_fcports);
  1036. /* Allocate a new replacement fcport. */
  1037. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1038. if (new_fcport == NULL)
  1039. return QLA_MEMORY_ALLOC_FAILED;
  1040. }
  1041. kfree(new_fcport);
  1042. return rval;
  1043. }
  1044. /*
  1045. * qlafx00_configure_all_targets
  1046. * Setup target devices with node ID's.
  1047. *
  1048. * Input:
  1049. * ha = adapter block pointer.
  1050. *
  1051. * Returns:
  1052. * 0 = success.
  1053. * BIT_0 = error
  1054. */
  1055. static int
  1056. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1057. {
  1058. int rval;
  1059. fc_port_t *fcport, *rmptemp;
  1060. LIST_HEAD(new_fcports);
  1061. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1062. FXDISC_GET_TGT_NODE_LIST);
  1063. if (rval != QLA_SUCCESS) {
  1064. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1065. return rval;
  1066. }
  1067. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1068. if (rval != QLA_SUCCESS) {
  1069. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1070. return rval;
  1071. }
  1072. /*
  1073. * Delete all previous devices marked lost.
  1074. */
  1075. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1076. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1077. break;
  1078. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1079. if (fcport->port_type != FCT_INITIATOR)
  1080. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1081. }
  1082. }
  1083. /*
  1084. * Add the new devices to our devices list.
  1085. */
  1086. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1087. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1088. break;
  1089. qla2x00_update_fcport(vha, fcport);
  1090. list_move_tail(&fcport->list, &vha->vp_fcports);
  1091. ql_log(ql_log_info, vha, 0x208f,
  1092. "Attach new target id 0x%x wwnn = %llx "
  1093. "wwpn = %llx.\n",
  1094. fcport->tgt_id,
  1095. (unsigned long long)wwn_to_u64(fcport->node_name),
  1096. (unsigned long long)wwn_to_u64(fcport->port_name));
  1097. }
  1098. /* Free all new device structures not processed. */
  1099. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1100. list_del(&fcport->list);
  1101. kfree(fcport);
  1102. }
  1103. return rval;
  1104. }
  1105. /*
  1106. * qlafx00_configure_devices
  1107. * Updates Fibre Channel Device Database with what is actually on loop.
  1108. *
  1109. * Input:
  1110. * ha = adapter block pointer.
  1111. *
  1112. * Returns:
  1113. * 0 = success.
  1114. * 1 = error.
  1115. * 2 = database was full and device was not configured.
  1116. */
  1117. int
  1118. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1119. {
  1120. int rval;
  1121. unsigned long flags, save_flags;
  1122. rval = QLA_SUCCESS;
  1123. save_flags = flags = vha->dpc_flags;
  1124. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1125. "Configure devices -- dpc flags =0x%lx\n", flags);
  1126. rval = qlafx00_configure_all_targets(vha);
  1127. if (rval == QLA_SUCCESS) {
  1128. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1129. rval = QLA_FUNCTION_FAILED;
  1130. } else {
  1131. atomic_set(&vha->loop_state, LOOP_READY);
  1132. ql_log(ql_log_info, vha, 0x2091,
  1133. "Device Ready\n");
  1134. }
  1135. }
  1136. if (rval) {
  1137. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1138. "%s *** FAILED ***.\n", __func__);
  1139. } else {
  1140. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1141. "%s: exiting normally.\n", __func__);
  1142. }
  1143. return rval;
  1144. }
  1145. static void
  1146. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
  1147. {
  1148. struct qla_hw_data *ha = vha->hw;
  1149. fc_port_t *fcport;
  1150. vha->flags.online = 0;
  1151. ha->mr.fw_hbt_en = 0;
  1152. if (!critemp) {
  1153. ha->flags.chip_reset_done = 0;
  1154. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1155. vha->qla_stats.total_isp_aborts++;
  1156. ql_log(ql_log_info, vha, 0x013f,
  1157. "Performing ISP error recovery - ha = %p.\n", ha);
  1158. ha->isp_ops->reset_chip(vha);
  1159. }
  1160. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1161. atomic_set(&vha->loop_state, LOOP_DOWN);
  1162. atomic_set(&vha->loop_down_timer,
  1163. QLAFX00_LOOP_DOWN_TIME);
  1164. } else {
  1165. if (!atomic_read(&vha->loop_down_timer))
  1166. atomic_set(&vha->loop_down_timer,
  1167. QLAFX00_LOOP_DOWN_TIME);
  1168. }
  1169. /* Clear all async request states across all VPs. */
  1170. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1171. fcport->flags = 0;
  1172. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1173. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1174. }
  1175. if (!ha->flags.eeh_busy) {
  1176. if (critemp) {
  1177. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  1178. } else {
  1179. /* Requeue all commands in outstanding command list. */
  1180. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1181. }
  1182. }
  1183. qla2x00_free_irqs(vha);
  1184. if (critemp)
  1185. set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
  1186. else
  1187. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1188. /* Clear the Interrupts */
  1189. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1190. ql_log(ql_log_info, vha, 0x0140,
  1191. "%s Done done - ha=%p.\n", __func__, ha);
  1192. }
  1193. /**
  1194. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1195. * @ha: HA context
  1196. *
  1197. * Beginning of request ring has initialization control block already built
  1198. * by nvram config routine.
  1199. *
  1200. * Returns 0 on success.
  1201. */
  1202. void
  1203. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1204. {
  1205. uint16_t cnt;
  1206. response_t *pkt;
  1207. rsp->ring_ptr = rsp->ring;
  1208. rsp->ring_index = 0;
  1209. rsp->status_srb = NULL;
  1210. pkt = rsp->ring_ptr;
  1211. for (cnt = 0; cnt < rsp->length; cnt++) {
  1212. pkt->signature = RESPONSE_PROCESSED;
  1213. WRT_REG_DWORD((void __iomem *)&pkt->signature,
  1214. RESPONSE_PROCESSED);
  1215. pkt++;
  1216. }
  1217. }
  1218. int
  1219. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1220. {
  1221. uint32_t status = QLA_FUNCTION_FAILED;
  1222. struct qla_hw_data *ha = vha->hw;
  1223. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1224. uint32_t aenmbx7;
  1225. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1226. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1227. ha->mbx_intr_code = MSW(aenmbx7);
  1228. ha->rqstq_intr_code = LSW(aenmbx7);
  1229. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1230. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1231. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1232. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1233. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1234. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1235. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1236. ha->mbx_intr_code, ha->rqstq_intr_code,
  1237. ha->req_que_off, ha->rsp_que_len);
  1238. /* Clear the Interrupts */
  1239. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1240. status = qla2x00_init_rings(vha);
  1241. if (!status) {
  1242. vha->flags.online = 1;
  1243. /* if no cable then assume it's good */
  1244. if ((vha->device_flags & DFLG_NO_CABLE))
  1245. status = 0;
  1246. /* Register system information */
  1247. if (qlafx00_fx_disc(vha,
  1248. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1249. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1250. "failed to register host info\n");
  1251. }
  1252. scsi_unblock_requests(vha->host);
  1253. return status;
  1254. }
  1255. void
  1256. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1257. {
  1258. struct qla_hw_data *ha = vha->hw;
  1259. uint32_t fw_heart_beat;
  1260. uint32_t aenmbx0;
  1261. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1262. uint32_t tempc;
  1263. /* Check firmware health */
  1264. if (ha->mr.fw_hbt_cnt)
  1265. ha->mr.fw_hbt_cnt--;
  1266. else {
  1267. if ((!ha->flags.mr_reset_hdlr_active) &&
  1268. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1269. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1270. (ha->mr.fw_hbt_en)) {
  1271. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1272. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1273. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1274. ha->mr.fw_hbt_miss_cnt = 0;
  1275. } else {
  1276. ha->mr.fw_hbt_miss_cnt++;
  1277. if (ha->mr.fw_hbt_miss_cnt ==
  1278. QLAFX00_HEARTBEAT_MISS_CNT) {
  1279. set_bit(ISP_ABORT_NEEDED,
  1280. &vha->dpc_flags);
  1281. qla2xxx_wake_dpc(vha);
  1282. ha->mr.fw_hbt_miss_cnt = 0;
  1283. }
  1284. }
  1285. }
  1286. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1287. }
  1288. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1289. /* Reset recovery to be performed in timer routine */
  1290. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1291. if (ha->mr.fw_reset_timer_exp) {
  1292. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1293. qla2xxx_wake_dpc(vha);
  1294. ha->mr.fw_reset_timer_exp = 0;
  1295. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1296. /* Wake up DPC to rescan the targets */
  1297. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1298. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1299. qla2xxx_wake_dpc(vha);
  1300. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1301. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1302. (!ha->mr.fw_hbt_en)) {
  1303. ha->mr.fw_hbt_en = 1;
  1304. } else if (!ha->mr.fw_reset_timer_tick) {
  1305. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1306. ha->mr.fw_reset_timer_exp = 1;
  1307. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1308. } else if (aenmbx0 == 0xFFFFFFFF) {
  1309. uint32_t data0, data1;
  1310. data0 = QLAFX00_RD_REG(ha,
  1311. QLAFX00_BAR1_BASE_ADDR_REG);
  1312. data1 = QLAFX00_RD_REG(ha,
  1313. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1314. data0 &= 0xffff0000;
  1315. data1 &= 0x0000ffff;
  1316. QLAFX00_WR_REG(ha,
  1317. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1318. (data0 | data1));
  1319. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1320. ha->mr.fw_reset_timer_tick =
  1321. QLAFX00_MAX_RESET_INTERVAL;
  1322. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1323. ha->mr.fw_reset_timer_tick =
  1324. QLAFX00_MAX_RESET_INTERVAL;
  1325. }
  1326. if (ha->mr.old_aenmbx0_state != aenmbx0) {
  1327. ha->mr.old_aenmbx0_state = aenmbx0;
  1328. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1329. }
  1330. ha->mr.fw_reset_timer_tick--;
  1331. }
  1332. if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
  1333. /*
  1334. * Critical temperature recovery to be
  1335. * performed in timer routine
  1336. */
  1337. if (ha->mr.fw_critemp_timer_tick == 0) {
  1338. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1339. ql_dbg(ql_dbg_timer, vha, 0x6012,
  1340. "ISPFx00(%s): Critical temp timer, "
  1341. "current SOC temperature: %d\n",
  1342. __func__, tempc);
  1343. if (tempc < ha->mr.critical_temperature) {
  1344. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1345. clear_bit(FX00_CRITEMP_RECOVERY,
  1346. &vha->dpc_flags);
  1347. qla2xxx_wake_dpc(vha);
  1348. }
  1349. ha->mr.fw_critemp_timer_tick =
  1350. QLAFX00_CRITEMP_INTERVAL;
  1351. } else {
  1352. ha->mr.fw_critemp_timer_tick--;
  1353. }
  1354. }
  1355. if (ha->mr.host_info_resend) {
  1356. /*
  1357. * Incomplete host info might be sent to firmware
  1358. * durinng system boot - info should be resend
  1359. */
  1360. if (ha->mr.hinfo_resend_timer_tick == 0) {
  1361. ha->mr.host_info_resend = false;
  1362. set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
  1363. ha->mr.hinfo_resend_timer_tick =
  1364. QLAFX00_HINFO_RESEND_INTERVAL;
  1365. qla2xxx_wake_dpc(vha);
  1366. } else {
  1367. ha->mr.hinfo_resend_timer_tick--;
  1368. }
  1369. }
  1370. }
  1371. /*
  1372. * qlfx00a_reset_initialize
  1373. * Re-initialize after a iSA device reset.
  1374. *
  1375. * Input:
  1376. * ha = adapter block pointer.
  1377. *
  1378. * Returns:
  1379. * 0 = success
  1380. */
  1381. int
  1382. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1383. {
  1384. struct qla_hw_data *ha = vha->hw;
  1385. if (vha->device_flags & DFLG_DEV_FAILED) {
  1386. ql_dbg(ql_dbg_init, vha, 0x0142,
  1387. "Device in failed state\n");
  1388. return QLA_SUCCESS;
  1389. }
  1390. ha->flags.mr_reset_hdlr_active = 1;
  1391. if (vha->flags.online) {
  1392. scsi_block_requests(vha->host);
  1393. qlafx00_abort_isp_cleanup(vha, false);
  1394. }
  1395. ql_log(ql_log_info, vha, 0x0143,
  1396. "(%s): succeeded.\n", __func__);
  1397. ha->flags.mr_reset_hdlr_active = 0;
  1398. return QLA_SUCCESS;
  1399. }
  1400. /*
  1401. * qlafx00_abort_isp
  1402. * Resets ISP and aborts all outstanding commands.
  1403. *
  1404. * Input:
  1405. * ha = adapter block pointer.
  1406. *
  1407. * Returns:
  1408. * 0 = success
  1409. */
  1410. int
  1411. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1412. {
  1413. struct qla_hw_data *ha = vha->hw;
  1414. if (vha->flags.online) {
  1415. if (unlikely(pci_channel_offline(ha->pdev) &&
  1416. ha->flags.pci_channel_io_perm_failure)) {
  1417. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1418. return QLA_SUCCESS;
  1419. }
  1420. scsi_block_requests(vha->host);
  1421. qlafx00_abort_isp_cleanup(vha, false);
  1422. } else {
  1423. scsi_block_requests(vha->host);
  1424. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1425. vha->qla_stats.total_isp_aborts++;
  1426. ha->isp_ops->reset_chip(vha);
  1427. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1428. /* Clear the Interrupts */
  1429. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1430. }
  1431. ql_log(ql_log_info, vha, 0x0145,
  1432. "(%s): succeeded.\n", __func__);
  1433. return QLA_SUCCESS;
  1434. }
  1435. static inline fc_port_t*
  1436. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1437. {
  1438. fc_port_t *fcport;
  1439. /* Check for matching device in remote port list. */
  1440. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1441. if (fcport->tgt_id == tgt_id) {
  1442. ql_dbg(ql_dbg_async, vha, 0x5072,
  1443. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1444. "and Remote TGT_ID: 0x%x\n",
  1445. fcport, fcport->tgt_id, tgt_id);
  1446. return fcport;
  1447. }
  1448. }
  1449. return NULL;
  1450. }
  1451. static void
  1452. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1453. {
  1454. fc_port_t *fcport;
  1455. ql_log(ql_log_info, vha, 0x5073,
  1456. "Detach TGT-ID: 0x%x\n", tgt_id);
  1457. fcport = qlafx00_get_fcport(vha, tgt_id);
  1458. if (!fcport)
  1459. return;
  1460. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1461. return;
  1462. }
  1463. int
  1464. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1465. {
  1466. int rval = 0;
  1467. uint32_t aen_code, aen_data;
  1468. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1469. aen_data = evt->u.aenfx.evtcode;
  1470. switch (evt->u.aenfx.evtcode) {
  1471. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1472. if (evt->u.aenfx.mbx[1] == 0) {
  1473. if (evt->u.aenfx.mbx[2] == 1) {
  1474. if (!vha->flags.fw_tgt_reported)
  1475. vha->flags.fw_tgt_reported = 1;
  1476. atomic_set(&vha->loop_down_timer, 0);
  1477. atomic_set(&vha->loop_state, LOOP_UP);
  1478. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1479. qla2xxx_wake_dpc(vha);
  1480. } else if (evt->u.aenfx.mbx[2] == 2) {
  1481. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1482. }
  1483. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1484. if (evt->u.aenfx.mbx[2] == 1) {
  1485. if (!vha->flags.fw_tgt_reported)
  1486. vha->flags.fw_tgt_reported = 1;
  1487. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1488. } else if (evt->u.aenfx.mbx[2] == 2) {
  1489. vha->device_flags |= DFLG_NO_CABLE;
  1490. qla2x00_mark_all_devices_lost(vha, 1);
  1491. }
  1492. }
  1493. break;
  1494. case QLAFX00_MBA_LINK_UP:
  1495. aen_code = FCH_EVT_LINKUP;
  1496. aen_data = 0;
  1497. break;
  1498. case QLAFX00_MBA_LINK_DOWN:
  1499. aen_code = FCH_EVT_LINKDOWN;
  1500. aen_data = 0;
  1501. break;
  1502. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  1503. ql_log(ql_log_info, vha, 0x5082,
  1504. "Process critical temperature event "
  1505. "aenmb[0]: %x\n",
  1506. evt->u.aenfx.evtcode);
  1507. scsi_block_requests(vha->host);
  1508. qlafx00_abort_isp_cleanup(vha, true);
  1509. scsi_unblock_requests(vha->host);
  1510. break;
  1511. }
  1512. fc_host_post_event(vha->host, fc_get_event_number(),
  1513. aen_code, aen_data);
  1514. return rval;
  1515. }
  1516. static void
  1517. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1518. {
  1519. u64 port_name = 0, node_name = 0;
  1520. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1521. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1522. fc_host_node_name(vha->host) = node_name;
  1523. fc_host_port_name(vha->host) = port_name;
  1524. if (!pinfo->port_type)
  1525. vha->hw->current_topology = ISP_CFG_F;
  1526. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1527. atomic_set(&vha->loop_state, LOOP_READY);
  1528. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1529. atomic_set(&vha->loop_state, LOOP_DOWN);
  1530. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1531. }
  1532. static void
  1533. qla2x00_fxdisc_iocb_timeout(void *data)
  1534. {
  1535. srb_t *sp = (srb_t *)data;
  1536. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1537. complete(&lio->u.fxiocb.fxiocb_comp);
  1538. }
  1539. static void
  1540. qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
  1541. {
  1542. srb_t *sp = (srb_t *)ptr;
  1543. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1544. complete(&lio->u.fxiocb.fxiocb_comp);
  1545. }
  1546. int
  1547. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1548. {
  1549. srb_t *sp;
  1550. struct srb_iocb *fdisc;
  1551. int rval = QLA_FUNCTION_FAILED;
  1552. struct qla_hw_data *ha = vha->hw;
  1553. struct host_system_info *phost_info;
  1554. struct register_host_info *preg_hsi;
  1555. struct new_utsname *p_sysid = NULL;
  1556. struct timeval tv;
  1557. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1558. if (!sp)
  1559. goto done;
  1560. fdisc = &sp->u.iocb_cmd;
  1561. switch (fx_type) {
  1562. case FXDISC_GET_CONFIG_INFO:
  1563. fdisc->u.fxiocb.flags =
  1564. SRB_FXDISC_RESP_DMA_VALID;
  1565. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1566. break;
  1567. case FXDISC_GET_PORT_INFO:
  1568. fdisc->u.fxiocb.flags =
  1569. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1570. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1571. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1572. break;
  1573. case FXDISC_GET_TGT_NODE_INFO:
  1574. fdisc->u.fxiocb.flags =
  1575. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1576. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1577. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1578. break;
  1579. case FXDISC_GET_TGT_NODE_LIST:
  1580. fdisc->u.fxiocb.flags =
  1581. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1582. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1583. break;
  1584. case FXDISC_REG_HOST_INFO:
  1585. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1586. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1587. p_sysid = utsname();
  1588. if (!p_sysid) {
  1589. ql_log(ql_log_warn, vha, 0x303c,
  1590. "Not able to get the system information\n");
  1591. goto done_free_sp;
  1592. }
  1593. break;
  1594. case FXDISC_ABORT_IOCTL:
  1595. default:
  1596. break;
  1597. }
  1598. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1599. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1600. fdisc->u.fxiocb.req_len,
  1601. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1602. if (!fdisc->u.fxiocb.req_addr)
  1603. goto done_free_sp;
  1604. if (fx_type == FXDISC_REG_HOST_INFO) {
  1605. preg_hsi = (struct register_host_info *)
  1606. fdisc->u.fxiocb.req_addr;
  1607. phost_info = &preg_hsi->hsi;
  1608. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1609. phost_info->os_type = OS_TYPE_LINUX;
  1610. strncpy(phost_info->sysname,
  1611. p_sysid->sysname, SYSNAME_LENGTH);
  1612. strncpy(phost_info->nodename,
  1613. p_sysid->nodename, NODENAME_LENGTH);
  1614. if (!strcmp(phost_info->nodename, "(none)"))
  1615. ha->mr.host_info_resend = true;
  1616. strncpy(phost_info->release,
  1617. p_sysid->release, RELEASE_LENGTH);
  1618. strncpy(phost_info->version,
  1619. p_sysid->version, VERSION_LENGTH);
  1620. strncpy(phost_info->machine,
  1621. p_sysid->machine, MACHINE_LENGTH);
  1622. strncpy(phost_info->domainname,
  1623. p_sysid->domainname, DOMNAME_LENGTH);
  1624. strncpy(phost_info->hostdriver,
  1625. QLA2XXX_VERSION, VERSION_LENGTH);
  1626. do_gettimeofday(&tv);
  1627. preg_hsi->utc = (uint64_t)tv.tv_sec;
  1628. ql_dbg(ql_dbg_init, vha, 0x0149,
  1629. "ISP%04X: Host registration with firmware\n",
  1630. ha->pdev->device);
  1631. ql_dbg(ql_dbg_init, vha, 0x014a,
  1632. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1633. phost_info->os_type,
  1634. phost_info->sysname,
  1635. phost_info->nodename);
  1636. ql_dbg(ql_dbg_init, vha, 0x014b,
  1637. "release = '%s', version = '%s'\n",
  1638. phost_info->release,
  1639. phost_info->version);
  1640. ql_dbg(ql_dbg_init, vha, 0x014c,
  1641. "machine = '%s' "
  1642. "domainname = '%s', hostdriver = '%s'\n",
  1643. phost_info->machine,
  1644. phost_info->domainname,
  1645. phost_info->hostdriver);
  1646. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1647. (uint8_t *)phost_info,
  1648. sizeof(struct host_system_info));
  1649. }
  1650. }
  1651. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1652. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1653. fdisc->u.fxiocb.rsp_len,
  1654. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1655. if (!fdisc->u.fxiocb.rsp_addr)
  1656. goto done_unmap_req;
  1657. }
  1658. sp->type = SRB_FXIOCB_DCMD;
  1659. sp->name = "fxdisc";
  1660. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1661. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1662. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1663. sp->done = qla2x00_fxdisc_sp_done;
  1664. rval = qla2x00_start_sp(sp);
  1665. if (rval != QLA_SUCCESS)
  1666. goto done_unmap_dma;
  1667. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1668. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1669. struct config_info_data *pinfo =
  1670. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1671. strcpy(vha->hw->model_number, pinfo->model_num);
  1672. strcpy(vha->hw->model_desc, pinfo->model_description);
  1673. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1674. sizeof(vha->hw->mr.symbolic_name));
  1675. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1676. sizeof(vha->hw->mr.serial_num));
  1677. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1678. sizeof(vha->hw->mr.hw_version));
  1679. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1680. sizeof(vha->hw->mr.fw_version));
  1681. strim(vha->hw->mr.fw_version);
  1682. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1683. sizeof(vha->hw->mr.uboot_version));
  1684. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1685. sizeof(vha->hw->mr.fru_serial_num));
  1686. vha->hw->mr.critical_temperature =
  1687. (pinfo->nominal_temp_value) ?
  1688. pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
  1689. ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
  1690. QLAFX00_EXTENDED_IO_EN_MASK) != 0;
  1691. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1692. struct port_info_data *pinfo =
  1693. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1694. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1695. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1696. vha->d_id.b.domain = pinfo->port_id[0];
  1697. vha->d_id.b.area = pinfo->port_id[1];
  1698. vha->d_id.b.al_pa = pinfo->port_id[2];
  1699. qlafx00_update_host_attr(vha, pinfo);
  1700. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1701. (uint8_t *)pinfo, 16);
  1702. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1703. struct qlafx00_tgt_node_info *pinfo =
  1704. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1705. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1706. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1707. fcport->port_type = FCT_TARGET;
  1708. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1709. (uint8_t *)pinfo, 16);
  1710. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1711. struct qlafx00_tgt_node_info *pinfo =
  1712. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1713. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1714. (uint8_t *)pinfo, 16);
  1715. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1716. } else if (fx_type == FXDISC_ABORT_IOCTL)
  1717. fdisc->u.fxiocb.result =
  1718. (fdisc->u.fxiocb.result ==
  1719. cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
  1720. cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
  1721. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1722. done_unmap_dma:
  1723. if (fdisc->u.fxiocb.rsp_addr)
  1724. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1725. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1726. done_unmap_req:
  1727. if (fdisc->u.fxiocb.req_addr)
  1728. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1729. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1730. done_free_sp:
  1731. sp->free(vha, sp);
  1732. done:
  1733. return rval;
  1734. }
  1735. /*
  1736. * qlafx00_initialize_adapter
  1737. * Initialize board.
  1738. *
  1739. * Input:
  1740. * ha = adapter block pointer.
  1741. *
  1742. * Returns:
  1743. * 0 = success
  1744. */
  1745. int
  1746. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1747. {
  1748. int rval;
  1749. struct qla_hw_data *ha = vha->hw;
  1750. uint32_t tempc;
  1751. /* Clear adapter flags. */
  1752. vha->flags.online = 0;
  1753. ha->flags.chip_reset_done = 0;
  1754. vha->flags.reset_active = 0;
  1755. ha->flags.pci_channel_io_perm_failure = 0;
  1756. ha->flags.eeh_busy = 0;
  1757. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1758. atomic_set(&vha->loop_state, LOOP_DOWN);
  1759. vha->device_flags = DFLG_NO_CABLE;
  1760. vha->dpc_flags = 0;
  1761. vha->flags.management_server_logged_in = 0;
  1762. ha->isp_abort_cnt = 0;
  1763. ha->beacon_blink_led = 0;
  1764. set_bit(0, ha->req_qid_map);
  1765. set_bit(0, ha->rsp_qid_map);
  1766. ql_dbg(ql_dbg_init, vha, 0x0147,
  1767. "Configuring PCI space...\n");
  1768. rval = ha->isp_ops->pci_config(vha);
  1769. if (rval) {
  1770. ql_log(ql_log_warn, vha, 0x0148,
  1771. "Unable to configure PCI space.\n");
  1772. return rval;
  1773. }
  1774. rval = qlafx00_init_fw_ready(vha);
  1775. if (rval != QLA_SUCCESS)
  1776. return rval;
  1777. qlafx00_save_queue_ptrs(vha);
  1778. rval = qlafx00_config_queues(vha);
  1779. if (rval != QLA_SUCCESS)
  1780. return rval;
  1781. /*
  1782. * Allocate the array of outstanding commands
  1783. * now that we know the firmware resources.
  1784. */
  1785. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1786. if (rval != QLA_SUCCESS)
  1787. return rval;
  1788. rval = qla2x00_init_rings(vha);
  1789. ha->flags.chip_reset_done = 1;
  1790. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1791. ql_dbg(ql_dbg_init, vha, 0x0152,
  1792. "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
  1793. __func__, tempc);
  1794. return rval;
  1795. }
  1796. uint32_t
  1797. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1798. char *buf)
  1799. {
  1800. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1801. int rval = QLA_FUNCTION_FAILED;
  1802. uint32_t state[1];
  1803. if (qla2x00_reset_active(vha))
  1804. ql_log(ql_log_warn, vha, 0x70ce,
  1805. "ISP reset active.\n");
  1806. else if (!vha->hw->flags.eeh_busy) {
  1807. rval = qlafx00_get_firmware_state(vha, state);
  1808. }
  1809. if (rval != QLA_SUCCESS)
  1810. memset(state, -1, sizeof(state));
  1811. return state[0];
  1812. }
  1813. void
  1814. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1815. {
  1816. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1817. (shost_priv(shost)))->hw;
  1818. u32 speed = FC_PORTSPEED_UNKNOWN;
  1819. switch (ha->link_data_rate) {
  1820. case QLAFX00_PORT_SPEED_2G:
  1821. speed = FC_PORTSPEED_2GBIT;
  1822. break;
  1823. case QLAFX00_PORT_SPEED_4G:
  1824. speed = FC_PORTSPEED_4GBIT;
  1825. break;
  1826. case QLAFX00_PORT_SPEED_8G:
  1827. speed = FC_PORTSPEED_8GBIT;
  1828. break;
  1829. case QLAFX00_PORT_SPEED_10G:
  1830. speed = FC_PORTSPEED_10GBIT;
  1831. break;
  1832. }
  1833. fc_host_speed(shost) = speed;
  1834. }
  1835. /** QLAFX00 specific ISR implementation functions */
  1836. static inline void
  1837. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1838. uint32_t sense_len, struct rsp_que *rsp, int res)
  1839. {
  1840. struct scsi_qla_host *vha = sp->fcport->vha;
  1841. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1842. uint32_t track_sense_len;
  1843. SET_FW_SENSE_LEN(sp, sense_len);
  1844. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1845. sense_len = SCSI_SENSE_BUFFERSIZE;
  1846. SET_CMD_SENSE_LEN(sp, sense_len);
  1847. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1848. track_sense_len = sense_len;
  1849. if (sense_len > par_sense_len)
  1850. sense_len = par_sense_len;
  1851. memcpy(cp->sense_buffer, sense_data, sense_len);
  1852. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1853. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1854. track_sense_len -= sense_len;
  1855. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1856. ql_dbg(ql_dbg_io, vha, 0x304d,
  1857. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1858. sense_len, par_sense_len, track_sense_len);
  1859. if (GET_FW_SENSE_LEN(sp) > 0) {
  1860. rsp->status_srb = sp;
  1861. cp->result = res;
  1862. }
  1863. if (sense_len) {
  1864. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1865. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1866. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1867. cp);
  1868. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1869. cp->sense_buffer, sense_len);
  1870. }
  1871. }
  1872. static void
  1873. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1874. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1875. __le16 sstatus, __le16 cpstatus)
  1876. {
  1877. struct srb_iocb *tmf;
  1878. tmf = &sp->u.iocb_cmd;
  1879. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1880. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1881. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1882. tmf->u.tmf.comp_status = cpstatus;
  1883. sp->done(vha, sp, 0);
  1884. }
  1885. static void
  1886. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1887. struct abort_iocb_entry_fx00 *pkt)
  1888. {
  1889. const char func[] = "ABT_IOCB";
  1890. srb_t *sp;
  1891. struct srb_iocb *abt;
  1892. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1893. if (!sp)
  1894. return;
  1895. abt = &sp->u.iocb_cmd;
  1896. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1897. sp->done(vha, sp, 0);
  1898. }
  1899. static void
  1900. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1901. struct ioctl_iocb_entry_fx00 *pkt)
  1902. {
  1903. const char func[] = "IOSB_IOCB";
  1904. srb_t *sp;
  1905. struct fc_bsg_job *bsg_job;
  1906. struct srb_iocb *iocb_job;
  1907. int res;
  1908. struct qla_mt_iocb_rsp_fx00 fstatus;
  1909. uint8_t *fw_sts_ptr;
  1910. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1911. if (!sp)
  1912. return;
  1913. if (sp->type == SRB_FXIOCB_DCMD) {
  1914. iocb_job = &sp->u.iocb_cmd;
  1915. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1916. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1917. iocb_job->u.fxiocb.result = pkt->status;
  1918. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1919. iocb_job->u.fxiocb.req_data =
  1920. pkt->dataword_r;
  1921. } else {
  1922. bsg_job = sp->u.bsg_job;
  1923. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1924. fstatus.reserved_1 = pkt->reserved_0;
  1925. fstatus.func_type = pkt->comp_func_num;
  1926. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1927. fstatus.ioctl_data = pkt->dataword_r;
  1928. fstatus.adapid = pkt->adapid;
  1929. fstatus.reserved_2 = pkt->dataword_r_extra;
  1930. fstatus.res_count = pkt->residuallen;
  1931. fstatus.status = pkt->status;
  1932. fstatus.seq_number = pkt->seq_no;
  1933. memcpy(fstatus.reserved_3,
  1934. pkt->reserved_2, 20 * sizeof(uint8_t));
  1935. fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
  1936. sizeof(struct fc_bsg_reply);
  1937. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  1938. sizeof(struct qla_mt_iocb_rsp_fx00));
  1939. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  1940. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  1941. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1942. sp->fcport->vha, 0x5080,
  1943. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  1944. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1945. sp->fcport->vha, 0x5074,
  1946. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  1947. res = bsg_job->reply->result = DID_OK << 16;
  1948. bsg_job->reply->reply_payload_rcv_len =
  1949. bsg_job->reply_payload.payload_len;
  1950. }
  1951. sp->done(vha, sp, res);
  1952. }
  1953. /**
  1954. * qlafx00_status_entry() - Process a Status IOCB entry.
  1955. * @ha: SCSI driver HA context
  1956. * @pkt: Entry pointer
  1957. */
  1958. static void
  1959. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1960. {
  1961. srb_t *sp;
  1962. fc_port_t *fcport;
  1963. struct scsi_cmnd *cp;
  1964. struct sts_entry_fx00 *sts;
  1965. __le16 comp_status;
  1966. __le16 scsi_status;
  1967. uint16_t ox_id;
  1968. __le16 lscsi_status;
  1969. int32_t resid;
  1970. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1971. fw_resid_len;
  1972. uint8_t *rsp_info = NULL, *sense_data = NULL;
  1973. struct qla_hw_data *ha = vha->hw;
  1974. uint32_t hindex, handle;
  1975. uint16_t que;
  1976. struct req_que *req;
  1977. int logit = 1;
  1978. int res = 0;
  1979. sts = (struct sts_entry_fx00 *) pkt;
  1980. comp_status = sts->comp_status;
  1981. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  1982. hindex = sts->handle;
  1983. handle = LSW(hindex);
  1984. que = MSW(hindex);
  1985. req = ha->req_q_map[que];
  1986. /* Validate handle. */
  1987. if (handle < req->num_outstanding_cmds)
  1988. sp = req->outstanding_cmds[handle];
  1989. else
  1990. sp = NULL;
  1991. if (sp == NULL) {
  1992. ql_dbg(ql_dbg_io, vha, 0x3034,
  1993. "Invalid status handle (0x%x).\n", handle);
  1994. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1995. qla2xxx_wake_dpc(vha);
  1996. return;
  1997. }
  1998. if (sp->type == SRB_TM_CMD) {
  1999. req->outstanding_cmds[handle] = NULL;
  2000. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  2001. scsi_status, comp_status);
  2002. return;
  2003. }
  2004. /* Fast path completion. */
  2005. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2006. qla2x00_process_completed_request(vha, req, handle);
  2007. return;
  2008. }
  2009. req->outstanding_cmds[handle] = NULL;
  2010. cp = GET_CMD_SP(sp);
  2011. if (cp == NULL) {
  2012. ql_dbg(ql_dbg_io, vha, 0x3048,
  2013. "Command already returned (0x%x/%p).\n",
  2014. handle, sp);
  2015. return;
  2016. }
  2017. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  2018. fcport = sp->fcport;
  2019. ox_id = 0;
  2020. sense_len = par_sense_len = rsp_info_len = resid_len =
  2021. fw_resid_len = 0;
  2022. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  2023. sense_len = sts->sense_len;
  2024. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2025. | (uint16_t)SS_RESIDUAL_OVER)))
  2026. resid_len = le32_to_cpu(sts->residual_len);
  2027. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2028. fw_resid_len = le32_to_cpu(sts->residual_len);
  2029. rsp_info = sense_data = sts->data;
  2030. par_sense_len = sizeof(sts->data);
  2031. /* Check for overrun. */
  2032. if (comp_status == CS_COMPLETE &&
  2033. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2034. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2035. /*
  2036. * Based on Host and scsi status generate status code for Linux
  2037. */
  2038. switch (le16_to_cpu(comp_status)) {
  2039. case CS_COMPLETE:
  2040. case CS_QUEUE_FULL:
  2041. if (scsi_status == 0) {
  2042. res = DID_OK << 16;
  2043. break;
  2044. }
  2045. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2046. | (uint16_t)SS_RESIDUAL_OVER))) {
  2047. resid = resid_len;
  2048. scsi_set_resid(cp, resid);
  2049. if (!lscsi_status &&
  2050. ((unsigned)(scsi_bufflen(cp) - resid) <
  2051. cp->underflow)) {
  2052. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2053. "Mid-layer underflow "
  2054. "detected (0x%x of 0x%x bytes).\n",
  2055. resid, scsi_bufflen(cp));
  2056. res = DID_ERROR << 16;
  2057. break;
  2058. }
  2059. }
  2060. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2061. if (lscsi_status ==
  2062. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2063. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2064. "QUEUE FULL detected.\n");
  2065. break;
  2066. }
  2067. logit = 0;
  2068. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2069. break;
  2070. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2071. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2072. break;
  2073. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2074. rsp, res);
  2075. break;
  2076. case CS_DATA_UNDERRUN:
  2077. /* Use F/W calculated residual length. */
  2078. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2079. resid = fw_resid_len;
  2080. else
  2081. resid = resid_len;
  2082. scsi_set_resid(cp, resid);
  2083. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2084. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2085. && fw_resid_len != resid_len) {
  2086. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2087. "Dropped frame(s) detected "
  2088. "(0x%x of 0x%x bytes).\n",
  2089. resid, scsi_bufflen(cp));
  2090. res = DID_ERROR << 16 |
  2091. le16_to_cpu(lscsi_status);
  2092. goto check_scsi_status;
  2093. }
  2094. if (!lscsi_status &&
  2095. ((unsigned)(scsi_bufflen(cp) - resid) <
  2096. cp->underflow)) {
  2097. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2098. "Mid-layer underflow "
  2099. "detected (0x%x of 0x%x bytes, "
  2100. "cp->underflow: 0x%x).\n",
  2101. resid, scsi_bufflen(cp), cp->underflow);
  2102. res = DID_ERROR << 16;
  2103. break;
  2104. }
  2105. } else if (lscsi_status !=
  2106. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2107. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2108. /*
  2109. * scsi status of task set and busy are considered
  2110. * to be task not completed.
  2111. */
  2112. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2113. "Dropped frame(s) detected (0x%x "
  2114. "of 0x%x bytes).\n", resid,
  2115. scsi_bufflen(cp));
  2116. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2117. goto check_scsi_status;
  2118. } else {
  2119. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2120. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2121. scsi_status, lscsi_status);
  2122. }
  2123. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2124. logit = 0;
  2125. check_scsi_status:
  2126. /*
  2127. * Check to see if SCSI Status is non zero. If so report SCSI
  2128. * Status.
  2129. */
  2130. if (lscsi_status != 0) {
  2131. if (lscsi_status ==
  2132. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2133. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2134. "QUEUE FULL detected.\n");
  2135. logit = 1;
  2136. break;
  2137. }
  2138. if (lscsi_status !=
  2139. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2140. break;
  2141. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2142. if (!(scsi_status &
  2143. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2144. break;
  2145. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2146. sense_len, rsp, res);
  2147. }
  2148. break;
  2149. case CS_PORT_LOGGED_OUT:
  2150. case CS_PORT_CONFIG_CHG:
  2151. case CS_PORT_BUSY:
  2152. case CS_INCOMPLETE:
  2153. case CS_PORT_UNAVAILABLE:
  2154. case CS_TIMEOUT:
  2155. case CS_RESET:
  2156. /*
  2157. * We are going to have the fc class block the rport
  2158. * while we try to recover so instruct the mid layer
  2159. * to requeue until the class decides how to handle this.
  2160. */
  2161. res = DID_TRANSPORT_DISRUPTED << 16;
  2162. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2163. "Port down status: port-state=0x%x.\n",
  2164. atomic_read(&fcport->state));
  2165. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2166. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2167. break;
  2168. case CS_ABORTED:
  2169. res = DID_RESET << 16;
  2170. break;
  2171. default:
  2172. res = DID_ERROR << 16;
  2173. break;
  2174. }
  2175. if (logit)
  2176. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2177. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2178. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2179. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2180. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2181. comp_status, scsi_status, res, vha->host_no,
  2182. cp->device->id, cp->device->lun, fcport->tgt_id,
  2183. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2184. rsp_info_len, resid_len, fw_resid_len, sense_len,
  2185. par_sense_len, rsp_info_len);
  2186. if (rsp->status_srb == NULL)
  2187. sp->done(ha, sp, res);
  2188. }
  2189. /**
  2190. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2191. * @ha: SCSI driver HA context
  2192. * @pkt: Entry pointer
  2193. *
  2194. * Extended sense data.
  2195. */
  2196. static void
  2197. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2198. {
  2199. uint8_t sense_sz = 0;
  2200. struct qla_hw_data *ha = rsp->hw;
  2201. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2202. srb_t *sp = rsp->status_srb;
  2203. struct scsi_cmnd *cp;
  2204. uint32_t sense_len;
  2205. uint8_t *sense_ptr;
  2206. if (!sp) {
  2207. ql_dbg(ql_dbg_io, vha, 0x3037,
  2208. "no SP, sp = %p\n", sp);
  2209. return;
  2210. }
  2211. if (!GET_FW_SENSE_LEN(sp)) {
  2212. ql_dbg(ql_dbg_io, vha, 0x304b,
  2213. "no fw sense data, sp = %p\n", sp);
  2214. return;
  2215. }
  2216. cp = GET_CMD_SP(sp);
  2217. if (cp == NULL) {
  2218. ql_log(ql_log_warn, vha, 0x303b,
  2219. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2220. rsp->status_srb = NULL;
  2221. return;
  2222. }
  2223. if (!GET_CMD_SENSE_LEN(sp)) {
  2224. ql_dbg(ql_dbg_io, vha, 0x304c,
  2225. "no sense data, sp = %p\n", sp);
  2226. } else {
  2227. sense_len = GET_CMD_SENSE_LEN(sp);
  2228. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2229. ql_dbg(ql_dbg_io, vha, 0x304f,
  2230. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2231. sp, sense_len, sense_ptr);
  2232. if (sense_len > sizeof(pkt->data))
  2233. sense_sz = sizeof(pkt->data);
  2234. else
  2235. sense_sz = sense_len;
  2236. /* Move sense data. */
  2237. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2238. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2239. memcpy(sense_ptr, pkt->data, sense_sz);
  2240. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2241. sense_ptr, sense_sz);
  2242. sense_len -= sense_sz;
  2243. sense_ptr += sense_sz;
  2244. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2245. SET_CMD_SENSE_LEN(sp, sense_len);
  2246. }
  2247. sense_len = GET_FW_SENSE_LEN(sp);
  2248. sense_len = (sense_len > sizeof(pkt->data)) ?
  2249. (sense_len - sizeof(pkt->data)) : 0;
  2250. SET_FW_SENSE_LEN(sp, sense_len);
  2251. /* Place command on done queue. */
  2252. if (sense_len == 0) {
  2253. rsp->status_srb = NULL;
  2254. sp->done(ha, sp, cp->result);
  2255. }
  2256. }
  2257. /**
  2258. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2259. * @ha: SCSI driver HA context
  2260. */
  2261. static void
  2262. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2263. struct rsp_que *rsp, void *pkt)
  2264. {
  2265. srb_t *sp;
  2266. struct multi_sts_entry_fx00 *stsmfx;
  2267. struct qla_hw_data *ha = vha->hw;
  2268. uint32_t handle, hindex, handle_count, i;
  2269. uint16_t que;
  2270. struct req_que *req;
  2271. __le32 *handle_ptr;
  2272. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2273. handle_count = stsmfx->handle_count;
  2274. if (handle_count > MAX_HANDLE_COUNT) {
  2275. ql_dbg(ql_dbg_io, vha, 0x3035,
  2276. "Invalid handle count (0x%x).\n", handle_count);
  2277. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2278. qla2xxx_wake_dpc(vha);
  2279. return;
  2280. }
  2281. handle_ptr = &stsmfx->handles[0];
  2282. for (i = 0; i < handle_count; i++) {
  2283. hindex = le32_to_cpu(*handle_ptr);
  2284. handle = LSW(hindex);
  2285. que = MSW(hindex);
  2286. req = ha->req_q_map[que];
  2287. /* Validate handle. */
  2288. if (handle < req->num_outstanding_cmds)
  2289. sp = req->outstanding_cmds[handle];
  2290. else
  2291. sp = NULL;
  2292. if (sp == NULL) {
  2293. ql_dbg(ql_dbg_io, vha, 0x3044,
  2294. "Invalid status handle (0x%x).\n", handle);
  2295. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2296. qla2xxx_wake_dpc(vha);
  2297. return;
  2298. }
  2299. qla2x00_process_completed_request(vha, req, handle);
  2300. handle_ptr++;
  2301. }
  2302. }
  2303. /**
  2304. * qlafx00_error_entry() - Process an error entry.
  2305. * @ha: SCSI driver HA context
  2306. * @pkt: Entry pointer
  2307. */
  2308. static void
  2309. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2310. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2311. {
  2312. srb_t *sp;
  2313. struct qla_hw_data *ha = vha->hw;
  2314. const char func[] = "ERROR-IOCB";
  2315. uint16_t que = 0;
  2316. struct req_que *req = NULL;
  2317. int res = DID_ERROR << 16;
  2318. ql_dbg(ql_dbg_async, vha, 0x507f,
  2319. "type of error status in response: 0x%x\n", estatus);
  2320. req = ha->req_q_map[que];
  2321. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2322. if (sp) {
  2323. sp->done(ha, sp, res);
  2324. return;
  2325. }
  2326. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2327. qla2xxx_wake_dpc(vha);
  2328. }
  2329. /**
  2330. * qlafx00_process_response_queue() - Process response queue entries.
  2331. * @ha: SCSI driver HA context
  2332. */
  2333. static void
  2334. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2335. struct rsp_que *rsp)
  2336. {
  2337. struct sts_entry_fx00 *pkt;
  2338. response_t *lptr;
  2339. uint16_t lreq_q_in = 0;
  2340. uint16_t lreq_q_out = 0;
  2341. lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in);
  2342. lreq_q_out = rsp->ring_index;
  2343. while (lreq_q_in != lreq_q_out) {
  2344. lptr = rsp->ring_ptr;
  2345. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2346. sizeof(rsp->rsp_pkt));
  2347. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2348. rsp->ring_index++;
  2349. lreq_q_out++;
  2350. if (rsp->ring_index == rsp->length) {
  2351. lreq_q_out = 0;
  2352. rsp->ring_index = 0;
  2353. rsp->ring_ptr = rsp->ring;
  2354. } else {
  2355. rsp->ring_ptr++;
  2356. }
  2357. if (pkt->entry_status != 0 &&
  2358. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2359. qlafx00_error_entry(vha, rsp,
  2360. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2361. pkt->entry_type);
  2362. continue;
  2363. }
  2364. switch (pkt->entry_type) {
  2365. case STATUS_TYPE_FX00:
  2366. qlafx00_status_entry(vha, rsp, pkt);
  2367. break;
  2368. case STATUS_CONT_TYPE_FX00:
  2369. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2370. break;
  2371. case MULTI_STATUS_TYPE_FX00:
  2372. qlafx00_multistatus_entry(vha, rsp, pkt);
  2373. break;
  2374. case ABORT_IOCB_TYPE_FX00:
  2375. qlafx00_abort_iocb_entry(vha, rsp->req,
  2376. (struct abort_iocb_entry_fx00 *)pkt);
  2377. break;
  2378. case IOCTL_IOSB_TYPE_FX00:
  2379. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2380. (struct ioctl_iocb_entry_fx00 *)pkt);
  2381. break;
  2382. default:
  2383. /* Type Not Supported. */
  2384. ql_dbg(ql_dbg_async, vha, 0x5081,
  2385. "Received unknown response pkt type %x "
  2386. "entry status=%x.\n",
  2387. pkt->entry_type, pkt->entry_status);
  2388. break;
  2389. }
  2390. }
  2391. /* Adjust ring index */
  2392. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2393. }
  2394. /**
  2395. * qlafx00_async_event() - Process aynchronous events.
  2396. * @ha: SCSI driver HA context
  2397. */
  2398. static void
  2399. qlafx00_async_event(scsi_qla_host_t *vha)
  2400. {
  2401. struct qla_hw_data *ha = vha->hw;
  2402. struct device_reg_fx00 __iomem *reg;
  2403. int data_size = 1;
  2404. reg = &ha->iobase->ispfx00;
  2405. /* Setup to process RIO completion. */
  2406. switch (ha->aenmb[0]) {
  2407. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2408. ql_log(ql_log_warn, vha, 0x5079,
  2409. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2410. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2411. break;
  2412. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2413. ql_dbg(ql_dbg_async, vha, 0x5076,
  2414. "Asynchronous FW shutdown requested.\n");
  2415. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2416. qla2xxx_wake_dpc(vha);
  2417. break;
  2418. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2419. ha->aenmb[1] = RD_REG_DWORD(&reg->aenmailbox1);
  2420. ha->aenmb[2] = RD_REG_DWORD(&reg->aenmailbox2);
  2421. ha->aenmb[3] = RD_REG_DWORD(&reg->aenmailbox3);
  2422. ql_dbg(ql_dbg_async, vha, 0x5077,
  2423. "Asynchronous port Update received "
  2424. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2425. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2426. data_size = 4;
  2427. break;
  2428. case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
  2429. ql_log(ql_log_info, vha, 0x5085,
  2430. "Asynchronous over temperature event received "
  2431. "aenmb[0]: %x\n",
  2432. ha->aenmb[0]);
  2433. break;
  2434. case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */
  2435. ql_log(ql_log_info, vha, 0x5086,
  2436. "Asynchronous normal temperature event received "
  2437. "aenmb[0]: %x\n",
  2438. ha->aenmb[0]);
  2439. break;
  2440. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  2441. ql_log(ql_log_info, vha, 0x5083,
  2442. "Asynchronous critical temperature event received "
  2443. "aenmb[0]: %x\n",
  2444. ha->aenmb[0]);
  2445. break;
  2446. default:
  2447. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2448. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2449. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2450. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2451. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2452. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2453. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2454. ql_dbg(ql_dbg_async, vha, 0x5078,
  2455. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2456. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2457. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2458. break;
  2459. }
  2460. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2461. (uint32_t *)ha->aenmb, data_size);
  2462. }
  2463. /**
  2464. *
  2465. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2466. * @ha: SCSI driver HA context
  2467. * @mb16: Mailbox16 register
  2468. */
  2469. static void
  2470. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2471. {
  2472. uint16_t cnt;
  2473. uint32_t __iomem *wptr;
  2474. struct qla_hw_data *ha = vha->hw;
  2475. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2476. if (!ha->mcp32)
  2477. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2478. /* Load return mailbox registers. */
  2479. ha->flags.mbox_int = 1;
  2480. ha->mailbox_out32[0] = mb0;
  2481. wptr = (uint32_t __iomem *)&reg->mailbox17;
  2482. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2483. ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
  2484. wptr++;
  2485. }
  2486. }
  2487. /**
  2488. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2489. * @irq:
  2490. * @dev_id: SCSI driver HA context
  2491. *
  2492. * Called by system whenever the host adapter generates an interrupt.
  2493. *
  2494. * Returns handled flag.
  2495. */
  2496. irqreturn_t
  2497. qlafx00_intr_handler(int irq, void *dev_id)
  2498. {
  2499. scsi_qla_host_t *vha;
  2500. struct qla_hw_data *ha;
  2501. struct device_reg_fx00 __iomem *reg;
  2502. int status;
  2503. unsigned long iter;
  2504. uint32_t stat;
  2505. uint32_t mb[8];
  2506. struct rsp_que *rsp;
  2507. unsigned long flags;
  2508. uint32_t clr_intr = 0;
  2509. uint32_t intr_stat = 0;
  2510. rsp = (struct rsp_que *) dev_id;
  2511. if (!rsp) {
  2512. ql_log(ql_log_info, NULL, 0x507d,
  2513. "%s: NULL response queue pointer.\n", __func__);
  2514. return IRQ_NONE;
  2515. }
  2516. ha = rsp->hw;
  2517. reg = &ha->iobase->ispfx00;
  2518. status = 0;
  2519. if (unlikely(pci_channel_offline(ha->pdev)))
  2520. return IRQ_HANDLED;
  2521. spin_lock_irqsave(&ha->hardware_lock, flags);
  2522. vha = pci_get_drvdata(ha->pdev);
  2523. for (iter = 50; iter--; clr_intr = 0) {
  2524. stat = QLAFX00_RD_INTR_REG(ha);
  2525. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2526. break;
  2527. intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
  2528. if (!intr_stat)
  2529. break;
  2530. if (stat & QLAFX00_INTR_MB_CMPLT) {
  2531. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2532. qlafx00_mbx_completion(vha, mb[0]);
  2533. status |= MBX_INTERRUPT;
  2534. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2535. }
  2536. if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
  2537. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2538. qlafx00_async_event(vha);
  2539. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2540. }
  2541. if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
  2542. qlafx00_process_response_queue(vha, rsp);
  2543. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2544. }
  2545. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2546. QLAFX00_RD_INTR_REG(ha);
  2547. }
  2548. qla2x00_handle_mbx_completion(ha, status);
  2549. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2550. return IRQ_HANDLED;
  2551. }
  2552. /** QLAFX00 specific IOCB implementation functions */
  2553. static inline cont_a64_entry_t *
  2554. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2555. cont_a64_entry_t *lcont_pkt)
  2556. {
  2557. cont_a64_entry_t *cont_pkt;
  2558. /* Adjust ring index. */
  2559. req->ring_index++;
  2560. if (req->ring_index == req->length) {
  2561. req->ring_index = 0;
  2562. req->ring_ptr = req->ring;
  2563. } else {
  2564. req->ring_ptr++;
  2565. }
  2566. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2567. /* Load packet defaults. */
  2568. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2569. return cont_pkt;
  2570. }
  2571. static inline void
  2572. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2573. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2574. {
  2575. uint16_t avail_dsds;
  2576. __le32 *cur_dsd;
  2577. scsi_qla_host_t *vha;
  2578. struct scsi_cmnd *cmd;
  2579. struct scatterlist *sg;
  2580. int i, cont;
  2581. struct req_que *req;
  2582. cont_a64_entry_t lcont_pkt;
  2583. cont_a64_entry_t *cont_pkt;
  2584. vha = sp->fcport->vha;
  2585. req = vha->req;
  2586. cmd = GET_CMD_SP(sp);
  2587. cont = 0;
  2588. cont_pkt = NULL;
  2589. /* Update entry type to indicate Command Type 3 IOCB */
  2590. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2591. /* No data transfer */
  2592. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2593. lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
  2594. return;
  2595. }
  2596. /* Set transfer direction */
  2597. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2598. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2599. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2600. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2601. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2602. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2603. }
  2604. /* One DSD is available in the Command Type 3 IOCB */
  2605. avail_dsds = 1;
  2606. cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
  2607. /* Load data segments */
  2608. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2609. dma_addr_t sle_dma;
  2610. /* Allocate additional continuation packets? */
  2611. if (avail_dsds == 0) {
  2612. /*
  2613. * Five DSDs are available in the Continuation
  2614. * Type 1 IOCB.
  2615. */
  2616. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2617. cont_pkt =
  2618. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2619. cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
  2620. avail_dsds = 5;
  2621. cont = 1;
  2622. }
  2623. sle_dma = sg_dma_address(sg);
  2624. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2625. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2626. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2627. avail_dsds--;
  2628. if (avail_dsds == 0 && cont == 1) {
  2629. cont = 0;
  2630. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2631. REQUEST_ENTRY_SIZE);
  2632. }
  2633. }
  2634. if (avail_dsds != 0 && cont == 1) {
  2635. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2636. REQUEST_ENTRY_SIZE);
  2637. }
  2638. }
  2639. /**
  2640. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2641. * @sp: command to send to the ISP
  2642. *
  2643. * Returns non-zero if a failure occurred, else zero.
  2644. */
  2645. int
  2646. qlafx00_start_scsi(srb_t *sp)
  2647. {
  2648. int ret, nseg;
  2649. unsigned long flags;
  2650. uint32_t index;
  2651. uint32_t handle;
  2652. uint16_t cnt;
  2653. uint16_t req_cnt;
  2654. uint16_t tot_dsds;
  2655. struct req_que *req = NULL;
  2656. struct rsp_que *rsp = NULL;
  2657. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2658. struct scsi_qla_host *vha = sp->fcport->vha;
  2659. struct qla_hw_data *ha = vha->hw;
  2660. struct cmd_type_7_fx00 *cmd_pkt;
  2661. struct cmd_type_7_fx00 lcmd_pkt;
  2662. struct scsi_lun llun;
  2663. /* Setup device pointers. */
  2664. ret = 0;
  2665. rsp = ha->rsp_q_map[0];
  2666. req = vha->req;
  2667. /* So we know we haven't pci_map'ed anything yet */
  2668. tot_dsds = 0;
  2669. /* Acquire ring specific lock */
  2670. spin_lock_irqsave(&ha->hardware_lock, flags);
  2671. /* Check for room in outstanding command list. */
  2672. handle = req->current_outstanding_cmd;
  2673. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2674. handle++;
  2675. if (handle == req->num_outstanding_cmds)
  2676. handle = 1;
  2677. if (!req->outstanding_cmds[handle])
  2678. break;
  2679. }
  2680. if (index == req->num_outstanding_cmds)
  2681. goto queuing_error;
  2682. /* Map the sg table so we have an accurate count of sg entries needed */
  2683. if (scsi_sg_count(cmd)) {
  2684. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2685. scsi_sg_count(cmd), cmd->sc_data_direction);
  2686. if (unlikely(!nseg))
  2687. goto queuing_error;
  2688. } else
  2689. nseg = 0;
  2690. tot_dsds = nseg;
  2691. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2692. if (req->cnt < (req_cnt + 2)) {
  2693. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2694. if (req->ring_index < cnt)
  2695. req->cnt = cnt - req->ring_index;
  2696. else
  2697. req->cnt = req->length -
  2698. (req->ring_index - cnt);
  2699. if (req->cnt < (req_cnt + 2))
  2700. goto queuing_error;
  2701. }
  2702. /* Build command packet. */
  2703. req->current_outstanding_cmd = handle;
  2704. req->outstanding_cmds[handle] = sp;
  2705. sp->handle = handle;
  2706. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2707. req->cnt -= req_cnt;
  2708. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2709. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2710. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2711. lcmd_pkt.reserved_0 = 0;
  2712. lcmd_pkt.port_path_ctrl = 0;
  2713. lcmd_pkt.reserved_1 = 0;
  2714. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2715. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2716. int_to_scsilun(cmd->device->lun, &llun);
  2717. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2718. sizeof(lcmd_pkt.lun));
  2719. /* Load SCSI command packet. */
  2720. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2721. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2722. /* Build IOCB segments */
  2723. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2724. /* Set total data segment count. */
  2725. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2726. /* Specify response queue number where completion should happen */
  2727. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2728. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2729. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2730. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2731. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2732. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2733. wmb();
  2734. /* Adjust ring index. */
  2735. req->ring_index++;
  2736. if (req->ring_index == req->length) {
  2737. req->ring_index = 0;
  2738. req->ring_ptr = req->ring;
  2739. } else
  2740. req->ring_ptr++;
  2741. sp->flags |= SRB_DMA_VALID;
  2742. /* Set chip new ring index. */
  2743. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2744. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2745. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2746. return QLA_SUCCESS;
  2747. queuing_error:
  2748. if (tot_dsds)
  2749. scsi_dma_unmap(cmd);
  2750. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2751. return QLA_FUNCTION_FAILED;
  2752. }
  2753. void
  2754. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2755. {
  2756. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2757. scsi_qla_host_t *vha = sp->fcport->vha;
  2758. struct req_que *req = vha->req;
  2759. struct tsk_mgmt_entry_fx00 tm_iocb;
  2760. struct scsi_lun llun;
  2761. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2762. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2763. tm_iocb.entry_count = 1;
  2764. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2765. tm_iocb.reserved_0 = 0;
  2766. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2767. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2768. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2769. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2770. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2771. sizeof(struct scsi_lun));
  2772. }
  2773. memcpy((void *)ptm_iocb, &tm_iocb,
  2774. sizeof(struct tsk_mgmt_entry_fx00));
  2775. wmb();
  2776. }
  2777. void
  2778. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2779. {
  2780. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2781. scsi_qla_host_t *vha = sp->fcport->vha;
  2782. struct req_que *req = vha->req;
  2783. struct abort_iocb_entry_fx00 abt_iocb;
  2784. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2785. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2786. abt_iocb.entry_count = 1;
  2787. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2788. abt_iocb.abort_handle =
  2789. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2790. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2791. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2792. memcpy((void *)pabt_iocb, &abt_iocb,
  2793. sizeof(struct abort_iocb_entry_fx00));
  2794. wmb();
  2795. }
  2796. void
  2797. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2798. {
  2799. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2800. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2801. struct fc_bsg_job *bsg_job;
  2802. struct fxdisc_entry_fx00 fx_iocb;
  2803. uint8_t entry_cnt = 1;
  2804. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2805. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2806. fx_iocb.handle = cpu_to_le32(sp->handle);
  2807. fx_iocb.entry_count = entry_cnt;
  2808. if (sp->type == SRB_FXIOCB_DCMD) {
  2809. fx_iocb.func_num =
  2810. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2811. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2812. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2813. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2814. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2815. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2816. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2817. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2818. fx_iocb.req_xfrcnt =
  2819. cpu_to_le16(fxio->u.fxiocb.req_len);
  2820. fx_iocb.dseg_rq_address[0] =
  2821. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2822. fx_iocb.dseg_rq_address[1] =
  2823. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2824. fx_iocb.dseg_rq_len =
  2825. cpu_to_le32(fxio->u.fxiocb.req_len);
  2826. }
  2827. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2828. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2829. fx_iocb.rsp_xfrcnt =
  2830. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2831. fx_iocb.dseg_rsp_address[0] =
  2832. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2833. fx_iocb.dseg_rsp_address[1] =
  2834. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2835. fx_iocb.dseg_rsp_len =
  2836. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2837. }
  2838. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2839. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2840. }
  2841. fx_iocb.flags = fxio->u.fxiocb.flags;
  2842. } else {
  2843. struct scatterlist *sg;
  2844. bsg_job = sp->u.bsg_job;
  2845. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2846. &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  2847. fx_iocb.func_num = piocb_rqst->func_type;
  2848. fx_iocb.adapid = piocb_rqst->adapid;
  2849. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2850. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2851. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2852. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2853. fx_iocb.dataword = piocb_rqst->dataword;
  2854. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2855. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2856. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2857. int avail_dsds, tot_dsds;
  2858. cont_a64_entry_t lcont_pkt;
  2859. cont_a64_entry_t *cont_pkt = NULL;
  2860. __le32 *cur_dsd;
  2861. int index = 0, cont = 0;
  2862. fx_iocb.req_dsdcnt =
  2863. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2864. tot_dsds =
  2865. bsg_job->request_payload.sg_cnt;
  2866. cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
  2867. avail_dsds = 1;
  2868. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2869. tot_dsds, index) {
  2870. dma_addr_t sle_dma;
  2871. /* Allocate additional continuation packets? */
  2872. if (avail_dsds == 0) {
  2873. /*
  2874. * Five DSDs are available in the Cont.
  2875. * Type 1 IOCB.
  2876. */
  2877. memset(&lcont_pkt, 0,
  2878. REQUEST_ENTRY_SIZE);
  2879. cont_pkt =
  2880. qlafx00_prep_cont_type1_iocb(
  2881. sp->fcport->vha->req,
  2882. &lcont_pkt);
  2883. cur_dsd = (__le32 *)
  2884. lcont_pkt.dseg_0_address;
  2885. avail_dsds = 5;
  2886. cont = 1;
  2887. entry_cnt++;
  2888. }
  2889. sle_dma = sg_dma_address(sg);
  2890. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2891. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2892. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2893. avail_dsds--;
  2894. if (avail_dsds == 0 && cont == 1) {
  2895. cont = 0;
  2896. memcpy_toio(
  2897. (void __iomem *)cont_pkt,
  2898. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2899. ql_dump_buffer(
  2900. ql_dbg_user + ql_dbg_verbose,
  2901. sp->fcport->vha, 0x3042,
  2902. (uint8_t *)&lcont_pkt,
  2903. REQUEST_ENTRY_SIZE);
  2904. }
  2905. }
  2906. if (avail_dsds != 0 && cont == 1) {
  2907. memcpy_toio((void __iomem *)cont_pkt,
  2908. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2909. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2910. sp->fcport->vha, 0x3043,
  2911. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2912. }
  2913. }
  2914. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  2915. int avail_dsds, tot_dsds;
  2916. cont_a64_entry_t lcont_pkt;
  2917. cont_a64_entry_t *cont_pkt = NULL;
  2918. __le32 *cur_dsd;
  2919. int index = 0, cont = 0;
  2920. fx_iocb.rsp_dsdcnt =
  2921. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  2922. tot_dsds = bsg_job->reply_payload.sg_cnt;
  2923. cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
  2924. avail_dsds = 1;
  2925. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  2926. tot_dsds, index) {
  2927. dma_addr_t sle_dma;
  2928. /* Allocate additional continuation packets? */
  2929. if (avail_dsds == 0) {
  2930. /*
  2931. * Five DSDs are available in the Cont.
  2932. * Type 1 IOCB.
  2933. */
  2934. memset(&lcont_pkt, 0,
  2935. REQUEST_ENTRY_SIZE);
  2936. cont_pkt =
  2937. qlafx00_prep_cont_type1_iocb(
  2938. sp->fcport->vha->req,
  2939. &lcont_pkt);
  2940. cur_dsd = (__le32 *)
  2941. lcont_pkt.dseg_0_address;
  2942. avail_dsds = 5;
  2943. cont = 1;
  2944. entry_cnt++;
  2945. }
  2946. sle_dma = sg_dma_address(sg);
  2947. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2948. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2949. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2950. avail_dsds--;
  2951. if (avail_dsds == 0 && cont == 1) {
  2952. cont = 0;
  2953. memcpy_toio((void __iomem *)cont_pkt,
  2954. &lcont_pkt,
  2955. REQUEST_ENTRY_SIZE);
  2956. ql_dump_buffer(
  2957. ql_dbg_user + ql_dbg_verbose,
  2958. sp->fcport->vha, 0x3045,
  2959. (uint8_t *)&lcont_pkt,
  2960. REQUEST_ENTRY_SIZE);
  2961. }
  2962. }
  2963. if (avail_dsds != 0 && cont == 1) {
  2964. memcpy_toio((void __iomem *)cont_pkt,
  2965. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2966. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2967. sp->fcport->vha, 0x3046,
  2968. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2969. }
  2970. }
  2971. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  2972. fx_iocb.dataword = piocb_rqst->dataword;
  2973. fx_iocb.flags = piocb_rqst->flags;
  2974. fx_iocb.entry_count = entry_cnt;
  2975. }
  2976. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2977. sp->fcport->vha, 0x3047,
  2978. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  2979. memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
  2980. sizeof(struct fxdisc_entry_fx00));
  2981. wmb();
  2982. }