bnx2fc_hwi.c 62 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196
  1. /* bnx2fc_hwi.c: QLogic NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2013 Broadcom Corporation
  6. * Copyright (c) 2014, QLogic Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation.
  11. *
  12. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  13. */
  14. #include "bnx2fc.h"
  15. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  16. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  17. struct fcoe_kcqe *new_cqe_kcqe);
  18. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  19. struct fcoe_kcqe *ofld_kcqe);
  20. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  21. struct fcoe_kcqe *ofld_kcqe);
  22. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  23. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  24. struct fcoe_kcqe *destroy_kcqe);
  25. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  26. {
  27. struct fcoe_kwqe_stat stat_req;
  28. struct kwqe *kwqe_arr[2];
  29. int num_kwqes = 1;
  30. int rc = 0;
  31. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  32. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  33. stat_req.hdr.flags =
  34. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  35. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  36. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  37. kwqe_arr[0] = (struct kwqe *) &stat_req;
  38. if (hba->cnic && hba->cnic->submit_kwqes)
  39. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  40. return rc;
  41. }
  42. /**
  43. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  44. *
  45. * @hba: adapter structure pointer
  46. *
  47. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  48. * with the f/w.
  49. *
  50. */
  51. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  52. {
  53. struct fcoe_kwqe_init1 fcoe_init1;
  54. struct fcoe_kwqe_init2 fcoe_init2;
  55. struct fcoe_kwqe_init3 fcoe_init3;
  56. struct kwqe *kwqe_arr[3];
  57. int num_kwqes = 3;
  58. int rc = 0;
  59. if (!hba->cnic) {
  60. printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
  61. return -ENODEV;
  62. }
  63. /* fill init1 KWQE */
  64. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  65. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  66. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  67. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  68. fcoe_init1.num_tasks = hba->max_tasks;
  69. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  70. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  71. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  72. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  73. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  74. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  75. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  76. fcoe_init1.task_list_pbl_addr_hi =
  77. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  78. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  79. fcoe_init1.flags = (PAGE_SHIFT <<
  80. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  81. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  82. /* fill init2 KWQE */
  83. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  84. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  85. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  86. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  87. fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
  88. fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
  89. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  90. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  91. ((u64) hba->hash_tbl_pbl_dma >> 32);
  92. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  93. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  94. ((u64) hba->t2_hash_tbl_dma >> 32);
  95. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  96. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  97. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  98. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  99. /* fill init3 KWQE */
  100. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  101. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  102. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  103. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  104. fcoe_init3.error_bit_map_lo = 0xffffffff;
  105. fcoe_init3.error_bit_map_hi = 0xffffffff;
  106. /*
  107. * enable both cached connection and cached tasks
  108. * 0 = none, 1 = cached connection, 2 = cached tasks, 3 = both
  109. */
  110. fcoe_init3.perf_config = 3;
  111. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  112. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  113. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  114. if (hba->cnic && hba->cnic->submit_kwqes)
  115. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  116. return rc;
  117. }
  118. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  119. {
  120. struct fcoe_kwqe_destroy fcoe_destroy;
  121. struct kwqe *kwqe_arr[2];
  122. int num_kwqes = 1;
  123. int rc = -1;
  124. /* fill destroy KWQE */
  125. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  126. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  127. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  128. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  129. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  130. if (hba->cnic && hba->cnic->submit_kwqes)
  131. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  132. return rc;
  133. }
  134. /**
  135. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  136. *
  137. * @port: port structure pointer
  138. * @tgt: bnx2fc_rport structure pointer
  139. */
  140. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  141. struct bnx2fc_rport *tgt)
  142. {
  143. struct fc_lport *lport = port->lport;
  144. struct bnx2fc_interface *interface = port->priv;
  145. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  146. struct bnx2fc_hba *hba = interface->hba;
  147. struct kwqe *kwqe_arr[4];
  148. struct fcoe_kwqe_conn_offload1 ofld_req1;
  149. struct fcoe_kwqe_conn_offload2 ofld_req2;
  150. struct fcoe_kwqe_conn_offload3 ofld_req3;
  151. struct fcoe_kwqe_conn_offload4 ofld_req4;
  152. struct fc_rport_priv *rdata = tgt->rdata;
  153. struct fc_rport *rport = tgt->rport;
  154. int num_kwqes = 4;
  155. u32 port_id;
  156. int rc = 0;
  157. u16 conn_id;
  158. /* Initialize offload request 1 structure */
  159. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  160. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  161. ofld_req1.hdr.flags =
  162. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  163. conn_id = (u16)tgt->fcoe_conn_id;
  164. ofld_req1.fcoe_conn_id = conn_id;
  165. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  166. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  167. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  168. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  169. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  170. ofld_req1.rq_first_pbe_addr_hi =
  171. (u32)((u64) tgt->rq_dma >> 32);
  172. ofld_req1.rq_prod = 0x8000;
  173. /* Initialize offload request 2 structure */
  174. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  175. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  176. ofld_req2.hdr.flags =
  177. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  178. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  179. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  180. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  181. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  182. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  183. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  184. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  185. /* Initialize offload request 3 structure */
  186. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  187. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  188. ofld_req3.hdr.flags =
  189. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  190. ofld_req3.vlan_tag = interface->vlan_id <<
  191. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  192. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  193. port_id = fc_host_port_id(lport->host);
  194. if (port_id == 0) {
  195. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  196. return -EINVAL;
  197. }
  198. /*
  199. * Store s_id of the initiator for further reference. This will
  200. * be used during disable/destroy during linkdown processing as
  201. * when the lport is reset, the port_id also is reset to 0
  202. */
  203. tgt->sid = port_id;
  204. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  205. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  206. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  207. port_id = rport->port_id;
  208. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  209. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  210. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  211. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  212. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  213. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  214. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  215. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  216. ofld_req3.rx_open_seqs_exch_c3 = 1;
  217. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  218. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  219. /* set mul_n_port_ids supported flag to 0, until it is supported */
  220. ofld_req3.flags = 0;
  221. /*
  222. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  223. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  224. */
  225. /* Info from PLOGI response */
  226. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  227. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  228. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  229. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  230. /*
  231. * Info from PRLI response, this info is used for sequence level error
  232. * recovery support
  233. */
  234. if (tgt->dev_type == TYPE_TAPE) {
  235. ofld_req3.flags |= 1 <<
  236. FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
  237. ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
  238. ? 1 : 0) <<
  239. FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
  240. }
  241. /* vlan flag */
  242. ofld_req3.flags |= (interface->vlan_enabled <<
  243. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  244. /* C2_VALID and ACK flags are not set as they are not supported */
  245. /* Initialize offload request 4 structure */
  246. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  247. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  248. ofld_req4.hdr.flags =
  249. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  250. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  251. ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
  252. /* local mac */
  253. ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
  254. ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
  255. ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
  256. ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
  257. ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
  258. ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  259. /* fcf mac */
  260. ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  261. ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  262. ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  263. ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  264. ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  265. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  266. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  267. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  268. ofld_req4.confq_pbl_base_addr_hi =
  269. (u32)((u64) tgt->confq_pbl_dma >> 32);
  270. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  271. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  272. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  273. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  274. if (hba->cnic && hba->cnic->submit_kwqes)
  275. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  276. return rc;
  277. }
  278. /**
  279. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  280. *
  281. * @port: port structure pointer
  282. * @tgt: bnx2fc_rport structure pointer
  283. */
  284. int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  285. struct bnx2fc_rport *tgt)
  286. {
  287. struct kwqe *kwqe_arr[2];
  288. struct bnx2fc_interface *interface = port->priv;
  289. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  290. struct bnx2fc_hba *hba = interface->hba;
  291. struct fcoe_kwqe_conn_enable_disable enbl_req;
  292. struct fc_lport *lport = port->lport;
  293. struct fc_rport *rport = tgt->rport;
  294. int num_kwqes = 1;
  295. int rc = 0;
  296. u32 port_id;
  297. memset(&enbl_req, 0x00,
  298. sizeof(struct fcoe_kwqe_conn_enable_disable));
  299. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  300. enbl_req.hdr.flags =
  301. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  302. enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
  303. /* local mac */
  304. enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
  305. enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
  306. enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
  307. enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
  308. enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
  309. memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
  310. enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  311. enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  312. enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  313. enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  314. enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  315. enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  316. port_id = fc_host_port_id(lport->host);
  317. if (port_id != tgt->sid) {
  318. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  319. "sid = 0x%x\n", port_id, tgt->sid);
  320. port_id = tgt->sid;
  321. }
  322. enbl_req.s_id[0] = (port_id & 0x000000FF);
  323. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  324. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  325. port_id = rport->port_id;
  326. enbl_req.d_id[0] = (port_id & 0x000000FF);
  327. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  328. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  329. enbl_req.vlan_tag = interface->vlan_id <<
  330. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  331. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  332. enbl_req.vlan_flag = interface->vlan_enabled;
  333. enbl_req.context_id = tgt->context_id;
  334. enbl_req.conn_id = tgt->fcoe_conn_id;
  335. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  336. if (hba->cnic && hba->cnic->submit_kwqes)
  337. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  338. return rc;
  339. }
  340. /**
  341. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  342. *
  343. * @port: port structure pointer
  344. * @tgt: bnx2fc_rport structure pointer
  345. */
  346. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  347. struct bnx2fc_rport *tgt)
  348. {
  349. struct bnx2fc_interface *interface = port->priv;
  350. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  351. struct bnx2fc_hba *hba = interface->hba;
  352. struct fcoe_kwqe_conn_enable_disable disable_req;
  353. struct kwqe *kwqe_arr[2];
  354. struct fc_rport *rport = tgt->rport;
  355. int num_kwqes = 1;
  356. int rc = 0;
  357. u32 port_id;
  358. memset(&disable_req, 0x00,
  359. sizeof(struct fcoe_kwqe_conn_enable_disable));
  360. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  361. disable_req.hdr.flags =
  362. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  363. disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
  364. disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
  365. disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
  366. disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
  367. disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
  368. disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
  369. disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  370. disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  371. disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  372. disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  373. disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  374. disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  375. port_id = tgt->sid;
  376. disable_req.s_id[0] = (port_id & 0x000000FF);
  377. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  378. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  379. port_id = rport->port_id;
  380. disable_req.d_id[0] = (port_id & 0x000000FF);
  381. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  382. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  383. disable_req.context_id = tgt->context_id;
  384. disable_req.conn_id = tgt->fcoe_conn_id;
  385. disable_req.vlan_tag = interface->vlan_id <<
  386. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  387. disable_req.vlan_tag |=
  388. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  389. disable_req.vlan_flag = interface->vlan_enabled;
  390. kwqe_arr[0] = (struct kwqe *) &disable_req;
  391. if (hba->cnic && hba->cnic->submit_kwqes)
  392. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  393. return rc;
  394. }
  395. /**
  396. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  397. *
  398. * @port: port structure pointer
  399. * @tgt: bnx2fc_rport structure pointer
  400. */
  401. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  402. struct bnx2fc_rport *tgt)
  403. {
  404. struct fcoe_kwqe_conn_destroy destroy_req;
  405. struct kwqe *kwqe_arr[2];
  406. int num_kwqes = 1;
  407. int rc = 0;
  408. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  409. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  410. destroy_req.hdr.flags =
  411. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  412. destroy_req.context_id = tgt->context_id;
  413. destroy_req.conn_id = tgt->fcoe_conn_id;
  414. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  415. if (hba->cnic && hba->cnic->submit_kwqes)
  416. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  417. return rc;
  418. }
  419. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  420. {
  421. struct bnx2fc_lport *blport;
  422. spin_lock_bh(&hba->hba_lock);
  423. list_for_each_entry(blport, &hba->vports, list) {
  424. if (blport->lport == lport) {
  425. spin_unlock_bh(&hba->hba_lock);
  426. return true;
  427. }
  428. }
  429. spin_unlock_bh(&hba->hba_lock);
  430. return false;
  431. }
  432. static void bnx2fc_unsol_els_work(struct work_struct *work)
  433. {
  434. struct bnx2fc_unsol_els *unsol_els;
  435. struct fc_lport *lport;
  436. struct bnx2fc_hba *hba;
  437. struct fc_frame *fp;
  438. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  439. lport = unsol_els->lport;
  440. fp = unsol_els->fp;
  441. hba = unsol_els->hba;
  442. if (is_valid_lport(hba, lport))
  443. fc_exch_recv(lport, fp);
  444. kfree(unsol_els);
  445. }
  446. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  447. unsigned char *buf,
  448. u32 frame_len, u16 l2_oxid)
  449. {
  450. struct fcoe_port *port = tgt->port;
  451. struct fc_lport *lport = port->lport;
  452. struct bnx2fc_interface *interface = port->priv;
  453. struct bnx2fc_unsol_els *unsol_els;
  454. struct fc_frame_header *fh;
  455. struct fc_frame *fp;
  456. struct sk_buff *skb;
  457. u32 payload_len;
  458. u32 crc;
  459. u8 op;
  460. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  461. if (!unsol_els) {
  462. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  463. return;
  464. }
  465. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  466. l2_oxid, frame_len);
  467. payload_len = frame_len - sizeof(struct fc_frame_header);
  468. fp = fc_frame_alloc(lport, payload_len);
  469. if (!fp) {
  470. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  471. kfree(unsol_els);
  472. return;
  473. }
  474. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  475. /* Copy FC Frame header and payload into the frame */
  476. memcpy(fh, buf, frame_len);
  477. if (l2_oxid != FC_XID_UNKNOWN)
  478. fh->fh_ox_id = htons(l2_oxid);
  479. skb = fp_skb(fp);
  480. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  481. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  482. if (fh->fh_type == FC_TYPE_ELS) {
  483. op = fc_frame_payload_op(fp);
  484. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  485. (op == ELS_FAN) || (op == ELS_CSU)) {
  486. /*
  487. * No need to reply for these
  488. * ELS requests
  489. */
  490. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  491. kfree_skb(skb);
  492. kfree(unsol_els);
  493. return;
  494. }
  495. }
  496. crc = fcoe_fc_crc(fp);
  497. fc_frame_init(fp);
  498. fr_dev(fp) = lport;
  499. fr_sof(fp) = FC_SOF_I3;
  500. fr_eof(fp) = FC_EOF_T;
  501. fr_crc(fp) = cpu_to_le32(~crc);
  502. unsol_els->lport = lport;
  503. unsol_els->hba = interface->hba;
  504. unsol_els->fp = fp;
  505. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  506. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  507. } else {
  508. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  509. kfree_skb(skb);
  510. kfree(unsol_els);
  511. }
  512. }
  513. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  514. {
  515. u8 num_rq;
  516. struct fcoe_err_report_entry *err_entry;
  517. unsigned char *rq_data;
  518. unsigned char *buf = NULL, *buf1;
  519. int i;
  520. u16 xid;
  521. u32 frame_len, len;
  522. struct bnx2fc_cmd *io_req = NULL;
  523. struct fcoe_task_ctx_entry *task, *task_page;
  524. struct bnx2fc_interface *interface = tgt->port->priv;
  525. struct bnx2fc_hba *hba = interface->hba;
  526. int task_idx, index;
  527. int rc = 0;
  528. u64 err_warn_bit_map;
  529. u8 err_warn = 0xff;
  530. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  531. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  532. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  533. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  534. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  535. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  536. spin_lock_bh(&tgt->tgt_lock);
  537. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  538. spin_unlock_bh(&tgt->tgt_lock);
  539. if (rq_data) {
  540. buf = rq_data;
  541. } else {
  542. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  543. GFP_ATOMIC);
  544. if (!buf1) {
  545. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  546. break;
  547. }
  548. for (i = 0; i < num_rq; i++) {
  549. spin_lock_bh(&tgt->tgt_lock);
  550. rq_data = (unsigned char *)
  551. bnx2fc_get_next_rqe(tgt, 1);
  552. spin_unlock_bh(&tgt->tgt_lock);
  553. len = BNX2FC_RQ_BUF_SZ;
  554. memcpy(buf1, rq_data, len);
  555. buf1 += len;
  556. }
  557. }
  558. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  559. FC_XID_UNKNOWN);
  560. if (buf != rq_data)
  561. kfree(buf);
  562. spin_lock_bh(&tgt->tgt_lock);
  563. bnx2fc_return_rqe(tgt, num_rq);
  564. spin_unlock_bh(&tgt->tgt_lock);
  565. break;
  566. case FCOE_ERROR_DETECTION_CQE_TYPE:
  567. /*
  568. * In case of error reporting CQE a single RQ entry
  569. * is consumed.
  570. */
  571. spin_lock_bh(&tgt->tgt_lock);
  572. num_rq = 1;
  573. err_entry = (struct fcoe_err_report_entry *)
  574. bnx2fc_get_next_rqe(tgt, 1);
  575. xid = err_entry->fc_hdr.ox_id;
  576. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  577. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  578. err_entry->data.err_warn_bitmap_hi,
  579. err_entry->data.err_warn_bitmap_lo);
  580. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  581. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  582. if (xid > hba->max_xid) {
  583. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  584. xid);
  585. goto ret_err_rqe;
  586. }
  587. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  588. index = xid % BNX2FC_TASKS_PER_PAGE;
  589. task_page = (struct fcoe_task_ctx_entry *)
  590. hba->task_ctx[task_idx];
  591. task = &(task_page[index]);
  592. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  593. if (!io_req)
  594. goto ret_err_rqe;
  595. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  596. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  597. goto ret_err_rqe;
  598. }
  599. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  600. &io_req->req_flags)) {
  601. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  602. "progress.. ignore unsol err\n");
  603. goto ret_err_rqe;
  604. }
  605. err_warn_bit_map = (u64)
  606. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  607. (u64)err_entry->data.err_warn_bitmap_lo;
  608. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  609. if (err_warn_bit_map & (u64)((u64)1 << i)) {
  610. err_warn = i;
  611. break;
  612. }
  613. }
  614. /*
  615. * If ABTS is already in progress, and FW error is
  616. * received after that, do not cancel the timeout_work
  617. * and let the error recovery continue by explicitly
  618. * logging out the target, when the ABTS eventually
  619. * times out.
  620. */
  621. if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) {
  622. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  623. "in ABTS processing\n", xid);
  624. goto ret_err_rqe;
  625. }
  626. BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn);
  627. if (tgt->dev_type != TYPE_TAPE)
  628. goto skip_rec;
  629. switch (err_warn) {
  630. case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION:
  631. case FCOE_ERROR_CODE_DATA_OOO_RO:
  632. case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT:
  633. case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET:
  634. case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ:
  635. case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET:
  636. BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n",
  637. xid);
  638. memcpy(&io_req->err_entry, err_entry,
  639. sizeof(struct fcoe_err_report_entry));
  640. if (!test_bit(BNX2FC_FLAG_SRR_SENT,
  641. &io_req->req_flags)) {
  642. spin_unlock_bh(&tgt->tgt_lock);
  643. rc = bnx2fc_send_rec(io_req);
  644. spin_lock_bh(&tgt->tgt_lock);
  645. if (rc)
  646. goto skip_rec;
  647. } else
  648. printk(KERN_ERR PFX "SRR in progress\n");
  649. goto ret_err_rqe;
  650. break;
  651. default:
  652. break;
  653. }
  654. skip_rec:
  655. set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags);
  656. /*
  657. * Cancel the timeout_work, as we received IO
  658. * completion with FW error.
  659. */
  660. if (cancel_delayed_work(&io_req->timeout_work))
  661. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  662. rc = bnx2fc_initiate_abts(io_req);
  663. if (rc != SUCCESS) {
  664. printk(KERN_ERR PFX "err_warn: initiate_abts "
  665. "failed xid = 0x%x. issue cleanup\n",
  666. io_req->xid);
  667. bnx2fc_initiate_cleanup(io_req);
  668. }
  669. ret_err_rqe:
  670. bnx2fc_return_rqe(tgt, 1);
  671. spin_unlock_bh(&tgt->tgt_lock);
  672. break;
  673. case FCOE_WARNING_DETECTION_CQE_TYPE:
  674. /*
  675. *In case of warning reporting CQE a single RQ entry
  676. * is consumes.
  677. */
  678. spin_lock_bh(&tgt->tgt_lock);
  679. num_rq = 1;
  680. err_entry = (struct fcoe_err_report_entry *)
  681. bnx2fc_get_next_rqe(tgt, 1);
  682. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  683. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  684. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  685. err_entry->data.err_warn_bitmap_hi,
  686. err_entry->data.err_warn_bitmap_lo);
  687. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  688. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  689. if (xid > hba->max_xid) {
  690. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid);
  691. goto ret_warn_rqe;
  692. }
  693. err_warn_bit_map = (u64)
  694. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  695. (u64)err_entry->data.err_warn_bitmap_lo;
  696. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  697. if (err_warn_bit_map & (u64) (1 << i)) {
  698. err_warn = i;
  699. break;
  700. }
  701. }
  702. BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn);
  703. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  704. index = xid % BNX2FC_TASKS_PER_PAGE;
  705. task_page = (struct fcoe_task_ctx_entry *)
  706. interface->hba->task_ctx[task_idx];
  707. task = &(task_page[index]);
  708. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  709. if (!io_req)
  710. goto ret_warn_rqe;
  711. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  712. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  713. goto ret_warn_rqe;
  714. }
  715. memcpy(&io_req->err_entry, err_entry,
  716. sizeof(struct fcoe_err_report_entry));
  717. if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION)
  718. /* REC_TOV is not a warning code */
  719. BUG_ON(1);
  720. else
  721. BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n");
  722. ret_warn_rqe:
  723. bnx2fc_return_rqe(tgt, 1);
  724. spin_unlock_bh(&tgt->tgt_lock);
  725. break;
  726. default:
  727. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  728. break;
  729. }
  730. }
  731. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  732. {
  733. struct fcoe_task_ctx_entry *task;
  734. struct fcoe_task_ctx_entry *task_page;
  735. struct fcoe_port *port = tgt->port;
  736. struct bnx2fc_interface *interface = port->priv;
  737. struct bnx2fc_hba *hba = interface->hba;
  738. struct bnx2fc_cmd *io_req;
  739. int task_idx, index;
  740. u16 xid;
  741. u8 cmd_type;
  742. u8 rx_state = 0;
  743. u8 num_rq;
  744. spin_lock_bh(&tgt->tgt_lock);
  745. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  746. if (xid >= hba->max_tasks) {
  747. printk(KERN_ERR PFX "ERROR:xid out of range\n");
  748. spin_unlock_bh(&tgt->tgt_lock);
  749. return;
  750. }
  751. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  752. index = xid % BNX2FC_TASKS_PER_PAGE;
  753. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  754. task = &(task_page[index]);
  755. num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
  756. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
  757. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
  758. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  759. if (io_req == NULL) {
  760. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  761. spin_unlock_bh(&tgt->tgt_lock);
  762. return;
  763. }
  764. /* Timestamp IO completion time */
  765. cmd_type = io_req->cmd_type;
  766. rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
  767. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
  768. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
  769. /* Process other IO completion types */
  770. switch (cmd_type) {
  771. case BNX2FC_SCSI_CMD:
  772. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  773. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  774. spin_unlock_bh(&tgt->tgt_lock);
  775. return;
  776. }
  777. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  778. bnx2fc_process_abts_compl(io_req, task, num_rq);
  779. else if (rx_state ==
  780. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  781. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  782. else
  783. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  784. rx_state);
  785. break;
  786. case BNX2FC_TASK_MGMT_CMD:
  787. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  788. bnx2fc_process_tm_compl(io_req, task, num_rq);
  789. break;
  790. case BNX2FC_ABTS:
  791. /*
  792. * ABTS request received by firmware. ABTS response
  793. * will be delivered to the task belonging to the IO
  794. * that was aborted
  795. */
  796. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  797. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  798. break;
  799. case BNX2FC_ELS:
  800. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
  801. bnx2fc_process_els_compl(io_req, task, num_rq);
  802. else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  803. bnx2fc_process_abts_compl(io_req, task, num_rq);
  804. else if (rx_state ==
  805. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  806. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  807. else
  808. printk(KERN_ERR PFX "Invalid rx state = %d\n",
  809. rx_state);
  810. break;
  811. case BNX2FC_CLEANUP:
  812. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  813. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  814. break;
  815. case BNX2FC_SEQ_CLEANUP:
  816. BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
  817. io_req->xid);
  818. bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
  819. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  820. break;
  821. default:
  822. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  823. break;
  824. }
  825. spin_unlock_bh(&tgt->tgt_lock);
  826. }
  827. void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
  828. {
  829. struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
  830. u32 msg;
  831. wmb();
  832. rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
  833. FCOE_CQE_TOGGLE_BIT_SHIFT);
  834. msg = *((u32 *)rx_db);
  835. writel(cpu_to_le32(msg), tgt->ctx_base);
  836. mmiowb();
  837. }
  838. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  839. {
  840. struct bnx2fc_work *work;
  841. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  842. if (!work)
  843. return NULL;
  844. INIT_LIST_HEAD(&work->list);
  845. work->tgt = tgt;
  846. work->wqe = wqe;
  847. return work;
  848. }
  849. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  850. {
  851. struct fcoe_cqe *cq;
  852. u32 cq_cons;
  853. struct fcoe_cqe *cqe;
  854. u32 num_free_sqes = 0;
  855. u32 num_cqes = 0;
  856. u16 wqe;
  857. /*
  858. * cq_lock is a low contention lock used to protect
  859. * the CQ data structure from being freed up during
  860. * the upload operation
  861. */
  862. spin_lock_bh(&tgt->cq_lock);
  863. if (!tgt->cq) {
  864. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  865. spin_unlock_bh(&tgt->cq_lock);
  866. return 0;
  867. }
  868. cq = tgt->cq;
  869. cq_cons = tgt->cq_cons_idx;
  870. cqe = &cq[cq_cons];
  871. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  872. (tgt->cq_curr_toggle_bit <<
  873. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  874. /* new entry on the cq */
  875. if (wqe & FCOE_CQE_CQE_TYPE) {
  876. /* Unsolicited event notification */
  877. bnx2fc_process_unsol_compl(tgt, wqe);
  878. } else {
  879. /* Pending work request completion */
  880. struct bnx2fc_work *work = NULL;
  881. struct bnx2fc_percpu_s *fps = NULL;
  882. unsigned int cpu = wqe % num_possible_cpus();
  883. fps = &per_cpu(bnx2fc_percpu, cpu);
  884. spin_lock_bh(&fps->fp_work_lock);
  885. if (unlikely(!fps->iothread))
  886. goto unlock;
  887. work = bnx2fc_alloc_work(tgt, wqe);
  888. if (work)
  889. list_add_tail(&work->list,
  890. &fps->work_list);
  891. unlock:
  892. spin_unlock_bh(&fps->fp_work_lock);
  893. /* Pending work request completion */
  894. if (fps->iothread && work)
  895. wake_up_process(fps->iothread);
  896. else
  897. bnx2fc_process_cq_compl(tgt, wqe);
  898. num_free_sqes++;
  899. }
  900. cqe++;
  901. tgt->cq_cons_idx++;
  902. num_cqes++;
  903. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  904. tgt->cq_cons_idx = 0;
  905. cqe = cq;
  906. tgt->cq_curr_toggle_bit =
  907. 1 - tgt->cq_curr_toggle_bit;
  908. }
  909. }
  910. if (num_cqes) {
  911. /* Arm CQ only if doorbell is mapped */
  912. if (tgt->ctx_base)
  913. bnx2fc_arm_cq(tgt);
  914. atomic_add(num_free_sqes, &tgt->free_sqes);
  915. }
  916. spin_unlock_bh(&tgt->cq_lock);
  917. return 0;
  918. }
  919. /**
  920. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  921. *
  922. * @hba: adapter structure pointer
  923. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  924. *
  925. * Fast path event notification handler
  926. */
  927. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  928. struct fcoe_kcqe *new_cqe_kcqe)
  929. {
  930. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  931. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  932. if (!tgt) {
  933. printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
  934. return;
  935. }
  936. bnx2fc_process_new_cqes(tgt);
  937. }
  938. /**
  939. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  940. *
  941. * @hba: adapter structure pointer
  942. * @ofld_kcqe: connection offload kcqe pointer
  943. *
  944. * handle session offload completion, enable the session if offload is
  945. * successful.
  946. */
  947. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  948. struct fcoe_kcqe *ofld_kcqe)
  949. {
  950. struct bnx2fc_rport *tgt;
  951. struct fcoe_port *port;
  952. struct bnx2fc_interface *interface;
  953. u32 conn_id;
  954. u32 context_id;
  955. conn_id = ofld_kcqe->fcoe_conn_id;
  956. context_id = ofld_kcqe->fcoe_conn_context_id;
  957. tgt = hba->tgt_ofld_list[conn_id];
  958. if (!tgt) {
  959. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  960. return;
  961. }
  962. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  963. ofld_kcqe->fcoe_conn_context_id);
  964. port = tgt->port;
  965. interface = tgt->port->priv;
  966. if (hba != interface->hba) {
  967. printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  968. goto ofld_cmpl_err;
  969. }
  970. /*
  971. * cnic has allocated a context_id for this session; use this
  972. * while enabling the session.
  973. */
  974. tgt->context_id = context_id;
  975. if (ofld_kcqe->completion_status) {
  976. if (ofld_kcqe->completion_status ==
  977. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  978. printk(KERN_ERR PFX "unable to allocate FCoE context "
  979. "resources\n");
  980. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  981. }
  982. } else {
  983. /* FW offload request successfully completed */
  984. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  985. }
  986. ofld_cmpl_err:
  987. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  988. wake_up_interruptible(&tgt->ofld_wait);
  989. }
  990. /**
  991. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  992. *
  993. * @hba: adapter structure pointer
  994. * @ofld_kcqe: connection offload kcqe pointer
  995. *
  996. * handle session enable completion, mark the rport as ready
  997. */
  998. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  999. struct fcoe_kcqe *ofld_kcqe)
  1000. {
  1001. struct bnx2fc_rport *tgt;
  1002. struct bnx2fc_interface *interface;
  1003. u32 conn_id;
  1004. u32 context_id;
  1005. context_id = ofld_kcqe->fcoe_conn_context_id;
  1006. conn_id = ofld_kcqe->fcoe_conn_id;
  1007. tgt = hba->tgt_ofld_list[conn_id];
  1008. if (!tgt) {
  1009. printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  1010. return;
  1011. }
  1012. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  1013. ofld_kcqe->fcoe_conn_context_id);
  1014. /*
  1015. * context_id should be the same for this target during offload
  1016. * and enable
  1017. */
  1018. if (tgt->context_id != context_id) {
  1019. printk(KERN_ERR PFX "context id mis-match\n");
  1020. return;
  1021. }
  1022. interface = tgt->port->priv;
  1023. if (hba != interface->hba) {
  1024. printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  1025. goto enbl_cmpl_err;
  1026. }
  1027. if (!ofld_kcqe->completion_status)
  1028. /* enable successful - rport ready for issuing IOs */
  1029. set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1030. enbl_cmpl_err:
  1031. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  1032. wake_up_interruptible(&tgt->ofld_wait);
  1033. }
  1034. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  1035. struct fcoe_kcqe *disable_kcqe)
  1036. {
  1037. struct bnx2fc_rport *tgt;
  1038. u32 conn_id;
  1039. conn_id = disable_kcqe->fcoe_conn_id;
  1040. tgt = hba->tgt_ofld_list[conn_id];
  1041. if (!tgt) {
  1042. printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
  1043. return;
  1044. }
  1045. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  1046. if (disable_kcqe->completion_status) {
  1047. printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
  1048. disable_kcqe->completion_status);
  1049. set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags);
  1050. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1051. wake_up_interruptible(&tgt->upld_wait);
  1052. } else {
  1053. /* disable successful */
  1054. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  1055. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  1056. clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags);
  1057. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1058. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1059. wake_up_interruptible(&tgt->upld_wait);
  1060. }
  1061. }
  1062. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  1063. struct fcoe_kcqe *destroy_kcqe)
  1064. {
  1065. struct bnx2fc_rport *tgt;
  1066. u32 conn_id;
  1067. conn_id = destroy_kcqe->fcoe_conn_id;
  1068. tgt = hba->tgt_ofld_list[conn_id];
  1069. if (!tgt) {
  1070. printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
  1071. return;
  1072. }
  1073. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  1074. if (destroy_kcqe->completion_status) {
  1075. printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
  1076. destroy_kcqe->completion_status);
  1077. return;
  1078. } else {
  1079. /* destroy successful */
  1080. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  1081. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1082. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  1083. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1084. wake_up_interruptible(&tgt->upld_wait);
  1085. }
  1086. }
  1087. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  1088. {
  1089. switch (err_code) {
  1090. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  1091. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  1092. break;
  1093. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  1094. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  1095. break;
  1096. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  1097. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  1098. break;
  1099. case FCOE_KCQE_COMPLETION_STATUS_ERROR:
  1100. printk(KERN_ERR PFX "init failure due to compl status err\n");
  1101. break;
  1102. case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
  1103. printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
  1104. break;
  1105. default:
  1106. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  1107. }
  1108. }
  1109. /**
  1110. * bnx2fc_indicae_kcqe - process KCQE
  1111. *
  1112. * @hba: adapter structure pointer
  1113. * @kcqe: kcqe pointer
  1114. * @num_cqe: Number of completion queue elements
  1115. *
  1116. * Generic KCQ event handler
  1117. */
  1118. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  1119. u32 num_cqe)
  1120. {
  1121. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1122. int i = 0;
  1123. struct fcoe_kcqe *kcqe = NULL;
  1124. while (i < num_cqe) {
  1125. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1126. switch (kcqe->op_code) {
  1127. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1128. bnx2fc_fastpath_notification(hba, kcqe);
  1129. break;
  1130. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1131. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1132. break;
  1133. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1134. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1135. break;
  1136. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1137. if (kcqe->completion_status !=
  1138. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1139. bnx2fc_init_failure(hba,
  1140. kcqe->completion_status);
  1141. } else {
  1142. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1143. bnx2fc_get_link_state(hba);
  1144. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1145. (u8)hba->pcidev->bus->number);
  1146. }
  1147. break;
  1148. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1149. if (kcqe->completion_status !=
  1150. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1151. printk(KERN_ERR PFX "DESTROY failed\n");
  1152. } else {
  1153. printk(KERN_ERR PFX "DESTROY success\n");
  1154. }
  1155. set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
  1156. wake_up_interruptible(&hba->destroy_wait);
  1157. break;
  1158. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1159. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1160. break;
  1161. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1162. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1163. break;
  1164. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1165. if (kcqe->completion_status !=
  1166. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1167. printk(KERN_ERR PFX "STAT failed\n");
  1168. complete(&hba->stat_req_done);
  1169. break;
  1170. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1171. /* fall thru */
  1172. default:
  1173. printk(KERN_ERR PFX "unknown opcode 0x%x\n",
  1174. kcqe->op_code);
  1175. }
  1176. }
  1177. }
  1178. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1179. {
  1180. struct fcoe_sqe *sqe;
  1181. sqe = &tgt->sq[tgt->sq_prod_idx];
  1182. /* Fill SQ WQE */
  1183. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1184. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1185. /* Advance SQ Prod Idx */
  1186. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1187. tgt->sq_prod_idx = 0;
  1188. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1189. }
  1190. }
  1191. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1192. {
  1193. struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
  1194. u32 msg;
  1195. wmb();
  1196. sq_db->prod = tgt->sq_prod_idx |
  1197. (tgt->sq_curr_toggle_bit << 15);
  1198. msg = *((u32 *)sq_db);
  1199. writel(cpu_to_le32(msg), tgt->ctx_base);
  1200. mmiowb();
  1201. }
  1202. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1203. {
  1204. u32 context_id = tgt->context_id;
  1205. struct fcoe_port *port = tgt->port;
  1206. u32 reg_off;
  1207. resource_size_t reg_base;
  1208. struct bnx2fc_interface *interface = port->priv;
  1209. struct bnx2fc_hba *hba = interface->hba;
  1210. reg_base = pci_resource_start(hba->pcidev,
  1211. BNX2X_DOORBELL_PCI_BAR);
  1212. reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF);
  1213. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1214. if (!tgt->ctx_base)
  1215. return -ENOMEM;
  1216. return 0;
  1217. }
  1218. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1219. {
  1220. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1221. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1222. return NULL;
  1223. tgt->rq_cons_idx += num_items;
  1224. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1225. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1226. return buf;
  1227. }
  1228. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1229. {
  1230. /* return the rq buffer */
  1231. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1232. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1233. /* Wrap around RQ */
  1234. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1235. }
  1236. tgt->rq_prod_idx = next_prod_idx;
  1237. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1238. }
  1239. void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
  1240. struct fcoe_task_ctx_entry *task,
  1241. struct bnx2fc_cmd *orig_io_req,
  1242. u32 offset)
  1243. {
  1244. struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
  1245. struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
  1246. struct bnx2fc_interface *interface = tgt->port->priv;
  1247. struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
  1248. struct fcoe_task_ctx_entry *orig_task;
  1249. struct fcoe_task_ctx_entry *task_page;
  1250. struct fcoe_ext_mul_sges_ctx *sgl;
  1251. u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
  1252. u8 orig_task_type;
  1253. u16 orig_xid = orig_io_req->xid;
  1254. u32 context_id = tgt->context_id;
  1255. u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
  1256. u32 orig_offset = offset;
  1257. int bd_count;
  1258. int orig_task_idx, index;
  1259. int i;
  1260. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1261. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1262. orig_task_type = FCOE_TASK_TYPE_WRITE;
  1263. else
  1264. orig_task_type = FCOE_TASK_TYPE_READ;
  1265. /* Tx flags */
  1266. task->txwr_rxrd.const_ctx.tx_flags =
  1267. FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
  1268. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1269. /* init flags */
  1270. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1271. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1272. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1273. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1274. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1275. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1276. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1277. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1278. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1279. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
  1280. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
  1281. bd_count = orig_io_req->bd_tbl->bd_valid;
  1282. /* obtain the appropriate bd entry from relative offset */
  1283. for (i = 0; i < bd_count; i++) {
  1284. if (offset < bd[i].buf_len)
  1285. break;
  1286. offset -= bd[i].buf_len;
  1287. }
  1288. phys_addr += (i * sizeof(struct fcoe_bd_ctx));
  1289. if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
  1290. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1291. (u32)phys_addr;
  1292. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1293. (u32)((u64)phys_addr >> 32);
  1294. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1295. bd_count;
  1296. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
  1297. offset; /* adjusted offset */
  1298. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
  1299. } else {
  1300. orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE;
  1301. index = orig_xid % BNX2FC_TASKS_PER_PAGE;
  1302. task_page = (struct fcoe_task_ctx_entry *)
  1303. interface->hba->task_ctx[orig_task_idx];
  1304. orig_task = &(task_page[index]);
  1305. /* Multiple SGEs were used for this IO */
  1306. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1307. sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
  1308. sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
  1309. sgl->mul_sgl.sgl_size = bd_count;
  1310. sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
  1311. sgl->mul_sgl.cur_sge_idx = i;
  1312. memset(&task->rxwr_only.rx_seq_ctx, 0,
  1313. sizeof(struct fcoe_rx_seq_ctx));
  1314. task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
  1315. task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
  1316. }
  1317. }
  1318. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1319. struct fcoe_task_ctx_entry *task,
  1320. u16 orig_xid)
  1321. {
  1322. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1323. struct bnx2fc_rport *tgt = io_req->tgt;
  1324. u32 context_id = tgt->context_id;
  1325. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1326. /* Tx Write Rx Read */
  1327. /* init flags */
  1328. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1329. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1330. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1331. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1332. if (tgt->dev_type == TYPE_TAPE)
  1333. task->txwr_rxrd.const_ctx.init_flags |=
  1334. FCOE_TASK_DEV_TYPE_TAPE <<
  1335. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1336. else
  1337. task->txwr_rxrd.const_ctx.init_flags |=
  1338. FCOE_TASK_DEV_TYPE_DISK <<
  1339. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1340. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1341. /* Tx flags */
  1342. task->txwr_rxrd.const_ctx.tx_flags =
  1343. FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1344. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1345. /* Rx Read Tx Write */
  1346. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1347. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1348. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1349. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1350. }
  1351. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1352. struct fcoe_task_ctx_entry *task)
  1353. {
  1354. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1355. struct bnx2fc_rport *tgt = io_req->tgt;
  1356. struct fc_frame_header *fc_hdr;
  1357. struct fcoe_ext_mul_sges_ctx *sgl;
  1358. u8 task_type = 0;
  1359. u64 *hdr;
  1360. u64 temp_hdr[3];
  1361. u32 context_id;
  1362. /* Obtain task_type */
  1363. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1364. (io_req->cmd_type == BNX2FC_ELS)) {
  1365. task_type = FCOE_TASK_TYPE_MIDPATH;
  1366. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1367. task_type = FCOE_TASK_TYPE_ABTS;
  1368. }
  1369. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1370. /* Setup the task from io_req for easy reference */
  1371. io_req->task = task;
  1372. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1373. io_req->cmd_type, task_type);
  1374. /* Tx only */
  1375. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1376. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1377. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1378. (u32)mp_req->mp_req_bd_dma;
  1379. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1380. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1381. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
  1382. }
  1383. /* Tx Write Rx Read */
  1384. /* init flags */
  1385. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1386. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1387. if (tgt->dev_type == TYPE_TAPE)
  1388. task->txwr_rxrd.const_ctx.init_flags |=
  1389. FCOE_TASK_DEV_TYPE_TAPE <<
  1390. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1391. else
  1392. task->txwr_rxrd.const_ctx.init_flags |=
  1393. FCOE_TASK_DEV_TYPE_DISK <<
  1394. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1395. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1396. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1397. /* tx flags */
  1398. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1399. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1400. /* Rx Write Tx Read */
  1401. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1402. /* rx flags */
  1403. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1404. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1405. context_id = tgt->context_id;
  1406. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1407. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1408. fc_hdr = &(mp_req->req_fc_hdr);
  1409. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1410. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1411. fc_hdr->fh_rx_id = htons(0xffff);
  1412. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1413. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1414. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1415. }
  1416. /* Fill FC Header into middle path buffer */
  1417. hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
  1418. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1419. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1420. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1421. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1422. /* Rx Only */
  1423. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1424. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1425. sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
  1426. sgl->mul_sgl.cur_sge_addr.hi =
  1427. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1428. sgl->mul_sgl.sgl_size = 1;
  1429. }
  1430. }
  1431. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1432. struct fcoe_task_ctx_entry *task)
  1433. {
  1434. u8 task_type;
  1435. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1436. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1437. struct bnx2fc_rport *tgt = io_req->tgt;
  1438. struct fcoe_cached_sge_ctx *cached_sge;
  1439. struct fcoe_ext_mul_sges_ctx *sgl;
  1440. int dev_type = tgt->dev_type;
  1441. u64 *fcp_cmnd;
  1442. u64 tmp_fcp_cmnd[4];
  1443. u32 context_id;
  1444. int cnt, i;
  1445. int bd_count;
  1446. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1447. /* Setup the task from io_req for easy reference */
  1448. io_req->task = task;
  1449. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1450. task_type = FCOE_TASK_TYPE_WRITE;
  1451. else
  1452. task_type = FCOE_TASK_TYPE_READ;
  1453. /* Tx only */
  1454. bd_count = bd_tbl->bd_valid;
  1455. cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
  1456. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1457. if ((dev_type == TYPE_DISK) && (bd_count == 1)) {
  1458. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1459. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo =
  1460. cached_sge->cur_buf_addr.lo =
  1461. fcoe_bd_tbl->buf_addr_lo;
  1462. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi =
  1463. cached_sge->cur_buf_addr.hi =
  1464. fcoe_bd_tbl->buf_addr_hi;
  1465. task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem =
  1466. cached_sge->cur_buf_rem =
  1467. fcoe_bd_tbl->buf_len;
  1468. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1469. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1470. } else {
  1471. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1472. (u32)bd_tbl->bd_tbl_dma;
  1473. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1474. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1475. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1476. bd_tbl->bd_valid;
  1477. }
  1478. }
  1479. /*Tx Write Rx Read */
  1480. /* Init state to NORMAL */
  1481. task->txwr_rxrd.const_ctx.init_flags |= task_type <<
  1482. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1483. if (dev_type == TYPE_TAPE) {
  1484. task->txwr_rxrd.const_ctx.init_flags |=
  1485. FCOE_TASK_DEV_TYPE_TAPE <<
  1486. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1487. io_req->rec_retry = 0;
  1488. io_req->rec_retry = 0;
  1489. } else
  1490. task->txwr_rxrd.const_ctx.init_flags |=
  1491. FCOE_TASK_DEV_TYPE_DISK <<
  1492. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1493. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1494. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1495. /* tx flags */
  1496. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1497. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1498. /* Set initial seq counter */
  1499. task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
  1500. /* Fill FCP_CMND IU */
  1501. fcp_cmnd = (u64 *)
  1502. task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
  1503. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1504. /* swap fcp_cmnd */
  1505. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1506. for (i = 0; i < cnt; i++) {
  1507. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1508. fcp_cmnd++;
  1509. }
  1510. /* Rx Write Tx Read */
  1511. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1512. context_id = tgt->context_id;
  1513. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1514. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1515. /* rx flags */
  1516. /* Set state to "waiting for the first packet" */
  1517. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1518. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1519. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1520. /* Rx Only */
  1521. if (task_type != FCOE_TASK_TYPE_READ)
  1522. return;
  1523. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1524. bd_count = bd_tbl->bd_valid;
  1525. if (dev_type == TYPE_DISK) {
  1526. if (bd_count == 1) {
  1527. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1528. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1529. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1530. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1531. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1532. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1533. } else if (bd_count == 2) {
  1534. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1535. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1536. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1537. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1538. fcoe_bd_tbl++;
  1539. cached_sge->second_buf_addr.lo =
  1540. fcoe_bd_tbl->buf_addr_lo;
  1541. cached_sge->second_buf_addr.hi =
  1542. fcoe_bd_tbl->buf_addr_hi;
  1543. cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
  1544. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1545. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1546. } else {
  1547. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1548. sgl->mul_sgl.cur_sge_addr.hi =
  1549. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1550. sgl->mul_sgl.sgl_size = bd_count;
  1551. }
  1552. } else {
  1553. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1554. sgl->mul_sgl.cur_sge_addr.hi =
  1555. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1556. sgl->mul_sgl.sgl_size = bd_count;
  1557. }
  1558. }
  1559. /**
  1560. * bnx2fc_setup_task_ctx - allocate and map task context
  1561. *
  1562. * @hba: pointer to adapter structure
  1563. *
  1564. * allocate memory for task context, and associated BD table to be used
  1565. * by firmware
  1566. *
  1567. */
  1568. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1569. {
  1570. int rc = 0;
  1571. struct regpair *task_ctx_bdt;
  1572. dma_addr_t addr;
  1573. int task_ctx_arr_sz;
  1574. int i;
  1575. /*
  1576. * Allocate task context bd table. A page size of bd table
  1577. * can map 256 buffers. Each buffer contains 32 task context
  1578. * entries. Hence the limit with one page is 8192 task context
  1579. * entries.
  1580. */
  1581. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1582. PAGE_SIZE,
  1583. &hba->task_ctx_bd_dma,
  1584. GFP_KERNEL);
  1585. if (!hba->task_ctx_bd_tbl) {
  1586. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1587. rc = -1;
  1588. goto out;
  1589. }
  1590. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1591. /*
  1592. * Allocate task_ctx which is an array of pointers pointing to
  1593. * a page containing 32 task contexts
  1594. */
  1595. task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
  1596. hba->task_ctx = kzalloc((task_ctx_arr_sz * sizeof(void *)),
  1597. GFP_KERNEL);
  1598. if (!hba->task_ctx) {
  1599. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1600. rc = -1;
  1601. goto out1;
  1602. }
  1603. /*
  1604. * Allocate task_ctx_dma which is an array of dma addresses
  1605. */
  1606. hba->task_ctx_dma = kmalloc((task_ctx_arr_sz *
  1607. sizeof(dma_addr_t)), GFP_KERNEL);
  1608. if (!hba->task_ctx_dma) {
  1609. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1610. rc = -1;
  1611. goto out2;
  1612. }
  1613. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1614. for (i = 0; i < task_ctx_arr_sz; i++) {
  1615. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1616. PAGE_SIZE,
  1617. &hba->task_ctx_dma[i],
  1618. GFP_KERNEL);
  1619. if (!hba->task_ctx[i]) {
  1620. printk(KERN_ERR PFX "unable to alloc task context\n");
  1621. rc = -1;
  1622. goto out3;
  1623. }
  1624. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1625. addr = (u64)hba->task_ctx_dma[i];
  1626. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1627. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1628. task_ctx_bdt++;
  1629. }
  1630. return 0;
  1631. out3:
  1632. for (i = 0; i < task_ctx_arr_sz; i++) {
  1633. if (hba->task_ctx[i]) {
  1634. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1635. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1636. hba->task_ctx[i] = NULL;
  1637. }
  1638. }
  1639. kfree(hba->task_ctx_dma);
  1640. hba->task_ctx_dma = NULL;
  1641. out2:
  1642. kfree(hba->task_ctx);
  1643. hba->task_ctx = NULL;
  1644. out1:
  1645. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1646. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1647. hba->task_ctx_bd_tbl = NULL;
  1648. out:
  1649. return rc;
  1650. }
  1651. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1652. {
  1653. int task_ctx_arr_sz;
  1654. int i;
  1655. if (hba->task_ctx_bd_tbl) {
  1656. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1657. hba->task_ctx_bd_tbl,
  1658. hba->task_ctx_bd_dma);
  1659. hba->task_ctx_bd_tbl = NULL;
  1660. }
  1661. task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE);
  1662. if (hba->task_ctx) {
  1663. for (i = 0; i < task_ctx_arr_sz; i++) {
  1664. if (hba->task_ctx[i]) {
  1665. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1666. hba->task_ctx[i],
  1667. hba->task_ctx_dma[i]);
  1668. hba->task_ctx[i] = NULL;
  1669. }
  1670. }
  1671. kfree(hba->task_ctx);
  1672. hba->task_ctx = NULL;
  1673. }
  1674. kfree(hba->task_ctx_dma);
  1675. hba->task_ctx_dma = NULL;
  1676. }
  1677. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1678. {
  1679. int i;
  1680. int segment_count;
  1681. u32 *pbl;
  1682. if (hba->hash_tbl_segments) {
  1683. pbl = hba->hash_tbl_pbl;
  1684. if (pbl) {
  1685. segment_count = hba->hash_tbl_segment_count;
  1686. for (i = 0; i < segment_count; ++i) {
  1687. dma_addr_t dma_address;
  1688. dma_address = le32_to_cpu(*pbl);
  1689. ++pbl;
  1690. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1691. ++pbl;
  1692. dma_free_coherent(&hba->pcidev->dev,
  1693. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1694. hba->hash_tbl_segments[i],
  1695. dma_address);
  1696. }
  1697. }
  1698. kfree(hba->hash_tbl_segments);
  1699. hba->hash_tbl_segments = NULL;
  1700. }
  1701. if (hba->hash_tbl_pbl) {
  1702. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1703. hba->hash_tbl_pbl,
  1704. hba->hash_tbl_pbl_dma);
  1705. hba->hash_tbl_pbl = NULL;
  1706. }
  1707. }
  1708. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1709. {
  1710. int i;
  1711. int hash_table_size;
  1712. int segment_count;
  1713. int segment_array_size;
  1714. int dma_segment_array_size;
  1715. dma_addr_t *dma_segment_array;
  1716. u32 *pbl;
  1717. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1718. sizeof(struct fcoe_hash_table_entry);
  1719. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1720. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1721. hba->hash_tbl_segment_count = segment_count;
  1722. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1723. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1724. if (!hba->hash_tbl_segments) {
  1725. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1726. return -ENOMEM;
  1727. }
  1728. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1729. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1730. if (!dma_segment_array) {
  1731. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1732. goto cleanup_ht;
  1733. }
  1734. for (i = 0; i < segment_count; ++i) {
  1735. hba->hash_tbl_segments[i] =
  1736. dma_alloc_coherent(&hba->pcidev->dev,
  1737. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1738. &dma_segment_array[i],
  1739. GFP_KERNEL);
  1740. if (!hba->hash_tbl_segments[i]) {
  1741. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1742. goto cleanup_dma;
  1743. }
  1744. memset(hba->hash_tbl_segments[i], 0,
  1745. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1746. }
  1747. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1748. PAGE_SIZE,
  1749. &hba->hash_tbl_pbl_dma,
  1750. GFP_KERNEL);
  1751. if (!hba->hash_tbl_pbl) {
  1752. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1753. goto cleanup_dma;
  1754. }
  1755. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1756. pbl = hba->hash_tbl_pbl;
  1757. for (i = 0; i < segment_count; ++i) {
  1758. u64 paddr = dma_segment_array[i];
  1759. *pbl = cpu_to_le32((u32) paddr);
  1760. ++pbl;
  1761. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1762. ++pbl;
  1763. }
  1764. pbl = hba->hash_tbl_pbl;
  1765. i = 0;
  1766. while (*pbl && *(pbl + 1)) {
  1767. u32 lo;
  1768. u32 hi;
  1769. lo = *pbl;
  1770. ++pbl;
  1771. hi = *pbl;
  1772. ++pbl;
  1773. ++i;
  1774. }
  1775. kfree(dma_segment_array);
  1776. return 0;
  1777. cleanup_dma:
  1778. for (i = 0; i < segment_count; ++i) {
  1779. if (hba->hash_tbl_segments[i])
  1780. dma_free_coherent(&hba->pcidev->dev,
  1781. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1782. hba->hash_tbl_segments[i],
  1783. dma_segment_array[i]);
  1784. }
  1785. kfree(dma_segment_array);
  1786. cleanup_ht:
  1787. kfree(hba->hash_tbl_segments);
  1788. hba->hash_tbl_segments = NULL;
  1789. return -ENOMEM;
  1790. }
  1791. /**
  1792. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1793. *
  1794. * @hba: Pointer to adapter structure
  1795. *
  1796. */
  1797. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1798. {
  1799. u64 addr;
  1800. u32 mem_size;
  1801. int i;
  1802. if (bnx2fc_allocate_hash_table(hba))
  1803. return -ENOMEM;
  1804. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1805. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1806. &hba->t2_hash_tbl_ptr_dma,
  1807. GFP_KERNEL);
  1808. if (!hba->t2_hash_tbl_ptr) {
  1809. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1810. bnx2fc_free_fw_resc(hba);
  1811. return -ENOMEM;
  1812. }
  1813. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1814. mem_size = BNX2FC_NUM_MAX_SESS *
  1815. sizeof(struct fcoe_t2_hash_table_entry);
  1816. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1817. &hba->t2_hash_tbl_dma,
  1818. GFP_KERNEL);
  1819. if (!hba->t2_hash_tbl) {
  1820. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1821. bnx2fc_free_fw_resc(hba);
  1822. return -ENOMEM;
  1823. }
  1824. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1825. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1826. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1827. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1828. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1829. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1830. }
  1831. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1832. PAGE_SIZE, &hba->dummy_buf_dma,
  1833. GFP_KERNEL);
  1834. if (!hba->dummy_buffer) {
  1835. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1836. bnx2fc_free_fw_resc(hba);
  1837. return -ENOMEM;
  1838. }
  1839. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1840. PAGE_SIZE,
  1841. &hba->stats_buf_dma,
  1842. GFP_KERNEL);
  1843. if (!hba->stats_buffer) {
  1844. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1845. bnx2fc_free_fw_resc(hba);
  1846. return -ENOMEM;
  1847. }
  1848. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1849. return 0;
  1850. }
  1851. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1852. {
  1853. u32 mem_size;
  1854. if (hba->stats_buffer) {
  1855. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1856. hba->stats_buffer, hba->stats_buf_dma);
  1857. hba->stats_buffer = NULL;
  1858. }
  1859. if (hba->dummy_buffer) {
  1860. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1861. hba->dummy_buffer, hba->dummy_buf_dma);
  1862. hba->dummy_buffer = NULL;
  1863. }
  1864. if (hba->t2_hash_tbl_ptr) {
  1865. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1866. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1867. hba->t2_hash_tbl_ptr,
  1868. hba->t2_hash_tbl_ptr_dma);
  1869. hba->t2_hash_tbl_ptr = NULL;
  1870. }
  1871. if (hba->t2_hash_tbl) {
  1872. mem_size = BNX2FC_NUM_MAX_SESS *
  1873. sizeof(struct fcoe_t2_hash_table_entry);
  1874. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1875. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1876. hba->t2_hash_tbl = NULL;
  1877. }
  1878. bnx2fc_free_hash_table(hba);
  1879. }