arcmsr_hba.c 125 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Nick Cheng, C.L. Huang
  6. ** Description: SCSI RAID Device Driver for Areca RAID Controller
  7. *******************************************************************************
  8. ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
  9. **
  10. ** Web site: www.areca.com.tw
  11. ** E-mail: support@areca.com.tw
  12. **
  13. ** This program is free software; you can redistribute it and/or modify
  14. ** it under the terms of the GNU General Public License version 2 as
  15. ** published by the Free Software Foundation.
  16. ** This program is distributed in the hope that it will be useful,
  17. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. ** GNU General Public License for more details.
  20. *******************************************************************************
  21. ** Redistribution and use in source and binary forms, with or without
  22. ** modification, are permitted provided that the following conditions
  23. ** are met:
  24. ** 1. Redistributions of source code must retain the above copyright
  25. ** notice, this list of conditions and the following disclaimer.
  26. ** 2. Redistributions in binary form must reproduce the above copyright
  27. ** notice, this list of conditions and the following disclaimer in the
  28. ** documentation and/or other materials provided with the distribution.
  29. ** 3. The name of the author may not be used to endorse or promote products
  30. ** derived from this software without specific prior written permission.
  31. **
  32. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  33. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  34. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  35. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  36. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  37. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  39. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  41. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *******************************************************************************
  43. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  44. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  45. *******************************************************************************
  46. */
  47. #include <linux/module.h>
  48. #include <linux/reboot.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/pci_ids.h>
  51. #include <linux/interrupt.h>
  52. #include <linux/moduleparam.h>
  53. #include <linux/errno.h>
  54. #include <linux/types.h>
  55. #include <linux/delay.h>
  56. #include <linux/dma-mapping.h>
  57. #include <linux/timer.h>
  58. #include <linux/slab.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <linux/circ_buf.h>
  62. #include <asm/dma.h>
  63. #include <asm/io.h>
  64. #include <asm/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
  74. MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. #define ARCMSR_SLEEPTIME 10
  78. #define ARCMSR_RETRYCOUNT 12
  79. static wait_queue_head_t wait_q;
  80. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  81. struct scsi_cmnd *cmd);
  82. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  83. static int arcmsr_abort(struct scsi_cmnd *);
  84. static int arcmsr_bus_reset(struct scsi_cmnd *);
  85. static int arcmsr_bios_param(struct scsi_device *sdev,
  86. struct block_device *bdev, sector_t capacity, int *info);
  87. static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  88. static int arcmsr_probe(struct pci_dev *pdev,
  89. const struct pci_device_id *id);
  90. static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
  91. static int arcmsr_resume(struct pci_dev *pdev);
  92. static void arcmsr_remove(struct pci_dev *pdev);
  93. static void arcmsr_shutdown(struct pci_dev *pdev);
  94. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  95. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  96. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  97. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  98. u32 intmask_org);
  99. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  100. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
  101. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
  102. static void arcmsr_request_device_map(unsigned long pacb);
  103. static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb);
  104. static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb);
  105. static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb);
  106. static void arcmsr_message_isr_bh_fn(struct work_struct *work);
  107. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
  108. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
  109. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
  110. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
  111. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
  112. static const char *arcmsr_info(struct Scsi_Host *);
  113. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  114. static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
  115. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
  116. {
  117. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  118. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  119. return scsi_change_queue_depth(sdev, queue_depth);
  120. }
  121. static struct scsi_host_template arcmsr_scsi_host_template = {
  122. .module = THIS_MODULE,
  123. .name = "Areca SAS/SATA RAID driver",
  124. .info = arcmsr_info,
  125. .queuecommand = arcmsr_queue_command,
  126. .eh_abort_handler = arcmsr_abort,
  127. .eh_bus_reset_handler = arcmsr_bus_reset,
  128. .bios_param = arcmsr_bios_param,
  129. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  130. .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
  131. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  132. .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
  133. .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
  134. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  135. .use_clustering = ENABLE_CLUSTERING,
  136. .shost_attrs = arcmsr_host_attrs,
  137. .no_write_same = 1,
  138. };
  139. static struct pci_device_id arcmsr_device_id_table[] = {
  140. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
  141. .driver_data = ACB_ADAPTER_TYPE_A},
  142. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
  143. .driver_data = ACB_ADAPTER_TYPE_A},
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
  145. .driver_data = ACB_ADAPTER_TYPE_A},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
  147. .driver_data = ACB_ADAPTER_TYPE_A},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
  149. .driver_data = ACB_ADAPTER_TYPE_A},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
  151. .driver_data = ACB_ADAPTER_TYPE_B},
  152. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
  153. .driver_data = ACB_ADAPTER_TYPE_B},
  154. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
  155. .driver_data = ACB_ADAPTER_TYPE_B},
  156. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
  157. .driver_data = ACB_ADAPTER_TYPE_A},
  158. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
  159. .driver_data = ACB_ADAPTER_TYPE_D},
  160. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
  161. .driver_data = ACB_ADAPTER_TYPE_A},
  162. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
  163. .driver_data = ACB_ADAPTER_TYPE_A},
  164. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
  165. .driver_data = ACB_ADAPTER_TYPE_A},
  166. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
  167. .driver_data = ACB_ADAPTER_TYPE_A},
  168. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
  169. .driver_data = ACB_ADAPTER_TYPE_A},
  170. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
  171. .driver_data = ACB_ADAPTER_TYPE_A},
  172. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
  173. .driver_data = ACB_ADAPTER_TYPE_A},
  174. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
  175. .driver_data = ACB_ADAPTER_TYPE_A},
  176. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
  177. .driver_data = ACB_ADAPTER_TYPE_A},
  178. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
  179. .driver_data = ACB_ADAPTER_TYPE_C},
  180. {0, 0}, /* Terminating entry */
  181. };
  182. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  183. static struct pci_driver arcmsr_pci_driver = {
  184. .name = "arcmsr",
  185. .id_table = arcmsr_device_id_table,
  186. .probe = arcmsr_probe,
  187. .remove = arcmsr_remove,
  188. .suspend = arcmsr_suspend,
  189. .resume = arcmsr_resume,
  190. .shutdown = arcmsr_shutdown,
  191. };
  192. /*
  193. ****************************************************************************
  194. ****************************************************************************
  195. */
  196. static void arcmsr_free_mu(struct AdapterControlBlock *acb)
  197. {
  198. switch (acb->adapter_type) {
  199. case ACB_ADAPTER_TYPE_B:
  200. case ACB_ADAPTER_TYPE_D: {
  201. dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
  202. acb->dma_coherent2, acb->dma_coherent_handle2);
  203. break;
  204. }
  205. }
  206. }
  207. static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
  208. {
  209. struct pci_dev *pdev = acb->pdev;
  210. switch (acb->adapter_type){
  211. case ACB_ADAPTER_TYPE_A:{
  212. acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
  213. if (!acb->pmuA) {
  214. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  215. return false;
  216. }
  217. break;
  218. }
  219. case ACB_ADAPTER_TYPE_B:{
  220. void __iomem *mem_base0, *mem_base1;
  221. mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  222. if (!mem_base0) {
  223. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  224. return false;
  225. }
  226. mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
  227. if (!mem_base1) {
  228. iounmap(mem_base0);
  229. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  230. return false;
  231. }
  232. acb->mem_base0 = mem_base0;
  233. acb->mem_base1 = mem_base1;
  234. break;
  235. }
  236. case ACB_ADAPTER_TYPE_C:{
  237. acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
  238. if (!acb->pmuC) {
  239. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  240. return false;
  241. }
  242. if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  243. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
  244. return true;
  245. }
  246. break;
  247. }
  248. case ACB_ADAPTER_TYPE_D: {
  249. void __iomem *mem_base0;
  250. unsigned long addr, range, flags;
  251. addr = (unsigned long)pci_resource_start(pdev, 0);
  252. range = pci_resource_len(pdev, 0);
  253. flags = pci_resource_flags(pdev, 0);
  254. if (flags & IORESOURCE_CACHEABLE)
  255. mem_base0 = ioremap(addr, range);
  256. else
  257. mem_base0 = ioremap_nocache(addr, range);
  258. if (!mem_base0) {
  259. pr_notice("arcmsr%d: memory mapping region fail\n",
  260. acb->host->host_no);
  261. return false;
  262. }
  263. acb->mem_base0 = mem_base0;
  264. break;
  265. }
  266. }
  267. return true;
  268. }
  269. static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
  270. {
  271. switch (acb->adapter_type) {
  272. case ACB_ADAPTER_TYPE_A:{
  273. iounmap(acb->pmuA);
  274. }
  275. break;
  276. case ACB_ADAPTER_TYPE_B:{
  277. iounmap(acb->mem_base0);
  278. iounmap(acb->mem_base1);
  279. }
  280. break;
  281. case ACB_ADAPTER_TYPE_C:{
  282. iounmap(acb->pmuC);
  283. }
  284. break;
  285. case ACB_ADAPTER_TYPE_D:
  286. iounmap(acb->mem_base0);
  287. break;
  288. }
  289. }
  290. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  291. {
  292. irqreturn_t handle_state;
  293. struct AdapterControlBlock *acb = dev_id;
  294. handle_state = arcmsr_interrupt(acb);
  295. return handle_state;
  296. }
  297. static int arcmsr_bios_param(struct scsi_device *sdev,
  298. struct block_device *bdev, sector_t capacity, int *geom)
  299. {
  300. int ret, heads, sectors, cylinders, total_capacity;
  301. unsigned char *buffer;/* return copy of block device's partition table */
  302. buffer = scsi_bios_ptable(bdev);
  303. if (buffer) {
  304. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  305. kfree(buffer);
  306. if (ret != -1)
  307. return ret;
  308. }
  309. total_capacity = capacity;
  310. heads = 64;
  311. sectors = 32;
  312. cylinders = total_capacity / (heads * sectors);
  313. if (cylinders > 1024) {
  314. heads = 255;
  315. sectors = 63;
  316. cylinders = total_capacity / (heads * sectors);
  317. }
  318. geom[0] = heads;
  319. geom[1] = sectors;
  320. geom[2] = cylinders;
  321. return 0;
  322. }
  323. static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
  324. {
  325. struct MessageUnit_A __iomem *reg = acb->pmuA;
  326. int i;
  327. for (i = 0; i < 2000; i++) {
  328. if (readl(&reg->outbound_intstatus) &
  329. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  330. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  331. &reg->outbound_intstatus);
  332. return true;
  333. }
  334. msleep(10);
  335. } /* max 20 seconds */
  336. return false;
  337. }
  338. static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
  339. {
  340. struct MessageUnit_B *reg = acb->pmuB;
  341. int i;
  342. for (i = 0; i < 2000; i++) {
  343. if (readl(reg->iop2drv_doorbell)
  344. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  345. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
  346. reg->iop2drv_doorbell);
  347. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
  348. reg->drv2iop_doorbell);
  349. return true;
  350. }
  351. msleep(10);
  352. } /* max 20 seconds */
  353. return false;
  354. }
  355. static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
  356. {
  357. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  358. int i;
  359. for (i = 0; i < 2000; i++) {
  360. if (readl(&phbcmu->outbound_doorbell)
  361. & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  362. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
  363. &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
  364. return true;
  365. }
  366. msleep(10);
  367. } /* max 20 seconds */
  368. return false;
  369. }
  370. static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
  371. {
  372. struct MessageUnit_D *reg = pACB->pmuD;
  373. int i;
  374. for (i = 0; i < 2000; i++) {
  375. if (readl(reg->outbound_doorbell)
  376. & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  377. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  378. reg->outbound_doorbell);
  379. return true;
  380. }
  381. msleep(10);
  382. } /* max 20 seconds */
  383. return false;
  384. }
  385. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
  386. {
  387. struct MessageUnit_A __iomem *reg = acb->pmuA;
  388. int retry_count = 30;
  389. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  390. do {
  391. if (arcmsr_hbaA_wait_msgint_ready(acb))
  392. break;
  393. else {
  394. retry_count--;
  395. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  396. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  397. }
  398. } while (retry_count != 0);
  399. }
  400. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
  401. {
  402. struct MessageUnit_B *reg = acb->pmuB;
  403. int retry_count = 30;
  404. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
  405. do {
  406. if (arcmsr_hbaB_wait_msgint_ready(acb))
  407. break;
  408. else {
  409. retry_count--;
  410. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  411. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  412. }
  413. } while (retry_count != 0);
  414. }
  415. static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
  416. {
  417. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  418. int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
  419. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  420. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  421. do {
  422. if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
  423. break;
  424. } else {
  425. retry_count--;
  426. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  427. timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
  428. }
  429. } while (retry_count != 0);
  430. return;
  431. }
  432. static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
  433. {
  434. int retry_count = 15;
  435. struct MessageUnit_D *reg = pACB->pmuD;
  436. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
  437. do {
  438. if (arcmsr_hbaD_wait_msgint_ready(pACB))
  439. break;
  440. retry_count--;
  441. pr_notice("arcmsr%d: wait 'flush adapter "
  442. "cache' timeout, retry count down = %d\n",
  443. pACB->host->host_no, retry_count);
  444. } while (retry_count != 0);
  445. }
  446. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  447. {
  448. switch (acb->adapter_type) {
  449. case ACB_ADAPTER_TYPE_A: {
  450. arcmsr_hbaA_flush_cache(acb);
  451. }
  452. break;
  453. case ACB_ADAPTER_TYPE_B: {
  454. arcmsr_hbaB_flush_cache(acb);
  455. }
  456. break;
  457. case ACB_ADAPTER_TYPE_C: {
  458. arcmsr_hbaC_flush_cache(acb);
  459. }
  460. break;
  461. case ACB_ADAPTER_TYPE_D:
  462. arcmsr_hbaD_flush_cache(acb);
  463. break;
  464. }
  465. }
  466. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  467. {
  468. struct pci_dev *pdev = acb->pdev;
  469. void *dma_coherent;
  470. dma_addr_t dma_coherent_handle;
  471. struct CommandControlBlock *ccb_tmp;
  472. int i = 0, j = 0;
  473. dma_addr_t cdb_phyaddr;
  474. unsigned long roundup_ccbsize;
  475. unsigned long max_xfer_len;
  476. unsigned long max_sg_entrys;
  477. uint32_t firm_config_version;
  478. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  479. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  480. acb->devstate[i][j] = ARECA_RAID_GONE;
  481. max_xfer_len = ARCMSR_MAX_XFER_LEN;
  482. max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
  483. firm_config_version = acb->firm_cfg_version;
  484. if((firm_config_version & 0xFF) >= 3){
  485. max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
  486. max_sg_entrys = (max_xfer_len/4096);
  487. }
  488. acb->host->max_sectors = max_xfer_len/512;
  489. acb->host->sg_tablesize = max_sg_entrys;
  490. roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
  491. acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
  492. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
  493. if(!dma_coherent){
  494. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
  495. return -ENOMEM;
  496. }
  497. acb->dma_coherent = dma_coherent;
  498. acb->dma_coherent_handle = dma_coherent_handle;
  499. memset(dma_coherent, 0, acb->uncache_size);
  500. ccb_tmp = dma_coherent;
  501. acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
  502. for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
  503. cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
  504. switch (acb->adapter_type) {
  505. case ACB_ADAPTER_TYPE_A:
  506. case ACB_ADAPTER_TYPE_B:
  507. ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
  508. break;
  509. case ACB_ADAPTER_TYPE_C:
  510. case ACB_ADAPTER_TYPE_D:
  511. ccb_tmp->cdb_phyaddr = cdb_phyaddr;
  512. break;
  513. }
  514. acb->pccb_pool[i] = ccb_tmp;
  515. ccb_tmp->acb = acb;
  516. INIT_LIST_HEAD(&ccb_tmp->list);
  517. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  518. ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
  519. dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
  520. }
  521. return 0;
  522. }
  523. static void arcmsr_message_isr_bh_fn(struct work_struct *work)
  524. {
  525. struct AdapterControlBlock *acb = container_of(work,
  526. struct AdapterControlBlock, arcmsr_do_message_isr_bh);
  527. char *acb_dev_map = (char *)acb->device_map;
  528. uint32_t __iomem *signature = NULL;
  529. char __iomem *devicemap = NULL;
  530. int target, lun;
  531. struct scsi_device *psdev;
  532. char diff, temp;
  533. switch (acb->adapter_type) {
  534. case ACB_ADAPTER_TYPE_A: {
  535. struct MessageUnit_A __iomem *reg = acb->pmuA;
  536. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  537. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  538. break;
  539. }
  540. case ACB_ADAPTER_TYPE_B: {
  541. struct MessageUnit_B *reg = acb->pmuB;
  542. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  543. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  544. break;
  545. }
  546. case ACB_ADAPTER_TYPE_C: {
  547. struct MessageUnit_C __iomem *reg = acb->pmuC;
  548. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  549. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  550. break;
  551. }
  552. case ACB_ADAPTER_TYPE_D: {
  553. struct MessageUnit_D *reg = acb->pmuD;
  554. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  555. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  556. break;
  557. }
  558. }
  559. atomic_inc(&acb->rq_map_token);
  560. if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
  561. return;
  562. for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
  563. target++) {
  564. temp = readb(devicemap);
  565. diff = (*acb_dev_map) ^ temp;
  566. if (diff != 0) {
  567. *acb_dev_map = temp;
  568. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
  569. lun++) {
  570. if ((diff & 0x01) == 1 &&
  571. (temp & 0x01) == 1) {
  572. scsi_add_device(acb->host,
  573. 0, target, lun);
  574. } else if ((diff & 0x01) == 1
  575. && (temp & 0x01) == 0) {
  576. psdev = scsi_device_lookup(acb->host,
  577. 0, target, lun);
  578. if (psdev != NULL) {
  579. scsi_remove_device(psdev);
  580. scsi_device_put(psdev);
  581. }
  582. }
  583. temp >>= 1;
  584. diff >>= 1;
  585. }
  586. }
  587. devicemap++;
  588. acb_dev_map++;
  589. }
  590. }
  591. static int
  592. arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
  593. {
  594. int i, j, r;
  595. struct msix_entry entries[ARCMST_NUM_MSIX_VECTORS];
  596. for (i = 0; i < ARCMST_NUM_MSIX_VECTORS; i++)
  597. entries[i].entry = i;
  598. r = pci_enable_msix_range(pdev, entries, 1, ARCMST_NUM_MSIX_VECTORS);
  599. if (r < 0)
  600. goto msi_int;
  601. acb->msix_vector_count = r;
  602. for (i = 0; i < r; i++) {
  603. if (request_irq(entries[i].vector,
  604. arcmsr_do_interrupt, 0, "arcmsr", acb)) {
  605. pr_warn("arcmsr%d: request_irq =%d failed!\n",
  606. acb->host->host_no, entries[i].vector);
  607. for (j = 0 ; j < i ; j++)
  608. free_irq(entries[j].vector, acb);
  609. pci_disable_msix(pdev);
  610. goto msi_int;
  611. }
  612. acb->entries[i] = entries[i];
  613. }
  614. acb->acb_flags |= ACB_F_MSIX_ENABLED;
  615. pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
  616. return SUCCESS;
  617. msi_int:
  618. if (pci_enable_msi_exact(pdev, 1) < 0)
  619. goto legacy_int;
  620. if (request_irq(pdev->irq, arcmsr_do_interrupt,
  621. IRQF_SHARED, "arcmsr", acb)) {
  622. pr_warn("arcmsr%d: request_irq =%d failed!\n",
  623. acb->host->host_no, pdev->irq);
  624. pci_disable_msi(pdev);
  625. goto legacy_int;
  626. }
  627. acb->acb_flags |= ACB_F_MSI_ENABLED;
  628. pr_info("arcmsr%d: msi enabled\n", acb->host->host_no);
  629. return SUCCESS;
  630. legacy_int:
  631. if (request_irq(pdev->irq, arcmsr_do_interrupt,
  632. IRQF_SHARED, "arcmsr", acb)) {
  633. pr_warn("arcmsr%d: request_irq = %d failed!\n",
  634. acb->host->host_no, pdev->irq);
  635. return FAILED;
  636. }
  637. return SUCCESS;
  638. }
  639. static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  640. {
  641. struct Scsi_Host *host;
  642. struct AdapterControlBlock *acb;
  643. uint8_t bus,dev_fun;
  644. int error;
  645. error = pci_enable_device(pdev);
  646. if(error){
  647. return -ENODEV;
  648. }
  649. host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
  650. if(!host){
  651. goto pci_disable_dev;
  652. }
  653. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  654. if(error){
  655. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  656. if(error){
  657. printk(KERN_WARNING
  658. "scsi%d: No suitable DMA mask available\n",
  659. host->host_no);
  660. goto scsi_host_release;
  661. }
  662. }
  663. init_waitqueue_head(&wait_q);
  664. bus = pdev->bus->number;
  665. dev_fun = pdev->devfn;
  666. acb = (struct AdapterControlBlock *) host->hostdata;
  667. memset(acb,0,sizeof(struct AdapterControlBlock));
  668. acb->pdev = pdev;
  669. acb->host = host;
  670. host->max_lun = ARCMSR_MAX_TARGETLUN;
  671. host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
  672. host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
  673. host->can_queue = ARCMSR_MAX_OUTSTANDING_CMD;
  674. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  675. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  676. host->unique_id = (bus << 8) | dev_fun;
  677. pci_set_drvdata(pdev, host);
  678. pci_set_master(pdev);
  679. error = pci_request_regions(pdev, "arcmsr");
  680. if(error){
  681. goto scsi_host_release;
  682. }
  683. spin_lock_init(&acb->eh_lock);
  684. spin_lock_init(&acb->ccblist_lock);
  685. spin_lock_init(&acb->postq_lock);
  686. spin_lock_init(&acb->doneq_lock);
  687. spin_lock_init(&acb->rqbuffer_lock);
  688. spin_lock_init(&acb->wqbuffer_lock);
  689. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  690. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  691. ACB_F_MESSAGE_WQBUFFER_READED);
  692. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  693. INIT_LIST_HEAD(&acb->ccb_free_list);
  694. acb->adapter_type = id->driver_data;
  695. error = arcmsr_remap_pciregion(acb);
  696. if(!error){
  697. goto pci_release_regs;
  698. }
  699. error = arcmsr_get_firmware_spec(acb);
  700. if(!error){
  701. goto unmap_pci_region;
  702. }
  703. error = arcmsr_alloc_ccb_pool(acb);
  704. if(error){
  705. goto free_hbb_mu;
  706. }
  707. error = scsi_add_host(host, &pdev->dev);
  708. if(error){
  709. goto free_ccb_pool;
  710. }
  711. if (arcmsr_request_irq(pdev, acb) == FAILED)
  712. goto scsi_host_remove;
  713. arcmsr_iop_init(acb);
  714. INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  715. atomic_set(&acb->rq_map_token, 16);
  716. atomic_set(&acb->ante_token_value, 16);
  717. acb->fw_flag = FW_NORMAL;
  718. init_timer(&acb->eternal_timer);
  719. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  720. acb->eternal_timer.data = (unsigned long) acb;
  721. acb->eternal_timer.function = &arcmsr_request_device_map;
  722. add_timer(&acb->eternal_timer);
  723. if(arcmsr_alloc_sysfs_attr(acb))
  724. goto out_free_sysfs;
  725. scsi_scan_host(host);
  726. return 0;
  727. out_free_sysfs:
  728. del_timer_sync(&acb->eternal_timer);
  729. flush_work(&acb->arcmsr_do_message_isr_bh);
  730. arcmsr_stop_adapter_bgrb(acb);
  731. arcmsr_flush_adapter_cache(acb);
  732. arcmsr_free_irq(pdev, acb);
  733. scsi_host_remove:
  734. scsi_remove_host(host);
  735. free_ccb_pool:
  736. arcmsr_free_ccb_pool(acb);
  737. free_hbb_mu:
  738. arcmsr_free_mu(acb);
  739. unmap_pci_region:
  740. arcmsr_unmap_pciregion(acb);
  741. pci_release_regs:
  742. pci_release_regions(pdev);
  743. scsi_host_release:
  744. scsi_host_put(host);
  745. pci_disable_dev:
  746. pci_disable_device(pdev);
  747. return -ENODEV;
  748. }
  749. static void arcmsr_free_irq(struct pci_dev *pdev,
  750. struct AdapterControlBlock *acb)
  751. {
  752. int i;
  753. if (acb->acb_flags & ACB_F_MSI_ENABLED) {
  754. free_irq(pdev->irq, acb);
  755. pci_disable_msi(pdev);
  756. } else if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
  757. for (i = 0; i < acb->msix_vector_count; i++)
  758. free_irq(acb->entries[i].vector, acb);
  759. pci_disable_msix(pdev);
  760. } else
  761. free_irq(pdev->irq, acb);
  762. }
  763. static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
  764. {
  765. uint32_t intmask_org;
  766. struct Scsi_Host *host = pci_get_drvdata(pdev);
  767. struct AdapterControlBlock *acb =
  768. (struct AdapterControlBlock *)host->hostdata;
  769. intmask_org = arcmsr_disable_outbound_ints(acb);
  770. arcmsr_free_irq(pdev, acb);
  771. del_timer_sync(&acb->eternal_timer);
  772. flush_work(&acb->arcmsr_do_message_isr_bh);
  773. arcmsr_stop_adapter_bgrb(acb);
  774. arcmsr_flush_adapter_cache(acb);
  775. pci_set_drvdata(pdev, host);
  776. pci_save_state(pdev);
  777. pci_disable_device(pdev);
  778. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  779. return 0;
  780. }
  781. static int arcmsr_resume(struct pci_dev *pdev)
  782. {
  783. int error;
  784. struct Scsi_Host *host = pci_get_drvdata(pdev);
  785. struct AdapterControlBlock *acb =
  786. (struct AdapterControlBlock *)host->hostdata;
  787. pci_set_power_state(pdev, PCI_D0);
  788. pci_enable_wake(pdev, PCI_D0, 0);
  789. pci_restore_state(pdev);
  790. if (pci_enable_device(pdev)) {
  791. pr_warn("%s: pci_enable_device error\n", __func__);
  792. return -ENODEV;
  793. }
  794. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  795. if (error) {
  796. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  797. if (error) {
  798. pr_warn("scsi%d: No suitable DMA mask available\n",
  799. host->host_no);
  800. goto controller_unregister;
  801. }
  802. }
  803. pci_set_master(pdev);
  804. if (arcmsr_request_irq(pdev, acb) == FAILED)
  805. goto controller_stop;
  806. arcmsr_iop_init(acb);
  807. INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  808. atomic_set(&acb->rq_map_token, 16);
  809. atomic_set(&acb->ante_token_value, 16);
  810. acb->fw_flag = FW_NORMAL;
  811. init_timer(&acb->eternal_timer);
  812. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  813. acb->eternal_timer.data = (unsigned long) acb;
  814. acb->eternal_timer.function = &arcmsr_request_device_map;
  815. add_timer(&acb->eternal_timer);
  816. return 0;
  817. controller_stop:
  818. arcmsr_stop_adapter_bgrb(acb);
  819. arcmsr_flush_adapter_cache(acb);
  820. controller_unregister:
  821. scsi_remove_host(host);
  822. arcmsr_free_ccb_pool(acb);
  823. arcmsr_unmap_pciregion(acb);
  824. pci_release_regions(pdev);
  825. scsi_host_put(host);
  826. pci_disable_device(pdev);
  827. return -ENODEV;
  828. }
  829. static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
  830. {
  831. struct MessageUnit_A __iomem *reg = acb->pmuA;
  832. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  833. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  834. printk(KERN_NOTICE
  835. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  836. , acb->host->host_no);
  837. return false;
  838. }
  839. return true;
  840. }
  841. static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
  842. {
  843. struct MessageUnit_B *reg = acb->pmuB;
  844. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
  845. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  846. printk(KERN_NOTICE
  847. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  848. , acb->host->host_no);
  849. return false;
  850. }
  851. return true;
  852. }
  853. static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
  854. {
  855. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  856. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  857. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  858. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  859. printk(KERN_NOTICE
  860. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  861. , pACB->host->host_no);
  862. return false;
  863. }
  864. return true;
  865. }
  866. static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
  867. {
  868. struct MessageUnit_D *reg = pACB->pmuD;
  869. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
  870. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  871. pr_notice("arcmsr%d: wait 'abort all outstanding "
  872. "command' timeout\n", pACB->host->host_no);
  873. return false;
  874. }
  875. return true;
  876. }
  877. static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  878. {
  879. uint8_t rtnval = 0;
  880. switch (acb->adapter_type) {
  881. case ACB_ADAPTER_TYPE_A: {
  882. rtnval = arcmsr_hbaA_abort_allcmd(acb);
  883. }
  884. break;
  885. case ACB_ADAPTER_TYPE_B: {
  886. rtnval = arcmsr_hbaB_abort_allcmd(acb);
  887. }
  888. break;
  889. case ACB_ADAPTER_TYPE_C: {
  890. rtnval = arcmsr_hbaC_abort_allcmd(acb);
  891. }
  892. break;
  893. case ACB_ADAPTER_TYPE_D:
  894. rtnval = arcmsr_hbaD_abort_allcmd(acb);
  895. break;
  896. }
  897. return rtnval;
  898. }
  899. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  900. {
  901. struct scsi_cmnd *pcmd = ccb->pcmd;
  902. scsi_dma_unmap(pcmd);
  903. }
  904. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
  905. {
  906. struct AdapterControlBlock *acb = ccb->acb;
  907. struct scsi_cmnd *pcmd = ccb->pcmd;
  908. unsigned long flags;
  909. atomic_dec(&acb->ccboutstandingcount);
  910. arcmsr_pci_unmap_dma(ccb);
  911. ccb->startdone = ARCMSR_CCB_DONE;
  912. spin_lock_irqsave(&acb->ccblist_lock, flags);
  913. list_add_tail(&ccb->list, &acb->ccb_free_list);
  914. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  915. pcmd->scsi_done(pcmd);
  916. }
  917. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  918. {
  919. struct scsi_cmnd *pcmd = ccb->pcmd;
  920. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  921. pcmd->result = DID_OK << 16;
  922. if (sensebuffer) {
  923. int sense_data_length =
  924. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  925. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  926. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  927. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  928. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  929. sensebuffer->Valid = 1;
  930. }
  931. }
  932. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  933. {
  934. u32 orig_mask = 0;
  935. switch (acb->adapter_type) {
  936. case ACB_ADAPTER_TYPE_A : {
  937. struct MessageUnit_A __iomem *reg = acb->pmuA;
  938. orig_mask = readl(&reg->outbound_intmask);
  939. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  940. &reg->outbound_intmask);
  941. }
  942. break;
  943. case ACB_ADAPTER_TYPE_B : {
  944. struct MessageUnit_B *reg = acb->pmuB;
  945. orig_mask = readl(reg->iop2drv_doorbell_mask);
  946. writel(0, reg->iop2drv_doorbell_mask);
  947. }
  948. break;
  949. case ACB_ADAPTER_TYPE_C:{
  950. struct MessageUnit_C __iomem *reg = acb->pmuC;
  951. /* disable all outbound interrupt */
  952. orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
  953. writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  954. }
  955. break;
  956. case ACB_ADAPTER_TYPE_D: {
  957. struct MessageUnit_D *reg = acb->pmuD;
  958. /* disable all outbound interrupt */
  959. writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
  960. }
  961. break;
  962. }
  963. return orig_mask;
  964. }
  965. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
  966. struct CommandControlBlock *ccb, bool error)
  967. {
  968. uint8_t id, lun;
  969. id = ccb->pcmd->device->id;
  970. lun = ccb->pcmd->device->lun;
  971. if (!error) {
  972. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  973. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  974. ccb->pcmd->result = DID_OK << 16;
  975. arcmsr_ccb_complete(ccb);
  976. }else{
  977. switch (ccb->arcmsr_cdb.DeviceStatus) {
  978. case ARCMSR_DEV_SELECT_TIMEOUT: {
  979. acb->devstate[id][lun] = ARECA_RAID_GONE;
  980. ccb->pcmd->result = DID_NO_CONNECT << 16;
  981. arcmsr_ccb_complete(ccb);
  982. }
  983. break;
  984. case ARCMSR_DEV_ABORTED:
  985. case ARCMSR_DEV_INIT_FAIL: {
  986. acb->devstate[id][lun] = ARECA_RAID_GONE;
  987. ccb->pcmd->result = DID_BAD_TARGET << 16;
  988. arcmsr_ccb_complete(ccb);
  989. }
  990. break;
  991. case ARCMSR_DEV_CHECK_CONDITION: {
  992. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  993. arcmsr_report_sense_info(ccb);
  994. arcmsr_ccb_complete(ccb);
  995. }
  996. break;
  997. default:
  998. printk(KERN_NOTICE
  999. "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
  1000. but got unknown DeviceStatus = 0x%x \n"
  1001. , acb->host->host_no
  1002. , id
  1003. , lun
  1004. , ccb->arcmsr_cdb.DeviceStatus);
  1005. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1006. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1007. arcmsr_ccb_complete(ccb);
  1008. break;
  1009. }
  1010. }
  1011. }
  1012. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
  1013. {
  1014. int id, lun;
  1015. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  1016. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  1017. struct scsi_cmnd *abortcmd = pCCB->pcmd;
  1018. if (abortcmd) {
  1019. id = abortcmd->device->id;
  1020. lun = abortcmd->device->lun;
  1021. abortcmd->result |= DID_ABORT << 16;
  1022. arcmsr_ccb_complete(pCCB);
  1023. printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
  1024. acb->host->host_no, pCCB);
  1025. }
  1026. return;
  1027. }
  1028. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  1029. done acb = '0x%p'"
  1030. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  1031. " ccboutstandingcount = %d \n"
  1032. , acb->host->host_no
  1033. , acb
  1034. , pCCB
  1035. , pCCB->acb
  1036. , pCCB->startdone
  1037. , atomic_read(&acb->ccboutstandingcount));
  1038. return;
  1039. }
  1040. arcmsr_report_ccb_state(acb, pCCB, error);
  1041. }
  1042. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  1043. {
  1044. int i = 0;
  1045. uint32_t flag_ccb, ccb_cdb_phy;
  1046. struct ARCMSR_CDB *pARCMSR_CDB;
  1047. bool error;
  1048. struct CommandControlBlock *pCCB;
  1049. switch (acb->adapter_type) {
  1050. case ACB_ADAPTER_TYPE_A: {
  1051. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1052. uint32_t outbound_intstatus;
  1053. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1054. acb->outbound_int_enable;
  1055. /*clear and abort all outbound posted Q*/
  1056. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1057. while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  1058. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  1059. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1060. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1061. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1062. arcmsr_drain_donequeue(acb, pCCB, error);
  1063. }
  1064. }
  1065. break;
  1066. case ACB_ADAPTER_TYPE_B: {
  1067. struct MessageUnit_B *reg = acb->pmuB;
  1068. /*clear all outbound posted Q*/
  1069. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
  1070. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  1071. flag_ccb = reg->done_qbuffer[i];
  1072. if (flag_ccb != 0) {
  1073. reg->done_qbuffer[i] = 0;
  1074. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1075. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1076. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1077. arcmsr_drain_donequeue(acb, pCCB, error);
  1078. }
  1079. reg->post_qbuffer[i] = 0;
  1080. }
  1081. reg->doneq_index = 0;
  1082. reg->postq_index = 0;
  1083. }
  1084. break;
  1085. case ACB_ADAPTER_TYPE_C: {
  1086. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1087. while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  1088. /*need to do*/
  1089. flag_ccb = readl(&reg->outbound_queueport_low);
  1090. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  1091. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  1092. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1093. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  1094. arcmsr_drain_donequeue(acb, pCCB, error);
  1095. }
  1096. }
  1097. break;
  1098. case ACB_ADAPTER_TYPE_D: {
  1099. struct MessageUnit_D *pmu = acb->pmuD;
  1100. uint32_t outbound_write_pointer;
  1101. uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
  1102. unsigned long flags;
  1103. residual = atomic_read(&acb->ccboutstandingcount);
  1104. for (i = 0; i < residual; i++) {
  1105. spin_lock_irqsave(&acb->doneq_lock, flags);
  1106. outbound_write_pointer =
  1107. pmu->done_qbuffer[0].addressLow + 1;
  1108. doneq_index = pmu->doneq_index;
  1109. if ((doneq_index & 0xFFF) !=
  1110. (outbound_write_pointer & 0xFFF)) {
  1111. toggle = doneq_index & 0x4000;
  1112. index_stripped = (doneq_index & 0xFFF) + 1;
  1113. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  1114. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  1115. ((toggle ^ 0x4000) + 1);
  1116. doneq_index = pmu->doneq_index;
  1117. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1118. addressLow = pmu->done_qbuffer[doneq_index &
  1119. 0xFFF].addressLow;
  1120. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  1121. pARCMSR_CDB = (struct ARCMSR_CDB *)
  1122. (acb->vir2phy_offset + ccb_cdb_phy);
  1123. pCCB = container_of(pARCMSR_CDB,
  1124. struct CommandControlBlock, arcmsr_cdb);
  1125. error = (addressLow &
  1126. ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
  1127. true : false;
  1128. arcmsr_drain_donequeue(acb, pCCB, error);
  1129. writel(doneq_index,
  1130. pmu->outboundlist_read_pointer);
  1131. } else {
  1132. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1133. mdelay(10);
  1134. }
  1135. }
  1136. pmu->postq_index = 0;
  1137. pmu->doneq_index = 0x40FF;
  1138. }
  1139. break;
  1140. }
  1141. }
  1142. static void arcmsr_remove(struct pci_dev *pdev)
  1143. {
  1144. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1145. struct AdapterControlBlock *acb =
  1146. (struct AdapterControlBlock *) host->hostdata;
  1147. int poll_count = 0;
  1148. arcmsr_free_sysfs_attr(acb);
  1149. scsi_remove_host(host);
  1150. flush_work(&acb->arcmsr_do_message_isr_bh);
  1151. del_timer_sync(&acb->eternal_timer);
  1152. arcmsr_disable_outbound_ints(acb);
  1153. arcmsr_stop_adapter_bgrb(acb);
  1154. arcmsr_flush_adapter_cache(acb);
  1155. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  1156. acb->acb_flags &= ~ACB_F_IOP_INITED;
  1157. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
  1158. if (!atomic_read(&acb->ccboutstandingcount))
  1159. break;
  1160. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1161. msleep(25);
  1162. }
  1163. if (atomic_read(&acb->ccboutstandingcount)) {
  1164. int i;
  1165. arcmsr_abort_allcmd(acb);
  1166. arcmsr_done4abort_postqueue(acb);
  1167. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1168. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1169. if (ccb->startdone == ARCMSR_CCB_START) {
  1170. ccb->startdone = ARCMSR_CCB_ABORTED;
  1171. ccb->pcmd->result = DID_ABORT << 16;
  1172. arcmsr_ccb_complete(ccb);
  1173. }
  1174. }
  1175. }
  1176. arcmsr_free_irq(pdev, acb);
  1177. arcmsr_free_ccb_pool(acb);
  1178. arcmsr_free_mu(acb);
  1179. arcmsr_unmap_pciregion(acb);
  1180. pci_release_regions(pdev);
  1181. scsi_host_put(host);
  1182. pci_disable_device(pdev);
  1183. }
  1184. static void arcmsr_shutdown(struct pci_dev *pdev)
  1185. {
  1186. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1187. struct AdapterControlBlock *acb =
  1188. (struct AdapterControlBlock *)host->hostdata;
  1189. del_timer_sync(&acb->eternal_timer);
  1190. arcmsr_disable_outbound_ints(acb);
  1191. arcmsr_free_irq(pdev, acb);
  1192. flush_work(&acb->arcmsr_do_message_isr_bh);
  1193. arcmsr_stop_adapter_bgrb(acb);
  1194. arcmsr_flush_adapter_cache(acb);
  1195. }
  1196. static int arcmsr_module_init(void)
  1197. {
  1198. int error = 0;
  1199. error = pci_register_driver(&arcmsr_pci_driver);
  1200. return error;
  1201. }
  1202. static void arcmsr_module_exit(void)
  1203. {
  1204. pci_unregister_driver(&arcmsr_pci_driver);
  1205. }
  1206. module_init(arcmsr_module_init);
  1207. module_exit(arcmsr_module_exit);
  1208. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  1209. u32 intmask_org)
  1210. {
  1211. u32 mask;
  1212. switch (acb->adapter_type) {
  1213. case ACB_ADAPTER_TYPE_A: {
  1214. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1215. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  1216. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
  1217. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
  1218. writel(mask, &reg->outbound_intmask);
  1219. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  1220. }
  1221. break;
  1222. case ACB_ADAPTER_TYPE_B: {
  1223. struct MessageUnit_B *reg = acb->pmuB;
  1224. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
  1225. ARCMSR_IOP2DRV_DATA_READ_OK |
  1226. ARCMSR_IOP2DRV_CDB_DONE |
  1227. ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  1228. writel(mask, reg->iop2drv_doorbell_mask);
  1229. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  1230. }
  1231. break;
  1232. case ACB_ADAPTER_TYPE_C: {
  1233. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1234. mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
  1235. writel(intmask_org & mask, &reg->host_int_mask);
  1236. acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
  1237. }
  1238. break;
  1239. case ACB_ADAPTER_TYPE_D: {
  1240. struct MessageUnit_D *reg = acb->pmuD;
  1241. mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
  1242. writel(intmask_org | mask, reg->pcief0_int_enable);
  1243. break;
  1244. }
  1245. }
  1246. }
  1247. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  1248. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  1249. {
  1250. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1251. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  1252. __le32 address_lo, address_hi;
  1253. int arccdbsize = 0x30;
  1254. __le32 length = 0;
  1255. int i;
  1256. struct scatterlist *sg;
  1257. int nseg;
  1258. ccb->pcmd = pcmd;
  1259. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  1260. arcmsr_cdb->TargetID = pcmd->device->id;
  1261. arcmsr_cdb->LUN = pcmd->device->lun;
  1262. arcmsr_cdb->Function = 1;
  1263. arcmsr_cdb->msgContext = 0;
  1264. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  1265. nseg = scsi_dma_map(pcmd);
  1266. if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
  1267. return FAILED;
  1268. scsi_for_each_sg(pcmd, sg, nseg, i) {
  1269. /* Get the physical address of the current data pointer */
  1270. length = cpu_to_le32(sg_dma_len(sg));
  1271. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  1272. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  1273. if (address_hi == 0) {
  1274. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  1275. pdma_sg->address = address_lo;
  1276. pdma_sg->length = length;
  1277. psge += sizeof (struct SG32ENTRY);
  1278. arccdbsize += sizeof (struct SG32ENTRY);
  1279. } else {
  1280. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  1281. pdma_sg->addresshigh = address_hi;
  1282. pdma_sg->address = address_lo;
  1283. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  1284. psge += sizeof (struct SG64ENTRY);
  1285. arccdbsize += sizeof (struct SG64ENTRY);
  1286. }
  1287. }
  1288. arcmsr_cdb->sgcount = (uint8_t)nseg;
  1289. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  1290. arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
  1291. if ( arccdbsize > 256)
  1292. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  1293. if (pcmd->sc_data_direction == DMA_TO_DEVICE)
  1294. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  1295. ccb->arc_cdb_size = arccdbsize;
  1296. return SUCCESS;
  1297. }
  1298. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  1299. {
  1300. uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
  1301. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1302. atomic_inc(&acb->ccboutstandingcount);
  1303. ccb->startdone = ARCMSR_CCB_START;
  1304. switch (acb->adapter_type) {
  1305. case ACB_ADAPTER_TYPE_A: {
  1306. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1307. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  1308. writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  1309. &reg->inbound_queueport);
  1310. else
  1311. writel(cdb_phyaddr, &reg->inbound_queueport);
  1312. break;
  1313. }
  1314. case ACB_ADAPTER_TYPE_B: {
  1315. struct MessageUnit_B *reg = acb->pmuB;
  1316. uint32_t ending_index, index = reg->postq_index;
  1317. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  1318. reg->post_qbuffer[ending_index] = 0;
  1319. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  1320. reg->post_qbuffer[index] =
  1321. cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
  1322. } else {
  1323. reg->post_qbuffer[index] = cdb_phyaddr;
  1324. }
  1325. index++;
  1326. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  1327. reg->postq_index = index;
  1328. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
  1329. }
  1330. break;
  1331. case ACB_ADAPTER_TYPE_C: {
  1332. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1333. uint32_t ccb_post_stamp, arc_cdb_size;
  1334. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1335. ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
  1336. if (acb->cdb_phyaddr_hi32) {
  1337. writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
  1338. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1339. } else {
  1340. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1341. }
  1342. }
  1343. break;
  1344. case ACB_ADAPTER_TYPE_D: {
  1345. struct MessageUnit_D *pmu = acb->pmuD;
  1346. u16 index_stripped;
  1347. u16 postq_index, toggle;
  1348. unsigned long flags;
  1349. struct InBound_SRB *pinbound_srb;
  1350. spin_lock_irqsave(&acb->postq_lock, flags);
  1351. postq_index = pmu->postq_index;
  1352. pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
  1353. pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr);
  1354. pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr);
  1355. pinbound_srb->length = ccb->arc_cdb_size >> 2;
  1356. arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
  1357. toggle = postq_index & 0x4000;
  1358. index_stripped = postq_index + 1;
  1359. index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
  1360. pmu->postq_index = index_stripped ? (index_stripped | toggle) :
  1361. (toggle ^ 0x4000);
  1362. writel(postq_index, pmu->inboundlist_write_pointer);
  1363. spin_unlock_irqrestore(&acb->postq_lock, flags);
  1364. break;
  1365. }
  1366. }
  1367. }
  1368. static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
  1369. {
  1370. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1371. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1372. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1373. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  1374. printk(KERN_NOTICE
  1375. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1376. , acb->host->host_no);
  1377. }
  1378. }
  1379. static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
  1380. {
  1381. struct MessageUnit_B *reg = acb->pmuB;
  1382. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1383. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
  1384. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  1385. printk(KERN_NOTICE
  1386. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1387. , acb->host->host_no);
  1388. }
  1389. }
  1390. static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
  1391. {
  1392. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1393. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1394. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1395. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1396. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  1397. printk(KERN_NOTICE
  1398. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1399. , pACB->host->host_no);
  1400. }
  1401. return;
  1402. }
  1403. static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
  1404. {
  1405. struct MessageUnit_D *reg = pACB->pmuD;
  1406. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1407. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
  1408. if (!arcmsr_hbaD_wait_msgint_ready(pACB))
  1409. pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
  1410. "timeout\n", pACB->host->host_no);
  1411. }
  1412. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  1413. {
  1414. switch (acb->adapter_type) {
  1415. case ACB_ADAPTER_TYPE_A: {
  1416. arcmsr_hbaA_stop_bgrb(acb);
  1417. }
  1418. break;
  1419. case ACB_ADAPTER_TYPE_B: {
  1420. arcmsr_hbaB_stop_bgrb(acb);
  1421. }
  1422. break;
  1423. case ACB_ADAPTER_TYPE_C: {
  1424. arcmsr_hbaC_stop_bgrb(acb);
  1425. }
  1426. break;
  1427. case ACB_ADAPTER_TYPE_D:
  1428. arcmsr_hbaD_stop_bgrb(acb);
  1429. break;
  1430. }
  1431. }
  1432. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  1433. {
  1434. dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
  1435. }
  1436. static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  1437. {
  1438. switch (acb->adapter_type) {
  1439. case ACB_ADAPTER_TYPE_A: {
  1440. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1441. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1442. }
  1443. break;
  1444. case ACB_ADAPTER_TYPE_B: {
  1445. struct MessageUnit_B *reg = acb->pmuB;
  1446. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  1447. }
  1448. break;
  1449. case ACB_ADAPTER_TYPE_C: {
  1450. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1451. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  1452. }
  1453. break;
  1454. case ACB_ADAPTER_TYPE_D: {
  1455. struct MessageUnit_D *reg = acb->pmuD;
  1456. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  1457. reg->inbound_doorbell);
  1458. }
  1459. break;
  1460. }
  1461. }
  1462. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  1463. {
  1464. switch (acb->adapter_type) {
  1465. case ACB_ADAPTER_TYPE_A: {
  1466. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1467. /*
  1468. ** push inbound doorbell tell iop, driver data write ok
  1469. ** and wait reply on next hwinterrupt for next Qbuffer post
  1470. */
  1471. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  1472. }
  1473. break;
  1474. case ACB_ADAPTER_TYPE_B: {
  1475. struct MessageUnit_B *reg = acb->pmuB;
  1476. /*
  1477. ** push inbound doorbell tell iop, driver data write ok
  1478. ** and wait reply on next hwinterrupt for next Qbuffer post
  1479. */
  1480. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
  1481. }
  1482. break;
  1483. case ACB_ADAPTER_TYPE_C: {
  1484. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1485. /*
  1486. ** push inbound doorbell tell iop, driver data write ok
  1487. ** and wait reply on next hwinterrupt for next Qbuffer post
  1488. */
  1489. writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
  1490. }
  1491. break;
  1492. case ACB_ADAPTER_TYPE_D: {
  1493. struct MessageUnit_D *reg = acb->pmuD;
  1494. writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
  1495. reg->inbound_doorbell);
  1496. }
  1497. break;
  1498. }
  1499. }
  1500. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  1501. {
  1502. struct QBUFFER __iomem *qbuffer = NULL;
  1503. switch (acb->adapter_type) {
  1504. case ACB_ADAPTER_TYPE_A: {
  1505. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1506. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1507. }
  1508. break;
  1509. case ACB_ADAPTER_TYPE_B: {
  1510. struct MessageUnit_B *reg = acb->pmuB;
  1511. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1512. }
  1513. break;
  1514. case ACB_ADAPTER_TYPE_C: {
  1515. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1516. qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
  1517. }
  1518. break;
  1519. case ACB_ADAPTER_TYPE_D: {
  1520. struct MessageUnit_D *reg = acb->pmuD;
  1521. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1522. }
  1523. break;
  1524. }
  1525. return qbuffer;
  1526. }
  1527. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  1528. {
  1529. struct QBUFFER __iomem *pqbuffer = NULL;
  1530. switch (acb->adapter_type) {
  1531. case ACB_ADAPTER_TYPE_A: {
  1532. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1533. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  1534. }
  1535. break;
  1536. case ACB_ADAPTER_TYPE_B: {
  1537. struct MessageUnit_B *reg = acb->pmuB;
  1538. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1539. }
  1540. break;
  1541. case ACB_ADAPTER_TYPE_C: {
  1542. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1543. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  1544. }
  1545. break;
  1546. case ACB_ADAPTER_TYPE_D: {
  1547. struct MessageUnit_D *reg = acb->pmuD;
  1548. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1549. }
  1550. break;
  1551. }
  1552. return pqbuffer;
  1553. }
  1554. static uint32_t
  1555. arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
  1556. struct QBUFFER __iomem *prbuffer)
  1557. {
  1558. uint8_t *pQbuffer;
  1559. uint8_t *buf1 = NULL;
  1560. uint32_t __iomem *iop_data;
  1561. uint32_t iop_len, data_len, *buf2 = NULL;
  1562. iop_data = (uint32_t __iomem *)prbuffer->data;
  1563. iop_len = readl(&prbuffer->data_len);
  1564. if (iop_len > 0) {
  1565. buf1 = kmalloc(128, GFP_ATOMIC);
  1566. buf2 = (uint32_t *)buf1;
  1567. if (buf1 == NULL)
  1568. return 0;
  1569. data_len = iop_len;
  1570. while (data_len >= 4) {
  1571. *buf2++ = readl(iop_data);
  1572. iop_data++;
  1573. data_len -= 4;
  1574. }
  1575. if (data_len)
  1576. *buf2 = readl(iop_data);
  1577. buf2 = (uint32_t *)buf1;
  1578. }
  1579. while (iop_len > 0) {
  1580. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  1581. *pQbuffer = *buf1;
  1582. acb->rqbuf_putIndex++;
  1583. /* if last, index number set it to 0 */
  1584. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  1585. buf1++;
  1586. iop_len--;
  1587. }
  1588. kfree(buf2);
  1589. /* let IOP know data has been read */
  1590. arcmsr_iop_message_read(acb);
  1591. return 1;
  1592. }
  1593. uint32_t
  1594. arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
  1595. struct QBUFFER __iomem *prbuffer) {
  1596. uint8_t *pQbuffer;
  1597. uint8_t __iomem *iop_data;
  1598. uint32_t iop_len;
  1599. if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D))
  1600. return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
  1601. iop_data = (uint8_t __iomem *)prbuffer->data;
  1602. iop_len = readl(&prbuffer->data_len);
  1603. while (iop_len > 0) {
  1604. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  1605. *pQbuffer = readb(iop_data);
  1606. acb->rqbuf_putIndex++;
  1607. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  1608. iop_data++;
  1609. iop_len--;
  1610. }
  1611. arcmsr_iop_message_read(acb);
  1612. return 1;
  1613. }
  1614. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1615. {
  1616. unsigned long flags;
  1617. struct QBUFFER __iomem *prbuffer;
  1618. int32_t buf_empty_len;
  1619. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  1620. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1621. buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
  1622. (ARCMSR_MAX_QBUFFER - 1);
  1623. if (buf_empty_len >= readl(&prbuffer->data_len)) {
  1624. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  1625. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1626. } else
  1627. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1628. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  1629. }
  1630. static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
  1631. {
  1632. uint8_t *pQbuffer;
  1633. struct QBUFFER __iomem *pwbuffer;
  1634. uint8_t *buf1 = NULL;
  1635. uint32_t __iomem *iop_data;
  1636. uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
  1637. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1638. buf1 = kmalloc(128, GFP_ATOMIC);
  1639. buf2 = (uint32_t *)buf1;
  1640. if (buf1 == NULL)
  1641. return;
  1642. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1643. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1644. iop_data = (uint32_t __iomem *)pwbuffer->data;
  1645. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  1646. && (allxfer_len < 124)) {
  1647. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  1648. *buf1 = *pQbuffer;
  1649. acb->wqbuf_getIndex++;
  1650. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  1651. buf1++;
  1652. allxfer_len++;
  1653. }
  1654. data_len = allxfer_len;
  1655. buf1 = (uint8_t *)buf2;
  1656. while (data_len >= 4) {
  1657. data = *buf2++;
  1658. writel(data, iop_data);
  1659. iop_data++;
  1660. data_len -= 4;
  1661. }
  1662. if (data_len) {
  1663. data = *buf2;
  1664. writel(data, iop_data);
  1665. }
  1666. writel(allxfer_len, &pwbuffer->data_len);
  1667. kfree(buf1);
  1668. arcmsr_iop_message_wrote(acb);
  1669. }
  1670. }
  1671. void
  1672. arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
  1673. {
  1674. uint8_t *pQbuffer;
  1675. struct QBUFFER __iomem *pwbuffer;
  1676. uint8_t __iomem *iop_data;
  1677. int32_t allxfer_len = 0;
  1678. if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
  1679. arcmsr_write_ioctldata2iop_in_DWORD(acb);
  1680. return;
  1681. }
  1682. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1683. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1684. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1685. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1686. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  1687. && (allxfer_len < 124)) {
  1688. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  1689. writeb(*pQbuffer, iop_data);
  1690. acb->wqbuf_getIndex++;
  1691. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  1692. iop_data++;
  1693. allxfer_len++;
  1694. }
  1695. writel(allxfer_len, &pwbuffer->data_len);
  1696. arcmsr_iop_message_wrote(acb);
  1697. }
  1698. }
  1699. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1700. {
  1701. unsigned long flags;
  1702. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  1703. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1704. if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  1705. arcmsr_write_ioctldata2iop(acb);
  1706. if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
  1707. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1708. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  1709. }
  1710. static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
  1711. {
  1712. uint32_t outbound_doorbell;
  1713. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1714. outbound_doorbell = readl(&reg->outbound_doorbell);
  1715. do {
  1716. writel(outbound_doorbell, &reg->outbound_doorbell);
  1717. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
  1718. arcmsr_iop2drv_data_wrote_handle(acb);
  1719. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
  1720. arcmsr_iop2drv_data_read_handle(acb);
  1721. outbound_doorbell = readl(&reg->outbound_doorbell);
  1722. } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
  1723. | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
  1724. }
  1725. static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
  1726. {
  1727. uint32_t outbound_doorbell;
  1728. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1729. /*
  1730. *******************************************************************
  1731. ** Maybe here we need to check wrqbuffer_lock is lock or not
  1732. ** DOORBELL: din! don!
  1733. ** check if there are any mail need to pack from firmware
  1734. *******************************************************************
  1735. */
  1736. outbound_doorbell = readl(&reg->outbound_doorbell);
  1737. do {
  1738. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  1739. readl(&reg->outbound_doorbell_clear);
  1740. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
  1741. arcmsr_iop2drv_data_wrote_handle(pACB);
  1742. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
  1743. arcmsr_iop2drv_data_read_handle(pACB);
  1744. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
  1745. arcmsr_hbaC_message_isr(pACB);
  1746. outbound_doorbell = readl(&reg->outbound_doorbell);
  1747. } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
  1748. | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
  1749. | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
  1750. }
  1751. static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
  1752. {
  1753. uint32_t outbound_doorbell;
  1754. struct MessageUnit_D *pmu = pACB->pmuD;
  1755. outbound_doorbell = readl(pmu->outbound_doorbell);
  1756. do {
  1757. writel(outbound_doorbell, pmu->outbound_doorbell);
  1758. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
  1759. arcmsr_hbaD_message_isr(pACB);
  1760. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
  1761. arcmsr_iop2drv_data_wrote_handle(pACB);
  1762. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
  1763. arcmsr_iop2drv_data_read_handle(pACB);
  1764. outbound_doorbell = readl(pmu->outbound_doorbell);
  1765. } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
  1766. | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
  1767. | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
  1768. }
  1769. static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
  1770. {
  1771. uint32_t flag_ccb;
  1772. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1773. struct ARCMSR_CDB *pARCMSR_CDB;
  1774. struct CommandControlBlock *pCCB;
  1775. bool error;
  1776. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1777. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1778. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1779. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1780. arcmsr_drain_donequeue(acb, pCCB, error);
  1781. }
  1782. }
  1783. static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
  1784. {
  1785. uint32_t index;
  1786. uint32_t flag_ccb;
  1787. struct MessageUnit_B *reg = acb->pmuB;
  1788. struct ARCMSR_CDB *pARCMSR_CDB;
  1789. struct CommandControlBlock *pCCB;
  1790. bool error;
  1791. index = reg->doneq_index;
  1792. while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
  1793. reg->done_qbuffer[index] = 0;
  1794. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1795. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1796. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1797. arcmsr_drain_donequeue(acb, pCCB, error);
  1798. index++;
  1799. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1800. reg->doneq_index = index;
  1801. }
  1802. }
  1803. static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
  1804. {
  1805. struct MessageUnit_C __iomem *phbcmu;
  1806. struct ARCMSR_CDB *arcmsr_cdb;
  1807. struct CommandControlBlock *ccb;
  1808. uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
  1809. int error;
  1810. phbcmu = acb->pmuC;
  1811. /* areca cdb command done */
  1812. /* Use correct offset and size for syncing */
  1813. while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
  1814. 0xFFFFFFFF) {
  1815. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  1816. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  1817. + ccb_cdb_phy);
  1818. ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
  1819. arcmsr_cdb);
  1820. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  1821. ? true : false;
  1822. /* check if command done with no error */
  1823. arcmsr_drain_donequeue(acb, ccb, error);
  1824. throttling++;
  1825. if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
  1826. writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
  1827. &phbcmu->inbound_doorbell);
  1828. throttling = 0;
  1829. }
  1830. }
  1831. }
  1832. static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
  1833. {
  1834. u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
  1835. uint32_t addressLow, ccb_cdb_phy;
  1836. int error;
  1837. struct MessageUnit_D *pmu;
  1838. struct ARCMSR_CDB *arcmsr_cdb;
  1839. struct CommandControlBlock *ccb;
  1840. unsigned long flags;
  1841. spin_lock_irqsave(&acb->doneq_lock, flags);
  1842. pmu = acb->pmuD;
  1843. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  1844. doneq_index = pmu->doneq_index;
  1845. if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
  1846. do {
  1847. toggle = doneq_index & 0x4000;
  1848. index_stripped = (doneq_index & 0xFFF) + 1;
  1849. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  1850. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  1851. ((toggle ^ 0x4000) + 1);
  1852. doneq_index = pmu->doneq_index;
  1853. addressLow = pmu->done_qbuffer[doneq_index &
  1854. 0xFFF].addressLow;
  1855. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  1856. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  1857. + ccb_cdb_phy);
  1858. ccb = container_of(arcmsr_cdb,
  1859. struct CommandControlBlock, arcmsr_cdb);
  1860. error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  1861. ? true : false;
  1862. arcmsr_drain_donequeue(acb, ccb, error);
  1863. writel(doneq_index, pmu->outboundlist_read_pointer);
  1864. } while ((doneq_index & 0xFFF) !=
  1865. (outbound_write_pointer & 0xFFF));
  1866. }
  1867. writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
  1868. pmu->outboundlist_interrupt_cause);
  1869. readl(pmu->outboundlist_interrupt_cause);
  1870. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1871. }
  1872. /*
  1873. **********************************************************************************
  1874. ** Handle a message interrupt
  1875. **
  1876. ** The only message interrupt we expect is in response to a query for the current adapter config.
  1877. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1878. **********************************************************************************
  1879. */
  1880. static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
  1881. {
  1882. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1883. /*clear interrupt and message state*/
  1884. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
  1885. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1886. }
  1887. static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
  1888. {
  1889. struct MessageUnit_B *reg = acb->pmuB;
  1890. /*clear interrupt and message state*/
  1891. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  1892. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1893. }
  1894. /*
  1895. **********************************************************************************
  1896. ** Handle a message interrupt
  1897. **
  1898. ** The only message interrupt we expect is in response to a query for the
  1899. ** current adapter config.
  1900. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1901. **********************************************************************************
  1902. */
  1903. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
  1904. {
  1905. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1906. /*clear interrupt and message state*/
  1907. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
  1908. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1909. }
  1910. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
  1911. {
  1912. struct MessageUnit_D *reg = acb->pmuD;
  1913. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
  1914. readl(reg->outbound_doorbell);
  1915. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1916. }
  1917. static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
  1918. {
  1919. uint32_t outbound_intstatus;
  1920. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1921. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1922. acb->outbound_int_enable;
  1923. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
  1924. return IRQ_NONE;
  1925. do {
  1926. writel(outbound_intstatus, &reg->outbound_intstatus);
  1927. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
  1928. arcmsr_hbaA_doorbell_isr(acb);
  1929. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
  1930. arcmsr_hbaA_postqueue_isr(acb);
  1931. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
  1932. arcmsr_hbaA_message_isr(acb);
  1933. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1934. acb->outbound_int_enable;
  1935. } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
  1936. | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
  1937. | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
  1938. return IRQ_HANDLED;
  1939. }
  1940. static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
  1941. {
  1942. uint32_t outbound_doorbell;
  1943. struct MessageUnit_B *reg = acb->pmuB;
  1944. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  1945. acb->outbound_int_enable;
  1946. if (!outbound_doorbell)
  1947. return IRQ_NONE;
  1948. do {
  1949. writel(~outbound_doorbell, reg->iop2drv_doorbell);
  1950. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  1951. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
  1952. arcmsr_iop2drv_data_wrote_handle(acb);
  1953. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
  1954. arcmsr_iop2drv_data_read_handle(acb);
  1955. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
  1956. arcmsr_hbaB_postqueue_isr(acb);
  1957. if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
  1958. arcmsr_hbaB_message_isr(acb);
  1959. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  1960. acb->outbound_int_enable;
  1961. } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
  1962. | ARCMSR_IOP2DRV_DATA_READ_OK
  1963. | ARCMSR_IOP2DRV_CDB_DONE
  1964. | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
  1965. return IRQ_HANDLED;
  1966. }
  1967. static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
  1968. {
  1969. uint32_t host_interrupt_status;
  1970. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  1971. /*
  1972. *********************************************
  1973. ** check outbound intstatus
  1974. *********************************************
  1975. */
  1976. host_interrupt_status = readl(&phbcmu->host_int_status) &
  1977. (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  1978. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
  1979. if (!host_interrupt_status)
  1980. return IRQ_NONE;
  1981. do {
  1982. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
  1983. arcmsr_hbaC_doorbell_isr(pACB);
  1984. /* MU post queue interrupts*/
  1985. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
  1986. arcmsr_hbaC_postqueue_isr(pACB);
  1987. host_interrupt_status = readl(&phbcmu->host_int_status);
  1988. } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  1989. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
  1990. return IRQ_HANDLED;
  1991. }
  1992. static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
  1993. {
  1994. u32 host_interrupt_status;
  1995. struct MessageUnit_D *pmu = pACB->pmuD;
  1996. host_interrupt_status = readl(pmu->host_int_status) &
  1997. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  1998. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
  1999. if (!host_interrupt_status)
  2000. return IRQ_NONE;
  2001. do {
  2002. /* MU post queue interrupts*/
  2003. if (host_interrupt_status &
  2004. ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
  2005. arcmsr_hbaD_postqueue_isr(pACB);
  2006. if (host_interrupt_status &
  2007. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
  2008. arcmsr_hbaD_doorbell_isr(pACB);
  2009. host_interrupt_status = readl(pmu->host_int_status);
  2010. } while (host_interrupt_status &
  2011. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  2012. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
  2013. return IRQ_HANDLED;
  2014. }
  2015. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  2016. {
  2017. switch (acb->adapter_type) {
  2018. case ACB_ADAPTER_TYPE_A:
  2019. return arcmsr_hbaA_handle_isr(acb);
  2020. break;
  2021. case ACB_ADAPTER_TYPE_B:
  2022. return arcmsr_hbaB_handle_isr(acb);
  2023. break;
  2024. case ACB_ADAPTER_TYPE_C:
  2025. return arcmsr_hbaC_handle_isr(acb);
  2026. case ACB_ADAPTER_TYPE_D:
  2027. return arcmsr_hbaD_handle_isr(acb);
  2028. default:
  2029. return IRQ_NONE;
  2030. }
  2031. }
  2032. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  2033. {
  2034. if (acb) {
  2035. /* stop adapter background rebuild */
  2036. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  2037. uint32_t intmask_org;
  2038. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  2039. intmask_org = arcmsr_disable_outbound_ints(acb);
  2040. arcmsr_stop_adapter_bgrb(acb);
  2041. arcmsr_flush_adapter_cache(acb);
  2042. arcmsr_enable_outbound_ints(acb, intmask_org);
  2043. }
  2044. }
  2045. }
  2046. void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
  2047. {
  2048. uint32_t i;
  2049. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2050. for (i = 0; i < 15; i++) {
  2051. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2052. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2053. acb->rqbuf_getIndex = 0;
  2054. acb->rqbuf_putIndex = 0;
  2055. arcmsr_iop_message_read(acb);
  2056. mdelay(30);
  2057. } else if (acb->rqbuf_getIndex !=
  2058. acb->rqbuf_putIndex) {
  2059. acb->rqbuf_getIndex = 0;
  2060. acb->rqbuf_putIndex = 0;
  2061. mdelay(30);
  2062. } else
  2063. break;
  2064. }
  2065. }
  2066. }
  2067. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  2068. struct scsi_cmnd *cmd)
  2069. {
  2070. char *buffer;
  2071. unsigned short use_sg;
  2072. int retvalue = 0, transfer_len = 0;
  2073. unsigned long flags;
  2074. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  2075. uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
  2076. (uint32_t)cmd->cmnd[6] << 16 |
  2077. (uint32_t)cmd->cmnd[7] << 8 |
  2078. (uint32_t)cmd->cmnd[8];
  2079. struct scatterlist *sg;
  2080. use_sg = scsi_sg_count(cmd);
  2081. sg = scsi_sglist(cmd);
  2082. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2083. if (use_sg > 1) {
  2084. retvalue = ARCMSR_MESSAGE_FAIL;
  2085. goto message_out;
  2086. }
  2087. transfer_len += sg->length;
  2088. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  2089. retvalue = ARCMSR_MESSAGE_FAIL;
  2090. pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
  2091. goto message_out;
  2092. }
  2093. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
  2094. switch (controlcode) {
  2095. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  2096. unsigned char *ver_addr;
  2097. uint8_t *ptmpQbuffer;
  2098. uint32_t allxfer_len = 0;
  2099. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2100. if (!ver_addr) {
  2101. retvalue = ARCMSR_MESSAGE_FAIL;
  2102. pr_info("%s: memory not enough!\n", __func__);
  2103. goto message_out;
  2104. }
  2105. ptmpQbuffer = ver_addr;
  2106. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2107. if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
  2108. unsigned int tail = acb->rqbuf_getIndex;
  2109. unsigned int head = acb->rqbuf_putIndex;
  2110. unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
  2111. allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
  2112. if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
  2113. allxfer_len = ARCMSR_API_DATA_BUFLEN;
  2114. if (allxfer_len <= cnt_to_end)
  2115. memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
  2116. else {
  2117. memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
  2118. memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
  2119. }
  2120. acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
  2121. }
  2122. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
  2123. allxfer_len);
  2124. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2125. struct QBUFFER __iomem *prbuffer;
  2126. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2127. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  2128. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  2129. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  2130. }
  2131. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2132. kfree(ver_addr);
  2133. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  2134. if (acb->fw_flag == FW_DEADLOCK)
  2135. pcmdmessagefld->cmdmessage.ReturnCode =
  2136. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2137. else
  2138. pcmdmessagefld->cmdmessage.ReturnCode =
  2139. ARCMSR_MESSAGE_RETURNCODE_OK;
  2140. break;
  2141. }
  2142. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  2143. unsigned char *ver_addr;
  2144. int32_t user_len, cnt2end;
  2145. uint8_t *pQbuffer, *ptmpuserbuffer;
  2146. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2147. if (!ver_addr) {
  2148. retvalue = ARCMSR_MESSAGE_FAIL;
  2149. goto message_out;
  2150. }
  2151. ptmpuserbuffer = ver_addr;
  2152. user_len = pcmdmessagefld->cmdmessage.Length;
  2153. memcpy(ptmpuserbuffer,
  2154. pcmdmessagefld->messagedatabuffer, user_len);
  2155. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2156. if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
  2157. struct SENSE_DATA *sensebuffer =
  2158. (struct SENSE_DATA *)cmd->sense_buffer;
  2159. arcmsr_write_ioctldata2iop(acb);
  2160. /* has error report sensedata */
  2161. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  2162. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  2163. sensebuffer->AdditionalSenseLength = 0x0A;
  2164. sensebuffer->AdditionalSenseCode = 0x20;
  2165. sensebuffer->Valid = 1;
  2166. retvalue = ARCMSR_MESSAGE_FAIL;
  2167. } else {
  2168. pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
  2169. cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
  2170. if (user_len > cnt2end) {
  2171. memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
  2172. ptmpuserbuffer += cnt2end;
  2173. user_len -= cnt2end;
  2174. acb->wqbuf_putIndex = 0;
  2175. pQbuffer = acb->wqbuffer;
  2176. }
  2177. memcpy(pQbuffer, ptmpuserbuffer, user_len);
  2178. acb->wqbuf_putIndex += user_len;
  2179. acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  2180. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  2181. acb->acb_flags &=
  2182. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  2183. arcmsr_write_ioctldata2iop(acb);
  2184. }
  2185. }
  2186. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2187. kfree(ver_addr);
  2188. if (acb->fw_flag == FW_DEADLOCK)
  2189. pcmdmessagefld->cmdmessage.ReturnCode =
  2190. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2191. else
  2192. pcmdmessagefld->cmdmessage.ReturnCode =
  2193. ARCMSR_MESSAGE_RETURNCODE_OK;
  2194. break;
  2195. }
  2196. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  2197. uint8_t *pQbuffer = acb->rqbuffer;
  2198. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2199. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2200. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2201. acb->rqbuf_getIndex = 0;
  2202. acb->rqbuf_putIndex = 0;
  2203. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2204. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2205. if (acb->fw_flag == FW_DEADLOCK)
  2206. pcmdmessagefld->cmdmessage.ReturnCode =
  2207. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2208. else
  2209. pcmdmessagefld->cmdmessage.ReturnCode =
  2210. ARCMSR_MESSAGE_RETURNCODE_OK;
  2211. break;
  2212. }
  2213. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  2214. uint8_t *pQbuffer = acb->wqbuffer;
  2215. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2216. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2217. ACB_F_MESSAGE_WQBUFFER_READED);
  2218. acb->wqbuf_getIndex = 0;
  2219. acb->wqbuf_putIndex = 0;
  2220. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2221. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2222. if (acb->fw_flag == FW_DEADLOCK)
  2223. pcmdmessagefld->cmdmessage.ReturnCode =
  2224. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2225. else
  2226. pcmdmessagefld->cmdmessage.ReturnCode =
  2227. ARCMSR_MESSAGE_RETURNCODE_OK;
  2228. break;
  2229. }
  2230. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  2231. uint8_t *pQbuffer;
  2232. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2233. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2234. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2235. acb->rqbuf_getIndex = 0;
  2236. acb->rqbuf_putIndex = 0;
  2237. pQbuffer = acb->rqbuffer;
  2238. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2239. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2240. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2241. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2242. ACB_F_MESSAGE_WQBUFFER_READED);
  2243. acb->wqbuf_getIndex = 0;
  2244. acb->wqbuf_putIndex = 0;
  2245. pQbuffer = acb->wqbuffer;
  2246. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2247. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2248. if (acb->fw_flag == FW_DEADLOCK)
  2249. pcmdmessagefld->cmdmessage.ReturnCode =
  2250. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2251. else
  2252. pcmdmessagefld->cmdmessage.ReturnCode =
  2253. ARCMSR_MESSAGE_RETURNCODE_OK;
  2254. break;
  2255. }
  2256. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  2257. if (acb->fw_flag == FW_DEADLOCK)
  2258. pcmdmessagefld->cmdmessage.ReturnCode =
  2259. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2260. else
  2261. pcmdmessagefld->cmdmessage.ReturnCode =
  2262. ARCMSR_MESSAGE_RETURNCODE_3F;
  2263. break;
  2264. }
  2265. case ARCMSR_MESSAGE_SAY_HELLO: {
  2266. int8_t *hello_string = "Hello! I am ARCMSR";
  2267. if (acb->fw_flag == FW_DEADLOCK)
  2268. pcmdmessagefld->cmdmessage.ReturnCode =
  2269. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2270. else
  2271. pcmdmessagefld->cmdmessage.ReturnCode =
  2272. ARCMSR_MESSAGE_RETURNCODE_OK;
  2273. memcpy(pcmdmessagefld->messagedatabuffer,
  2274. hello_string, (int16_t)strlen(hello_string));
  2275. break;
  2276. }
  2277. case ARCMSR_MESSAGE_SAY_GOODBYE: {
  2278. if (acb->fw_flag == FW_DEADLOCK)
  2279. pcmdmessagefld->cmdmessage.ReturnCode =
  2280. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2281. else
  2282. pcmdmessagefld->cmdmessage.ReturnCode =
  2283. ARCMSR_MESSAGE_RETURNCODE_OK;
  2284. arcmsr_iop_parking(acb);
  2285. break;
  2286. }
  2287. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
  2288. if (acb->fw_flag == FW_DEADLOCK)
  2289. pcmdmessagefld->cmdmessage.ReturnCode =
  2290. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2291. else
  2292. pcmdmessagefld->cmdmessage.ReturnCode =
  2293. ARCMSR_MESSAGE_RETURNCODE_OK;
  2294. arcmsr_flush_adapter_cache(acb);
  2295. break;
  2296. }
  2297. default:
  2298. retvalue = ARCMSR_MESSAGE_FAIL;
  2299. pr_info("%s: unknown controlcode!\n", __func__);
  2300. }
  2301. message_out:
  2302. if (use_sg) {
  2303. struct scatterlist *sg = scsi_sglist(cmd);
  2304. kunmap_atomic(buffer - sg->offset);
  2305. }
  2306. return retvalue;
  2307. }
  2308. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  2309. {
  2310. struct list_head *head = &acb->ccb_free_list;
  2311. struct CommandControlBlock *ccb = NULL;
  2312. unsigned long flags;
  2313. spin_lock_irqsave(&acb->ccblist_lock, flags);
  2314. if (!list_empty(head)) {
  2315. ccb = list_entry(head->next, struct CommandControlBlock, list);
  2316. list_del_init(&ccb->list);
  2317. }else{
  2318. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2319. return NULL;
  2320. }
  2321. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2322. return ccb;
  2323. }
  2324. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  2325. struct scsi_cmnd *cmd)
  2326. {
  2327. switch (cmd->cmnd[0]) {
  2328. case INQUIRY: {
  2329. unsigned char inqdata[36];
  2330. char *buffer;
  2331. struct scatterlist *sg;
  2332. if (cmd->device->lun) {
  2333. cmd->result = (DID_TIME_OUT << 16);
  2334. cmd->scsi_done(cmd);
  2335. return;
  2336. }
  2337. inqdata[0] = TYPE_PROCESSOR;
  2338. /* Periph Qualifier & Periph Dev Type */
  2339. inqdata[1] = 0;
  2340. /* rem media bit & Dev Type Modifier */
  2341. inqdata[2] = 0;
  2342. /* ISO, ECMA, & ANSI versions */
  2343. inqdata[4] = 31;
  2344. /* length of additional data */
  2345. strncpy(&inqdata[8], "Areca ", 8);
  2346. /* Vendor Identification */
  2347. strncpy(&inqdata[16], "RAID controller ", 16);
  2348. /* Product Identification */
  2349. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  2350. sg = scsi_sglist(cmd);
  2351. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2352. memcpy(buffer, inqdata, sizeof(inqdata));
  2353. sg = scsi_sglist(cmd);
  2354. kunmap_atomic(buffer - sg->offset);
  2355. cmd->scsi_done(cmd);
  2356. }
  2357. break;
  2358. case WRITE_BUFFER:
  2359. case READ_BUFFER: {
  2360. if (arcmsr_iop_message_xfer(acb, cmd))
  2361. cmd->result = (DID_ERROR << 16);
  2362. cmd->scsi_done(cmd);
  2363. }
  2364. break;
  2365. default:
  2366. cmd->scsi_done(cmd);
  2367. }
  2368. }
  2369. static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
  2370. void (* done)(struct scsi_cmnd *))
  2371. {
  2372. struct Scsi_Host *host = cmd->device->host;
  2373. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  2374. struct CommandControlBlock *ccb;
  2375. int target = cmd->device->id;
  2376. int lun = cmd->device->lun;
  2377. uint8_t scsicmd = cmd->cmnd[0];
  2378. cmd->scsi_done = done;
  2379. cmd->host_scribble = NULL;
  2380. cmd->result = 0;
  2381. if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
  2382. if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
  2383. cmd->result = (DID_NO_CONNECT << 16);
  2384. }
  2385. cmd->scsi_done(cmd);
  2386. return 0;
  2387. }
  2388. if (target == 16) {
  2389. /* virtual device for iop message transfer */
  2390. arcmsr_handle_virtual_command(acb, cmd);
  2391. return 0;
  2392. }
  2393. ccb = arcmsr_get_freeccb(acb);
  2394. if (!ccb)
  2395. return SCSI_MLQUEUE_HOST_BUSY;
  2396. if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
  2397. cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
  2398. cmd->scsi_done(cmd);
  2399. return 0;
  2400. }
  2401. arcmsr_post_ccb(acb, ccb);
  2402. return 0;
  2403. }
  2404. static DEF_SCSI_QCMD(arcmsr_queue_command)
  2405. static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
  2406. {
  2407. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2408. char *acb_firm_model = acb->firm_model;
  2409. char *acb_firm_version = acb->firm_version;
  2410. char *acb_device_map = acb->device_map;
  2411. char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
  2412. char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
  2413. char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
  2414. int count;
  2415. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2416. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  2417. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2418. miscellaneous data' timeout \n", acb->host->host_no);
  2419. return false;
  2420. }
  2421. count = 8;
  2422. while (count){
  2423. *acb_firm_model = readb(iop_firm_model);
  2424. acb_firm_model++;
  2425. iop_firm_model++;
  2426. count--;
  2427. }
  2428. count = 16;
  2429. while (count){
  2430. *acb_firm_version = readb(iop_firm_version);
  2431. acb_firm_version++;
  2432. iop_firm_version++;
  2433. count--;
  2434. }
  2435. count=16;
  2436. while(count){
  2437. *acb_device_map = readb(iop_device_map);
  2438. acb_device_map++;
  2439. iop_device_map++;
  2440. count--;
  2441. }
  2442. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2443. acb->host->host_no,
  2444. acb->firm_model,
  2445. acb->firm_version);
  2446. acb->signature = readl(&reg->message_rwbuffer[0]);
  2447. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  2448. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  2449. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  2450. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  2451. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2452. return true;
  2453. }
  2454. static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
  2455. {
  2456. struct MessageUnit_B *reg = acb->pmuB;
  2457. struct pci_dev *pdev = acb->pdev;
  2458. void *dma_coherent;
  2459. dma_addr_t dma_coherent_handle;
  2460. char *acb_firm_model = acb->firm_model;
  2461. char *acb_firm_version = acb->firm_version;
  2462. char *acb_device_map = acb->device_map;
  2463. char __iomem *iop_firm_model;
  2464. /*firm_model,15,60-67*/
  2465. char __iomem *iop_firm_version;
  2466. /*firm_version,17,68-83*/
  2467. char __iomem *iop_device_map;
  2468. /*firm_version,21,84-99*/
  2469. int count;
  2470. acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32);
  2471. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
  2472. &dma_coherent_handle, GFP_KERNEL);
  2473. if (!dma_coherent){
  2474. printk(KERN_NOTICE
  2475. "arcmsr%d: dma_alloc_coherent got error for hbb mu\n",
  2476. acb->host->host_no);
  2477. return false;
  2478. }
  2479. acb->dma_coherent_handle2 = dma_coherent_handle;
  2480. acb->dma_coherent2 = dma_coherent;
  2481. reg = (struct MessageUnit_B *)dma_coherent;
  2482. acb->pmuB = reg;
  2483. reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
  2484. reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
  2485. reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
  2486. reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
  2487. reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
  2488. reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
  2489. reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
  2490. iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
  2491. iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
  2492. iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
  2493. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  2494. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  2495. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2496. miscellaneous data' timeout \n", acb->host->host_no);
  2497. return false;
  2498. }
  2499. count = 8;
  2500. while (count){
  2501. *acb_firm_model = readb(iop_firm_model);
  2502. acb_firm_model++;
  2503. iop_firm_model++;
  2504. count--;
  2505. }
  2506. count = 16;
  2507. while (count){
  2508. *acb_firm_version = readb(iop_firm_version);
  2509. acb_firm_version++;
  2510. iop_firm_version++;
  2511. count--;
  2512. }
  2513. count = 16;
  2514. while(count){
  2515. *acb_device_map = readb(iop_device_map);
  2516. acb_device_map++;
  2517. iop_device_map++;
  2518. count--;
  2519. }
  2520. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2521. acb->host->host_no,
  2522. acb->firm_model,
  2523. acb->firm_version);
  2524. acb->signature = readl(&reg->message_rwbuffer[1]);
  2525. /*firm_signature,1,00-03*/
  2526. acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
  2527. /*firm_request_len,1,04-07*/
  2528. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
  2529. /*firm_numbers_queue,2,08-11*/
  2530. acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
  2531. /*firm_sdram_size,3,12-15*/
  2532. acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
  2533. /*firm_ide_channels,4,16-19*/
  2534. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2535. /*firm_ide_channels,4,16-19*/
  2536. return true;
  2537. }
  2538. static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
  2539. {
  2540. uint32_t intmask_org, Index, firmware_state = 0;
  2541. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  2542. char *acb_firm_model = pACB->firm_model;
  2543. char *acb_firm_version = pACB->firm_version;
  2544. char __iomem *iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
  2545. char __iomem *iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
  2546. int count;
  2547. /* disable all outbound interrupt */
  2548. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  2549. writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  2550. /* wait firmware ready */
  2551. do {
  2552. firmware_state = readl(&reg->outbound_msgaddr1);
  2553. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  2554. /* post "get config" instruction */
  2555. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2556. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2557. /* wait message ready */
  2558. for (Index = 0; Index < 2000; Index++) {
  2559. if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  2560. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
  2561. break;
  2562. }
  2563. udelay(10);
  2564. } /*max 1 seconds*/
  2565. if (Index >= 2000) {
  2566. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2567. miscellaneous data' timeout \n", pACB->host->host_no);
  2568. return false;
  2569. }
  2570. count = 8;
  2571. while (count) {
  2572. *acb_firm_model = readb(iop_firm_model);
  2573. acb_firm_model++;
  2574. iop_firm_model++;
  2575. count--;
  2576. }
  2577. count = 16;
  2578. while (count) {
  2579. *acb_firm_version = readb(iop_firm_version);
  2580. acb_firm_version++;
  2581. iop_firm_version++;
  2582. count--;
  2583. }
  2584. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2585. pACB->host->host_no,
  2586. pACB->firm_model,
  2587. pACB->firm_version);
  2588. pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
  2589. pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
  2590. pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
  2591. pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
  2592. pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2593. /*all interrupt service will be enable at arcmsr_iop_init*/
  2594. return true;
  2595. }
  2596. static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
  2597. {
  2598. char *acb_firm_model = acb->firm_model;
  2599. char *acb_firm_version = acb->firm_version;
  2600. char *acb_device_map = acb->device_map;
  2601. char __iomem *iop_firm_model;
  2602. char __iomem *iop_firm_version;
  2603. char __iomem *iop_device_map;
  2604. u32 count;
  2605. struct MessageUnit_D *reg;
  2606. void *dma_coherent2;
  2607. dma_addr_t dma_coherent_handle2;
  2608. struct pci_dev *pdev = acb->pdev;
  2609. acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32);
  2610. dma_coherent2 = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
  2611. &dma_coherent_handle2, GFP_KERNEL);
  2612. if (!dma_coherent2) {
  2613. pr_notice("DMA allocation failed...\n");
  2614. return false;
  2615. }
  2616. memset(dma_coherent2, 0, acb->roundup_ccbsize);
  2617. acb->dma_coherent_handle2 = dma_coherent_handle2;
  2618. acb->dma_coherent2 = dma_coherent2;
  2619. reg = (struct MessageUnit_D *)dma_coherent2;
  2620. acb->pmuD = reg;
  2621. reg->chip_id = acb->mem_base0 + ARCMSR_ARC1214_CHIP_ID;
  2622. reg->cpu_mem_config = acb->mem_base0 +
  2623. ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION;
  2624. reg->i2o_host_interrupt_mask = acb->mem_base0 +
  2625. ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK;
  2626. reg->sample_at_reset = acb->mem_base0 + ARCMSR_ARC1214_SAMPLE_RESET;
  2627. reg->reset_request = acb->mem_base0 + ARCMSR_ARC1214_RESET_REQUEST;
  2628. reg->host_int_status = acb->mem_base0 +
  2629. ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS;
  2630. reg->pcief0_int_enable = acb->mem_base0 +
  2631. ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE;
  2632. reg->inbound_msgaddr0 = acb->mem_base0 +
  2633. ARCMSR_ARC1214_INBOUND_MESSAGE0;
  2634. reg->inbound_msgaddr1 = acb->mem_base0 +
  2635. ARCMSR_ARC1214_INBOUND_MESSAGE1;
  2636. reg->outbound_msgaddr0 = acb->mem_base0 +
  2637. ARCMSR_ARC1214_OUTBOUND_MESSAGE0;
  2638. reg->outbound_msgaddr1 = acb->mem_base0 +
  2639. ARCMSR_ARC1214_OUTBOUND_MESSAGE1;
  2640. reg->inbound_doorbell = acb->mem_base0 +
  2641. ARCMSR_ARC1214_INBOUND_DOORBELL;
  2642. reg->outbound_doorbell = acb->mem_base0 +
  2643. ARCMSR_ARC1214_OUTBOUND_DOORBELL;
  2644. reg->outbound_doorbell_enable = acb->mem_base0 +
  2645. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE;
  2646. reg->inboundlist_base_low = acb->mem_base0 +
  2647. ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW;
  2648. reg->inboundlist_base_high = acb->mem_base0 +
  2649. ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH;
  2650. reg->inboundlist_write_pointer = acb->mem_base0 +
  2651. ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER;
  2652. reg->outboundlist_base_low = acb->mem_base0 +
  2653. ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW;
  2654. reg->outboundlist_base_high = acb->mem_base0 +
  2655. ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH;
  2656. reg->outboundlist_copy_pointer = acb->mem_base0 +
  2657. ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER;
  2658. reg->outboundlist_read_pointer = acb->mem_base0 +
  2659. ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER;
  2660. reg->outboundlist_interrupt_cause = acb->mem_base0 +
  2661. ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE;
  2662. reg->outboundlist_interrupt_enable = acb->mem_base0 +
  2663. ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE;
  2664. reg->message_wbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_WBUFFER;
  2665. reg->message_rbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_RBUFFER;
  2666. reg->msgcode_rwbuffer = acb->mem_base0 +
  2667. ARCMSR_ARC1214_MESSAGE_RWBUFFER;
  2668. iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]);
  2669. iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]);
  2670. iop_device_map = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  2671. if (readl(acb->pmuD->outbound_doorbell) &
  2672. ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  2673. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  2674. acb->pmuD->outbound_doorbell);/*clear interrupt*/
  2675. }
  2676. /* post "get config" instruction */
  2677. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
  2678. /* wait message ready */
  2679. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  2680. pr_notice("arcmsr%d: wait get adapter firmware "
  2681. "miscellaneous data timeout\n", acb->host->host_no);
  2682. dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
  2683. acb->dma_coherent2, acb->dma_coherent_handle2);
  2684. return false;
  2685. }
  2686. count = 8;
  2687. while (count) {
  2688. *acb_firm_model = readb(iop_firm_model);
  2689. acb_firm_model++;
  2690. iop_firm_model++;
  2691. count--;
  2692. }
  2693. count = 16;
  2694. while (count) {
  2695. *acb_firm_version = readb(iop_firm_version);
  2696. acb_firm_version++;
  2697. iop_firm_version++;
  2698. count--;
  2699. }
  2700. count = 16;
  2701. while (count) {
  2702. *acb_device_map = readb(iop_device_map);
  2703. acb_device_map++;
  2704. iop_device_map++;
  2705. count--;
  2706. }
  2707. acb->signature = readl(&reg->msgcode_rwbuffer[1]);
  2708. /*firm_signature,1,00-03*/
  2709. acb->firm_request_len = readl(&reg->msgcode_rwbuffer[2]);
  2710. /*firm_request_len,1,04-07*/
  2711. acb->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[3]);
  2712. /*firm_numbers_queue,2,08-11*/
  2713. acb->firm_sdram_size = readl(&reg->msgcode_rwbuffer[4]);
  2714. /*firm_sdram_size,3,12-15*/
  2715. acb->firm_hd_channels = readl(&reg->msgcode_rwbuffer[5]);
  2716. /*firm_hd_channels,4,16-19*/
  2717. acb->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]);
  2718. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2719. acb->host->host_no,
  2720. acb->firm_model,
  2721. acb->firm_version);
  2722. return true;
  2723. }
  2724. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  2725. {
  2726. bool rtn = false;
  2727. switch (acb->adapter_type) {
  2728. case ACB_ADAPTER_TYPE_A:
  2729. rtn = arcmsr_hbaA_get_config(acb);
  2730. break;
  2731. case ACB_ADAPTER_TYPE_B:
  2732. rtn = arcmsr_hbaB_get_config(acb);
  2733. break;
  2734. case ACB_ADAPTER_TYPE_C:
  2735. rtn = arcmsr_hbaC_get_config(acb);
  2736. break;
  2737. case ACB_ADAPTER_TYPE_D:
  2738. rtn = arcmsr_hbaD_get_config(acb);
  2739. break;
  2740. default:
  2741. break;
  2742. }
  2743. if (acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
  2744. acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD;
  2745. else
  2746. acb->maxOutstanding = acb->firm_numbers_queue - 1;
  2747. acb->host->can_queue = acb->maxOutstanding;
  2748. return rtn;
  2749. }
  2750. static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
  2751. struct CommandControlBlock *poll_ccb)
  2752. {
  2753. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2754. struct CommandControlBlock *ccb;
  2755. struct ARCMSR_CDB *arcmsr_cdb;
  2756. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  2757. int rtn;
  2758. bool error;
  2759. polling_hba_ccb_retry:
  2760. poll_count++;
  2761. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  2762. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  2763. while (1) {
  2764. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  2765. if (poll_ccb_done){
  2766. rtn = SUCCESS;
  2767. break;
  2768. }else {
  2769. msleep(25);
  2770. if (poll_count > 100){
  2771. rtn = FAILED;
  2772. break;
  2773. }
  2774. goto polling_hba_ccb_retry;
  2775. }
  2776. }
  2777. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2778. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2779. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  2780. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2781. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2782. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2783. " poll command abort successfully \n"
  2784. , acb->host->host_no
  2785. , ccb->pcmd->device->id
  2786. , (u32)ccb->pcmd->device->lun
  2787. , ccb);
  2788. ccb->pcmd->result = DID_ABORT << 16;
  2789. arcmsr_ccb_complete(ccb);
  2790. continue;
  2791. }
  2792. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2793. " command done ccb = '0x%p'"
  2794. "ccboutstandingcount = %d \n"
  2795. , acb->host->host_no
  2796. , ccb
  2797. , atomic_read(&acb->ccboutstandingcount));
  2798. continue;
  2799. }
  2800. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2801. arcmsr_report_ccb_state(acb, ccb, error);
  2802. }
  2803. return rtn;
  2804. }
  2805. static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
  2806. struct CommandControlBlock *poll_ccb)
  2807. {
  2808. struct MessageUnit_B *reg = acb->pmuB;
  2809. struct ARCMSR_CDB *arcmsr_cdb;
  2810. struct CommandControlBlock *ccb;
  2811. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  2812. int index, rtn;
  2813. bool error;
  2814. polling_hbb_ccb_retry:
  2815. poll_count++;
  2816. /* clear doorbell interrupt */
  2817. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2818. while(1){
  2819. index = reg->doneq_index;
  2820. flag_ccb = reg->done_qbuffer[index];
  2821. if (flag_ccb == 0) {
  2822. if (poll_ccb_done){
  2823. rtn = SUCCESS;
  2824. break;
  2825. }else {
  2826. msleep(25);
  2827. if (poll_count > 100){
  2828. rtn = FAILED;
  2829. break;
  2830. }
  2831. goto polling_hbb_ccb_retry;
  2832. }
  2833. }
  2834. reg->done_qbuffer[index] = 0;
  2835. index++;
  2836. /*if last index number set it to 0 */
  2837. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  2838. reg->doneq_index = index;
  2839. /* check if command done with no error*/
  2840. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2841. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2842. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  2843. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2844. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2845. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2846. " poll command abort successfully \n"
  2847. ,acb->host->host_no
  2848. ,ccb->pcmd->device->id
  2849. ,(u32)ccb->pcmd->device->lun
  2850. ,ccb);
  2851. ccb->pcmd->result = DID_ABORT << 16;
  2852. arcmsr_ccb_complete(ccb);
  2853. continue;
  2854. }
  2855. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2856. " command done ccb = '0x%p'"
  2857. "ccboutstandingcount = %d \n"
  2858. , acb->host->host_no
  2859. , ccb
  2860. , atomic_read(&acb->ccboutstandingcount));
  2861. continue;
  2862. }
  2863. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2864. arcmsr_report_ccb_state(acb, ccb, error);
  2865. }
  2866. return rtn;
  2867. }
  2868. static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
  2869. struct CommandControlBlock *poll_ccb)
  2870. {
  2871. struct MessageUnit_C __iomem *reg = acb->pmuC;
  2872. uint32_t flag_ccb, ccb_cdb_phy;
  2873. struct ARCMSR_CDB *arcmsr_cdb;
  2874. bool error;
  2875. struct CommandControlBlock *pCCB;
  2876. uint32_t poll_ccb_done = 0, poll_count = 0;
  2877. int rtn;
  2878. polling_hbc_ccb_retry:
  2879. poll_count++;
  2880. while (1) {
  2881. if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
  2882. if (poll_ccb_done) {
  2883. rtn = SUCCESS;
  2884. break;
  2885. } else {
  2886. msleep(25);
  2887. if (poll_count > 100) {
  2888. rtn = FAILED;
  2889. break;
  2890. }
  2891. goto polling_hbc_ccb_retry;
  2892. }
  2893. }
  2894. flag_ccb = readl(&reg->outbound_queueport_low);
  2895. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2896. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  2897. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2898. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  2899. /* check ifcommand done with no error*/
  2900. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  2901. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  2902. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2903. " poll command abort successfully \n"
  2904. , acb->host->host_no
  2905. , pCCB->pcmd->device->id
  2906. , (u32)pCCB->pcmd->device->lun
  2907. , pCCB);
  2908. pCCB->pcmd->result = DID_ABORT << 16;
  2909. arcmsr_ccb_complete(pCCB);
  2910. continue;
  2911. }
  2912. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2913. " command done ccb = '0x%p'"
  2914. "ccboutstandingcount = %d \n"
  2915. , acb->host->host_no
  2916. , pCCB
  2917. , atomic_read(&acb->ccboutstandingcount));
  2918. continue;
  2919. }
  2920. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  2921. arcmsr_report_ccb_state(acb, pCCB, error);
  2922. }
  2923. return rtn;
  2924. }
  2925. static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
  2926. struct CommandControlBlock *poll_ccb)
  2927. {
  2928. bool error;
  2929. uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy;
  2930. int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
  2931. unsigned long flags;
  2932. struct ARCMSR_CDB *arcmsr_cdb;
  2933. struct CommandControlBlock *pCCB;
  2934. struct MessageUnit_D *pmu = acb->pmuD;
  2935. polling_hbaD_ccb_retry:
  2936. poll_count++;
  2937. while (1) {
  2938. spin_lock_irqsave(&acb->doneq_lock, flags);
  2939. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  2940. doneq_index = pmu->doneq_index;
  2941. if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
  2942. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2943. if (poll_ccb_done) {
  2944. rtn = SUCCESS;
  2945. break;
  2946. } else {
  2947. msleep(25);
  2948. if (poll_count > 40) {
  2949. rtn = FAILED;
  2950. break;
  2951. }
  2952. goto polling_hbaD_ccb_retry;
  2953. }
  2954. }
  2955. toggle = doneq_index & 0x4000;
  2956. index_stripped = (doneq_index & 0xFFF) + 1;
  2957. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  2958. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  2959. ((toggle ^ 0x4000) + 1);
  2960. doneq_index = pmu->doneq_index;
  2961. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2962. flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
  2963. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2964. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
  2965. ccb_cdb_phy);
  2966. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
  2967. arcmsr_cdb);
  2968. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  2969. if ((pCCB->acb != acb) ||
  2970. (pCCB->startdone != ARCMSR_CCB_START)) {
  2971. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  2972. pr_notice("arcmsr%d: scsi id = %d "
  2973. "lun = %d ccb = '0x%p' poll command "
  2974. "abort successfully\n"
  2975. , acb->host->host_no
  2976. , pCCB->pcmd->device->id
  2977. , (u32)pCCB->pcmd->device->lun
  2978. , pCCB);
  2979. pCCB->pcmd->result = DID_ABORT << 16;
  2980. arcmsr_ccb_complete(pCCB);
  2981. continue;
  2982. }
  2983. pr_notice("arcmsr%d: polling an illegal "
  2984. "ccb command done ccb = '0x%p' "
  2985. "ccboutstandingcount = %d\n"
  2986. , acb->host->host_no
  2987. , pCCB
  2988. , atomic_read(&acb->ccboutstandingcount));
  2989. continue;
  2990. }
  2991. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  2992. ? true : false;
  2993. arcmsr_report_ccb_state(acb, pCCB, error);
  2994. }
  2995. return rtn;
  2996. }
  2997. static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  2998. struct CommandControlBlock *poll_ccb)
  2999. {
  3000. int rtn = 0;
  3001. switch (acb->adapter_type) {
  3002. case ACB_ADAPTER_TYPE_A: {
  3003. rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
  3004. }
  3005. break;
  3006. case ACB_ADAPTER_TYPE_B: {
  3007. rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
  3008. }
  3009. break;
  3010. case ACB_ADAPTER_TYPE_C: {
  3011. rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
  3012. }
  3013. break;
  3014. case ACB_ADAPTER_TYPE_D:
  3015. rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
  3016. break;
  3017. }
  3018. return rtn;
  3019. }
  3020. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  3021. {
  3022. uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
  3023. dma_addr_t dma_coherent_handle;
  3024. /*
  3025. ********************************************************************
  3026. ** here we need to tell iop 331 our freeccb.HighPart
  3027. ** if freeccb.HighPart is not zero
  3028. ********************************************************************
  3029. */
  3030. switch (acb->adapter_type) {
  3031. case ACB_ADAPTER_TYPE_B:
  3032. case ACB_ADAPTER_TYPE_D:
  3033. dma_coherent_handle = acb->dma_coherent_handle2;
  3034. break;
  3035. default:
  3036. dma_coherent_handle = acb->dma_coherent_handle;
  3037. break;
  3038. }
  3039. cdb_phyaddr = lower_32_bits(dma_coherent_handle);
  3040. cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
  3041. acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
  3042. /*
  3043. ***********************************************************************
  3044. ** if adapter type B, set window of "post command Q"
  3045. ***********************************************************************
  3046. */
  3047. switch (acb->adapter_type) {
  3048. case ACB_ADAPTER_TYPE_A: {
  3049. if (cdb_phyaddr_hi32 != 0) {
  3050. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3051. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  3052. &reg->message_rwbuffer[0]);
  3053. writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  3054. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  3055. &reg->inbound_msgaddr0);
  3056. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3057. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  3058. part physical address timeout\n",
  3059. acb->host->host_no);
  3060. return 1;
  3061. }
  3062. }
  3063. }
  3064. break;
  3065. case ACB_ADAPTER_TYPE_B: {
  3066. uint32_t __iomem *rwbuffer;
  3067. struct MessageUnit_B *reg = acb->pmuB;
  3068. reg->postq_index = 0;
  3069. reg->doneq_index = 0;
  3070. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
  3071. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3072. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  3073. acb->host->host_no);
  3074. return 1;
  3075. }
  3076. rwbuffer = reg->message_rwbuffer;
  3077. /* driver "set config" signature */
  3078. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3079. /* normal should be zero */
  3080. writel(cdb_phyaddr_hi32, rwbuffer++);
  3081. /* postQ size (256 + 8)*4 */
  3082. writel(cdb_phyaddr, rwbuffer++);
  3083. /* doneQ size (256 + 8)*4 */
  3084. writel(cdb_phyaddr + 1056, rwbuffer++);
  3085. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  3086. writel(1056, rwbuffer);
  3087. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
  3088. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3089. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3090. timeout \n",acb->host->host_no);
  3091. return 1;
  3092. }
  3093. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  3094. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3095. pr_err("arcmsr%d: can't set driver mode.\n",
  3096. acb->host->host_no);
  3097. return 1;
  3098. }
  3099. }
  3100. break;
  3101. case ACB_ADAPTER_TYPE_C: {
  3102. if (cdb_phyaddr_hi32 != 0) {
  3103. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3104. printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
  3105. acb->adapter_index, cdb_phyaddr_hi32);
  3106. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  3107. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
  3108. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  3109. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3110. if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
  3111. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3112. timeout \n", acb->host->host_no);
  3113. return 1;
  3114. }
  3115. }
  3116. }
  3117. break;
  3118. case ACB_ADAPTER_TYPE_D: {
  3119. uint32_t __iomem *rwbuffer;
  3120. struct MessageUnit_D *reg = acb->pmuD;
  3121. reg->postq_index = 0;
  3122. reg->doneq_index = 0;
  3123. rwbuffer = reg->msgcode_rwbuffer;
  3124. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3125. writel(cdb_phyaddr_hi32, rwbuffer++);
  3126. writel(cdb_phyaddr, rwbuffer++);
  3127. writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
  3128. sizeof(struct InBound_SRB)), rwbuffer++);
  3129. writel(0x100, rwbuffer);
  3130. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
  3131. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  3132. pr_notice("arcmsr%d: 'set command Q window' timeout\n",
  3133. acb->host->host_no);
  3134. return 1;
  3135. }
  3136. }
  3137. break;
  3138. }
  3139. return 0;
  3140. }
  3141. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  3142. {
  3143. uint32_t firmware_state = 0;
  3144. switch (acb->adapter_type) {
  3145. case ACB_ADAPTER_TYPE_A: {
  3146. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3147. do {
  3148. firmware_state = readl(&reg->outbound_msgaddr1);
  3149. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  3150. }
  3151. break;
  3152. case ACB_ADAPTER_TYPE_B: {
  3153. struct MessageUnit_B *reg = acb->pmuB;
  3154. do {
  3155. firmware_state = readl(reg->iop2drv_doorbell);
  3156. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  3157. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  3158. }
  3159. break;
  3160. case ACB_ADAPTER_TYPE_C: {
  3161. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3162. do {
  3163. firmware_state = readl(&reg->outbound_msgaddr1);
  3164. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  3165. }
  3166. break;
  3167. case ACB_ADAPTER_TYPE_D: {
  3168. struct MessageUnit_D *reg = acb->pmuD;
  3169. do {
  3170. firmware_state = readl(reg->outbound_msgaddr1);
  3171. } while ((firmware_state &
  3172. ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
  3173. }
  3174. break;
  3175. }
  3176. }
  3177. static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb)
  3178. {
  3179. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3180. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  3181. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3182. return;
  3183. } else {
  3184. acb->fw_flag = FW_NORMAL;
  3185. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
  3186. atomic_set(&acb->rq_map_token, 16);
  3187. }
  3188. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  3189. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3190. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3191. return;
  3192. }
  3193. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3194. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3195. }
  3196. return;
  3197. }
  3198. static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb)
  3199. {
  3200. struct MessageUnit_B *reg = acb->pmuB;
  3201. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  3202. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3203. return;
  3204. } else {
  3205. acb->fw_flag = FW_NORMAL;
  3206. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  3207. atomic_set(&acb->rq_map_token, 16);
  3208. }
  3209. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  3210. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3211. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3212. return;
  3213. }
  3214. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  3215. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3216. }
  3217. return;
  3218. }
  3219. static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb)
  3220. {
  3221. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3222. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
  3223. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3224. return;
  3225. } else {
  3226. acb->fw_flag = FW_NORMAL;
  3227. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  3228. atomic_set(&acb->rq_map_token, 16);
  3229. }
  3230. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  3231. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3232. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3233. return;
  3234. }
  3235. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3236. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3237. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3238. }
  3239. return;
  3240. }
  3241. static void arcmsr_hbaD_request_device_map(struct AdapterControlBlock *acb)
  3242. {
  3243. struct MessageUnit_D *reg = acb->pmuD;
  3244. if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
  3245. ((acb->acb_flags & ACB_F_BUS_RESET) != 0) ||
  3246. ((acb->acb_flags & ACB_F_ABORT) != 0)) {
  3247. mod_timer(&acb->eternal_timer,
  3248. jiffies + msecs_to_jiffies(6 * HZ));
  3249. } else {
  3250. acb->fw_flag = FW_NORMAL;
  3251. if (atomic_read(&acb->ante_token_value) ==
  3252. atomic_read(&acb->rq_map_token)) {
  3253. atomic_set(&acb->rq_map_token, 16);
  3254. }
  3255. atomic_set(&acb->ante_token_value,
  3256. atomic_read(&acb->rq_map_token));
  3257. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3258. mod_timer(&acb->eternal_timer, jiffies +
  3259. msecs_to_jiffies(6 * HZ));
  3260. return;
  3261. }
  3262. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG,
  3263. reg->inbound_msgaddr0);
  3264. mod_timer(&acb->eternal_timer, jiffies +
  3265. msecs_to_jiffies(6 * HZ));
  3266. }
  3267. }
  3268. static void arcmsr_request_device_map(unsigned long pacb)
  3269. {
  3270. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
  3271. switch (acb->adapter_type) {
  3272. case ACB_ADAPTER_TYPE_A: {
  3273. arcmsr_hbaA_request_device_map(acb);
  3274. }
  3275. break;
  3276. case ACB_ADAPTER_TYPE_B: {
  3277. arcmsr_hbaB_request_device_map(acb);
  3278. }
  3279. break;
  3280. case ACB_ADAPTER_TYPE_C: {
  3281. arcmsr_hbaC_request_device_map(acb);
  3282. }
  3283. break;
  3284. case ACB_ADAPTER_TYPE_D:
  3285. arcmsr_hbaD_request_device_map(acb);
  3286. break;
  3287. }
  3288. }
  3289. static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
  3290. {
  3291. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3292. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3293. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  3294. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3295. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3296. rebulid' timeout \n", acb->host->host_no);
  3297. }
  3298. }
  3299. static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
  3300. {
  3301. struct MessageUnit_B *reg = acb->pmuB;
  3302. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3303. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
  3304. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3305. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3306. rebulid' timeout \n",acb->host->host_no);
  3307. }
  3308. }
  3309. static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
  3310. {
  3311. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  3312. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3313. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
  3314. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
  3315. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  3316. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3317. rebulid' timeout \n", pACB->host->host_no);
  3318. }
  3319. return;
  3320. }
  3321. static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
  3322. {
  3323. struct MessageUnit_D *pmu = pACB->pmuD;
  3324. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3325. writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
  3326. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  3327. pr_notice("arcmsr%d: wait 'start adapter "
  3328. "background rebulid' timeout\n", pACB->host->host_no);
  3329. }
  3330. }
  3331. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  3332. {
  3333. switch (acb->adapter_type) {
  3334. case ACB_ADAPTER_TYPE_A:
  3335. arcmsr_hbaA_start_bgrb(acb);
  3336. break;
  3337. case ACB_ADAPTER_TYPE_B:
  3338. arcmsr_hbaB_start_bgrb(acb);
  3339. break;
  3340. case ACB_ADAPTER_TYPE_C:
  3341. arcmsr_hbaC_start_bgrb(acb);
  3342. break;
  3343. case ACB_ADAPTER_TYPE_D:
  3344. arcmsr_hbaD_start_bgrb(acb);
  3345. break;
  3346. }
  3347. }
  3348. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  3349. {
  3350. switch (acb->adapter_type) {
  3351. case ACB_ADAPTER_TYPE_A: {
  3352. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3353. uint32_t outbound_doorbell;
  3354. /* empty doorbell Qbuffer if door bell ringed */
  3355. outbound_doorbell = readl(&reg->outbound_doorbell);
  3356. /*clear doorbell interrupt */
  3357. writel(outbound_doorbell, &reg->outbound_doorbell);
  3358. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  3359. }
  3360. break;
  3361. case ACB_ADAPTER_TYPE_B: {
  3362. struct MessageUnit_B *reg = acb->pmuB;
  3363. /*clear interrupt and message state*/
  3364. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  3365. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  3366. /* let IOP know data has been read */
  3367. }
  3368. break;
  3369. case ACB_ADAPTER_TYPE_C: {
  3370. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3371. uint32_t outbound_doorbell, i;
  3372. /* empty doorbell Qbuffer if door bell ringed */
  3373. outbound_doorbell = readl(&reg->outbound_doorbell);
  3374. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  3375. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  3376. for (i = 0; i < 200; i++) {
  3377. msleep(20);
  3378. outbound_doorbell = readl(&reg->outbound_doorbell);
  3379. if (outbound_doorbell &
  3380. ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
  3381. writel(outbound_doorbell,
  3382. &reg->outbound_doorbell_clear);
  3383. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
  3384. &reg->inbound_doorbell);
  3385. } else
  3386. break;
  3387. }
  3388. }
  3389. break;
  3390. case ACB_ADAPTER_TYPE_D: {
  3391. struct MessageUnit_D *reg = acb->pmuD;
  3392. uint32_t outbound_doorbell, i;
  3393. /* empty doorbell Qbuffer if door bell ringed */
  3394. outbound_doorbell = readl(reg->outbound_doorbell);
  3395. writel(outbound_doorbell, reg->outbound_doorbell);
  3396. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  3397. reg->inbound_doorbell);
  3398. for (i = 0; i < 200; i++) {
  3399. msleep(20);
  3400. outbound_doorbell = readl(reg->outbound_doorbell);
  3401. if (outbound_doorbell &
  3402. ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
  3403. writel(outbound_doorbell,
  3404. reg->outbound_doorbell);
  3405. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  3406. reg->inbound_doorbell);
  3407. } else
  3408. break;
  3409. }
  3410. }
  3411. break;
  3412. }
  3413. }
  3414. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  3415. {
  3416. switch (acb->adapter_type) {
  3417. case ACB_ADAPTER_TYPE_A:
  3418. return;
  3419. case ACB_ADAPTER_TYPE_B:
  3420. {
  3421. struct MessageUnit_B *reg = acb->pmuB;
  3422. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
  3423. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3424. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  3425. return;
  3426. }
  3427. }
  3428. break;
  3429. case ACB_ADAPTER_TYPE_C:
  3430. return;
  3431. }
  3432. return;
  3433. }
  3434. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
  3435. {
  3436. uint8_t value[64];
  3437. int i, count = 0;
  3438. struct MessageUnit_A __iomem *pmuA = acb->pmuA;
  3439. struct MessageUnit_C __iomem *pmuC = acb->pmuC;
  3440. struct MessageUnit_D *pmuD = acb->pmuD;
  3441. /* backup pci config data */
  3442. printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
  3443. for (i = 0; i < 64; i++) {
  3444. pci_read_config_byte(acb->pdev, i, &value[i]);
  3445. }
  3446. /* hardware reset signal */
  3447. if ((acb->dev_id == 0x1680)) {
  3448. writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
  3449. } else if ((acb->dev_id == 0x1880)) {
  3450. do {
  3451. count++;
  3452. writel(0xF, &pmuC->write_sequence);
  3453. writel(0x4, &pmuC->write_sequence);
  3454. writel(0xB, &pmuC->write_sequence);
  3455. writel(0x2, &pmuC->write_sequence);
  3456. writel(0x7, &pmuC->write_sequence);
  3457. writel(0xD, &pmuC->write_sequence);
  3458. } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
  3459. writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
  3460. } else if ((acb->dev_id == 0x1214)) {
  3461. writel(0x20, pmuD->reset_request);
  3462. } else {
  3463. pci_write_config_byte(acb->pdev, 0x84, 0x20);
  3464. }
  3465. msleep(2000);
  3466. /* write back pci config data */
  3467. for (i = 0; i < 64; i++) {
  3468. pci_write_config_byte(acb->pdev, i, value[i]);
  3469. }
  3470. msleep(1000);
  3471. return;
  3472. }
  3473. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  3474. {
  3475. uint32_t intmask_org;
  3476. /* disable all outbound interrupt */
  3477. intmask_org = arcmsr_disable_outbound_ints(acb);
  3478. arcmsr_wait_firmware_ready(acb);
  3479. arcmsr_iop_confirm(acb);
  3480. /*start background rebuild*/
  3481. arcmsr_start_adapter_bgrb(acb);
  3482. /* empty doorbell Qbuffer if door bell ringed */
  3483. arcmsr_clear_doorbell_queue_buffer(acb);
  3484. arcmsr_enable_eoi_mode(acb);
  3485. /* enable outbound Post Queue,outbound doorbell Interrupt */
  3486. arcmsr_enable_outbound_ints(acb, intmask_org);
  3487. acb->acb_flags |= ACB_F_IOP_INITED;
  3488. }
  3489. static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
  3490. {
  3491. struct CommandControlBlock *ccb;
  3492. uint32_t intmask_org;
  3493. uint8_t rtnval = 0x00;
  3494. int i = 0;
  3495. unsigned long flags;
  3496. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  3497. /* disable all outbound interrupt */
  3498. intmask_org = arcmsr_disable_outbound_ints(acb);
  3499. /* talk to iop 331 outstanding command aborted */
  3500. rtnval = arcmsr_abort_allcmd(acb);
  3501. /* clear all outbound posted Q */
  3502. arcmsr_done4abort_postqueue(acb);
  3503. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  3504. ccb = acb->pccb_pool[i];
  3505. if (ccb->startdone == ARCMSR_CCB_START) {
  3506. scsi_dma_unmap(ccb->pcmd);
  3507. ccb->startdone = ARCMSR_CCB_DONE;
  3508. ccb->ccb_flags = 0;
  3509. spin_lock_irqsave(&acb->ccblist_lock, flags);
  3510. list_add_tail(&ccb->list, &acb->ccb_free_list);
  3511. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  3512. }
  3513. }
  3514. atomic_set(&acb->ccboutstandingcount, 0);
  3515. /* enable all outbound interrupt */
  3516. arcmsr_enable_outbound_ints(acb, intmask_org);
  3517. return rtnval;
  3518. }
  3519. return rtnval;
  3520. }
  3521. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  3522. {
  3523. struct AdapterControlBlock *acb;
  3524. uint32_t intmask_org, outbound_doorbell;
  3525. int retry_count = 0;
  3526. int rtn = FAILED;
  3527. acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
  3528. printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
  3529. acb->num_resets++;
  3530. switch(acb->adapter_type){
  3531. case ACB_ADAPTER_TYPE_A:{
  3532. if (acb->acb_flags & ACB_F_BUS_RESET){
  3533. long timeout;
  3534. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  3535. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  3536. if (timeout) {
  3537. return SUCCESS;
  3538. }
  3539. }
  3540. acb->acb_flags |= ACB_F_BUS_RESET;
  3541. if (!arcmsr_iop_reset(acb)) {
  3542. struct MessageUnit_A __iomem *reg;
  3543. reg = acb->pmuA;
  3544. arcmsr_hardware_reset(acb);
  3545. acb->acb_flags &= ~ACB_F_IOP_INITED;
  3546. sleep_again:
  3547. ssleep(ARCMSR_SLEEPTIME);
  3548. if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
  3549. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
  3550. if (retry_count > ARCMSR_RETRYCOUNT) {
  3551. acb->fw_flag = FW_DEADLOCK;
  3552. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
  3553. return FAILED;
  3554. }
  3555. retry_count++;
  3556. goto sleep_again;
  3557. }
  3558. acb->acb_flags |= ACB_F_IOP_INITED;
  3559. /* disable all outbound interrupt */
  3560. intmask_org = arcmsr_disable_outbound_ints(acb);
  3561. arcmsr_get_firmware_spec(acb);
  3562. arcmsr_start_adapter_bgrb(acb);
  3563. /* clear Qbuffer if door bell ringed */
  3564. outbound_doorbell = readl(&reg->outbound_doorbell);
  3565. writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
  3566. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  3567. /* enable outbound Post Queue,outbound doorbell Interrupt */
  3568. arcmsr_enable_outbound_ints(acb, intmask_org);
  3569. atomic_set(&acb->rq_map_token, 16);
  3570. atomic_set(&acb->ante_token_value, 16);
  3571. acb->fw_flag = FW_NORMAL;
  3572. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3573. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3574. rtn = SUCCESS;
  3575. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  3576. } else {
  3577. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3578. atomic_set(&acb->rq_map_token, 16);
  3579. atomic_set(&acb->ante_token_value, 16);
  3580. acb->fw_flag = FW_NORMAL;
  3581. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  3582. rtn = SUCCESS;
  3583. }
  3584. break;
  3585. }
  3586. case ACB_ADAPTER_TYPE_B:{
  3587. acb->acb_flags |= ACB_F_BUS_RESET;
  3588. if (!arcmsr_iop_reset(acb)) {
  3589. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3590. rtn = FAILED;
  3591. } else {
  3592. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3593. atomic_set(&acb->rq_map_token, 16);
  3594. atomic_set(&acb->ante_token_value, 16);
  3595. acb->fw_flag = FW_NORMAL;
  3596. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3597. rtn = SUCCESS;
  3598. }
  3599. break;
  3600. }
  3601. case ACB_ADAPTER_TYPE_C:{
  3602. if (acb->acb_flags & ACB_F_BUS_RESET) {
  3603. long timeout;
  3604. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  3605. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  3606. if (timeout) {
  3607. return SUCCESS;
  3608. }
  3609. }
  3610. acb->acb_flags |= ACB_F_BUS_RESET;
  3611. if (!arcmsr_iop_reset(acb)) {
  3612. struct MessageUnit_C __iomem *reg;
  3613. reg = acb->pmuC;
  3614. arcmsr_hardware_reset(acb);
  3615. acb->acb_flags &= ~ACB_F_IOP_INITED;
  3616. sleep:
  3617. ssleep(ARCMSR_SLEEPTIME);
  3618. if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
  3619. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
  3620. if (retry_count > ARCMSR_RETRYCOUNT) {
  3621. acb->fw_flag = FW_DEADLOCK;
  3622. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
  3623. return FAILED;
  3624. }
  3625. retry_count++;
  3626. goto sleep;
  3627. }
  3628. acb->acb_flags |= ACB_F_IOP_INITED;
  3629. /* disable all outbound interrupt */
  3630. intmask_org = arcmsr_disable_outbound_ints(acb);
  3631. arcmsr_get_firmware_spec(acb);
  3632. arcmsr_start_adapter_bgrb(acb);
  3633. /* clear Qbuffer if door bell ringed */
  3634. arcmsr_clear_doorbell_queue_buffer(acb);
  3635. /* enable outbound Post Queue,outbound doorbell Interrupt */
  3636. arcmsr_enable_outbound_ints(acb, intmask_org);
  3637. atomic_set(&acb->rq_map_token, 16);
  3638. atomic_set(&acb->ante_token_value, 16);
  3639. acb->fw_flag = FW_NORMAL;
  3640. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3641. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3642. rtn = SUCCESS;
  3643. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  3644. } else {
  3645. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3646. atomic_set(&acb->rq_map_token, 16);
  3647. atomic_set(&acb->ante_token_value, 16);
  3648. acb->fw_flag = FW_NORMAL;
  3649. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  3650. rtn = SUCCESS;
  3651. }
  3652. break;
  3653. }
  3654. case ACB_ADAPTER_TYPE_D: {
  3655. if (acb->acb_flags & ACB_F_BUS_RESET) {
  3656. long timeout;
  3657. pr_notice("arcmsr: there is an bus reset"
  3658. " eh proceeding.......\n");
  3659. timeout = wait_event_timeout(wait_q, (acb->acb_flags
  3660. & ACB_F_BUS_RESET) == 0, 220 * HZ);
  3661. if (timeout)
  3662. return SUCCESS;
  3663. }
  3664. acb->acb_flags |= ACB_F_BUS_RESET;
  3665. if (!arcmsr_iop_reset(acb)) {
  3666. struct MessageUnit_D *reg;
  3667. reg = acb->pmuD;
  3668. arcmsr_hardware_reset(acb);
  3669. acb->acb_flags &= ~ACB_F_IOP_INITED;
  3670. nap:
  3671. ssleep(ARCMSR_SLEEPTIME);
  3672. if ((readl(reg->sample_at_reset) & 0x80) != 0) {
  3673. pr_err("arcmsr%d: waiting for "
  3674. "hw bus reset return, retry=%d\n",
  3675. acb->host->host_no, retry_count);
  3676. if (retry_count > ARCMSR_RETRYCOUNT) {
  3677. acb->fw_flag = FW_DEADLOCK;
  3678. pr_err("arcmsr%d: waiting for hw bus"
  3679. " reset return, "
  3680. "RETRY TERMINATED!!\n",
  3681. acb->host->host_no);
  3682. return FAILED;
  3683. }
  3684. retry_count++;
  3685. goto nap;
  3686. }
  3687. acb->acb_flags |= ACB_F_IOP_INITED;
  3688. /* disable all outbound interrupt */
  3689. intmask_org = arcmsr_disable_outbound_ints(acb);
  3690. arcmsr_get_firmware_spec(acb);
  3691. arcmsr_start_adapter_bgrb(acb);
  3692. arcmsr_clear_doorbell_queue_buffer(acb);
  3693. arcmsr_enable_outbound_ints(acb, intmask_org);
  3694. atomic_set(&acb->rq_map_token, 16);
  3695. atomic_set(&acb->ante_token_value, 16);
  3696. acb->fw_flag = FW_NORMAL;
  3697. mod_timer(&acb->eternal_timer,
  3698. jiffies + msecs_to_jiffies(6 * HZ));
  3699. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3700. rtn = SUCCESS;
  3701. pr_err("arcmsr: scsi bus reset "
  3702. "eh returns with success\n");
  3703. } else {
  3704. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3705. atomic_set(&acb->rq_map_token, 16);
  3706. atomic_set(&acb->ante_token_value, 16);
  3707. acb->fw_flag = FW_NORMAL;
  3708. mod_timer(&acb->eternal_timer,
  3709. jiffies + msecs_to_jiffies(6 * HZ));
  3710. rtn = SUCCESS;
  3711. }
  3712. break;
  3713. }
  3714. }
  3715. return rtn;
  3716. }
  3717. static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  3718. struct CommandControlBlock *ccb)
  3719. {
  3720. int rtn;
  3721. rtn = arcmsr_polling_ccbdone(acb, ccb);
  3722. return rtn;
  3723. }
  3724. static int arcmsr_abort(struct scsi_cmnd *cmd)
  3725. {
  3726. struct AdapterControlBlock *acb =
  3727. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  3728. int i = 0;
  3729. int rtn = FAILED;
  3730. uint32_t intmask_org;
  3731. printk(KERN_NOTICE
  3732. "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
  3733. acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
  3734. acb->acb_flags |= ACB_F_ABORT;
  3735. acb->num_aborts++;
  3736. /*
  3737. ************************************************
  3738. ** the all interrupt service routine is locked
  3739. ** we need to handle it as soon as possible and exit
  3740. ************************************************
  3741. */
  3742. if (!atomic_read(&acb->ccboutstandingcount)) {
  3743. acb->acb_flags &= ~ACB_F_ABORT;
  3744. return rtn;
  3745. }
  3746. intmask_org = arcmsr_disable_outbound_ints(acb);
  3747. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  3748. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  3749. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  3750. ccb->startdone = ARCMSR_CCB_ABORTED;
  3751. rtn = arcmsr_abort_one_cmd(acb, ccb);
  3752. break;
  3753. }
  3754. }
  3755. acb->acb_flags &= ~ACB_F_ABORT;
  3756. arcmsr_enable_outbound_ints(acb, intmask_org);
  3757. return rtn;
  3758. }
  3759. static const char *arcmsr_info(struct Scsi_Host *host)
  3760. {
  3761. struct AdapterControlBlock *acb =
  3762. (struct AdapterControlBlock *) host->hostdata;
  3763. static char buf[256];
  3764. char *type;
  3765. int raid6 = 1;
  3766. switch (acb->pdev->device) {
  3767. case PCI_DEVICE_ID_ARECA_1110:
  3768. case PCI_DEVICE_ID_ARECA_1200:
  3769. case PCI_DEVICE_ID_ARECA_1202:
  3770. case PCI_DEVICE_ID_ARECA_1210:
  3771. raid6 = 0;
  3772. /*FALLTHRU*/
  3773. case PCI_DEVICE_ID_ARECA_1120:
  3774. case PCI_DEVICE_ID_ARECA_1130:
  3775. case PCI_DEVICE_ID_ARECA_1160:
  3776. case PCI_DEVICE_ID_ARECA_1170:
  3777. case PCI_DEVICE_ID_ARECA_1201:
  3778. case PCI_DEVICE_ID_ARECA_1220:
  3779. case PCI_DEVICE_ID_ARECA_1230:
  3780. case PCI_DEVICE_ID_ARECA_1260:
  3781. case PCI_DEVICE_ID_ARECA_1270:
  3782. case PCI_DEVICE_ID_ARECA_1280:
  3783. type = "SATA";
  3784. break;
  3785. case PCI_DEVICE_ID_ARECA_1214:
  3786. case PCI_DEVICE_ID_ARECA_1380:
  3787. case PCI_DEVICE_ID_ARECA_1381:
  3788. case PCI_DEVICE_ID_ARECA_1680:
  3789. case PCI_DEVICE_ID_ARECA_1681:
  3790. case PCI_DEVICE_ID_ARECA_1880:
  3791. type = "SAS/SATA";
  3792. break;
  3793. default:
  3794. type = "unknown";
  3795. raid6 = 0;
  3796. break;
  3797. }
  3798. sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
  3799. type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
  3800. return buf;
  3801. }